: gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; richard.guent...@gmail.com; tamar.christ...@arm.com;
juzhe.zh...@rivai.ai; Li, Pan2 ; jeffreya...@gmail.com;
rdapp@gmail.com; panciyan
Subject: [PATCH] RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and
form 9
From: panciyan
This patch add
cture and conditionalize the appropriate
> code.
I see, thanks Jeff.
Pan
-Original Message-
From: Jeff Law
Sent: Friday, July 18, 2025 1:23 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com; Chen, Ken
; Liu, Hongtao
Subject:
t: Thursday, July 17, 2025 4:10 PM
To: gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; richard.guent...@gmail.com; tamar.christ...@arm.com;
juzhe.zh...@rivai.ai; Li, Pan2 ; jeffreya...@gmail.com;
rdapp@gmail.com; panciyan
Subject: [PATCH] RISC-V: Add testcase for unsigned scalar SAT_ADD form 8
Seems the test is not that correct for DImode, will send v2 for this change.
/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i128.c
Pan
-Original Message-
From: Li, Pan2
Sent: Tuesday, July 15, 2025 10:45 AM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai
if hit the SAT IFN code-gen, there should be branchless, and for the
Correctness of code-gen, we have run test to take care of it.
Pan
-Original Message-
From: Jeff Law
Sent: Monday, July 14, 2025 8:37 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com
Pan
-Original Message-
From: Richard Biener
Sent: Friday, July 11, 2025 4:49 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya...@gmail.com; rdapp@gmail.com; Chen, Ken ;
Liu, Hongtao
Subject: Re: [PATCH v1 1/2] Match: Leverage BITS_PER
r it will be a normal mul, then looks we don't need to check that anymore, am
I understanding correct?
Pan
-Original Message-
From: Richard Biener
Sent: Friday, July 11, 2025 2:23 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya...
Ok, thanks.
Pan
-Original Message-
From: Ciyan Pan
Sent: Friday, July 11, 2025 10:35 AM
To: gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; richard.guent...@gmail.com; tamar.christ...@arm.com;
juzhe.zh...@rivai.ai; Li, Pan2 ; jeffreya...@gmail.com;
rdapp@gmail.com; panciyan
day, July 10, 2025 3:14 PM
To: gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; richard.guent...@gmail.com; tamar.christ...@arm.com;
juzhe.zh...@rivai.ai; Li, Pan2 ; jeffreya...@gmail.com;
rdapp@gmail.com; panciyan
Subject: [PATCH] RISC-V: Add testcases for unsigned vector SAT_SUB form 11
I see, thanks Jeff, just rerun it locally without new failures, will commit It
soon.
Pan
-Original Message-
From: Jeff Law
Sent: Thursday, July 10, 2025 9:22 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com; Chen, Ken
; Liu
7;?
compiler exited with status 1
FAIL: gcc.target/riscv/sat/sat_u_sub-run-4-u32.c -O3 (test for excess errors)
Pan
-Original Message-
From: Jeff Law
Sent: Wednesday, July 9, 2025 11:47 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp
Thanks Jeff and Kito, LGTM.
Pan
-Original Message-
From: Jeff Law
Sent: Wednesday, July 9, 2025 10:33 PM
To: Ciyan Pan ; gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; richard.guent...@gmail.com; tamar.christ...@arm.com;
juzhe.zh...@rivai.ai; Li, Pan2 ; rdapp@gmail.com
Subject
-strided-a-u8-i2-gap.c -flto -ffat-lto-objects
scan-tree-dump-times vect "vectorized 2 loops" 1
Pan
-Original Message-
From: Robin Dapp
Sent: Wednesday, July 9, 2025 3:10 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya.
> It looks like there's ~200 uses of risc_v in dg-do run clauses in the
> "sat" subdirectory tests. Should those be adjusted as well?
Yes, I will take care of that soon.
Pan
-Original Message-
From: Jeff Law
Sent: Tuesday, July 8, 2025 9:47 PM
To: Li, Pan2 ; gc
> Is that correct? Don't you need to be testing that the platform has
> vector in addition to being rv64?
It is riscv.exp test, so I think vector extension is not required here.
Pan
-Original Message-
From: Jeff Law
Sent: Tuesday, July 8, 2025 11:45 AM
To: Li, Pan2 ;
juzhe.zh...@rivai.ai; Li, Pan2 ; jeffreya...@gmail.com;
rdapp@gmail.com; panciyan
Subject: [PATCH] RISC-V: Add testcases for unsigned vector SAT_SUB form 11 and
form 12
From: panciyan
This patch adds testcase for form11 and form12, as shown below:
void __a
I see, thanks a lot.
Pan
-Original Message-
From: Jeff Law
Sent: Monday, July 7, 2025 10:38 AM
To: Li, Pan2 ; Robin Dapp ;
gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; Chen, Ken ;
Liu, Hongtao
Subject: Re: [PATCH v3 3/4] RISC-V: Implement unsigned scalar
aw
Sent: Saturday, July 5, 2025 9:46 AM
To: Robin Dapp ; Li, Pan2 ;
gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; Chen, Ken ;
Liu, Hongtao
Subject: Re: [PATCH v3 3/4] RISC-V: Implement unsigned scalar SAT_MUL from
uint128_t
On 7/4/25 1:18 PM, Robin Dapp wrote:
> T
PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya...@gmail.com; rdapp@gmail.com; Chen, Ken ;
Liu, Hongtao
Subject: Re: [PATCH v3 1/4] Internal-fn: Introduce new IFN_SAT_MUL for unsigned
int
On Wed, Jul 2, 2025 at 7:31 AM wrote:
>
>
2:19 PM
To: gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; richard.guent...@gmail.com; tamar.christ...@arm.com;
juzhe.zh...@rivai.ai; Li, Pan2 ; jeffreya...@gmail.com;
rdapp@gmail.com; panciyan
Subject: [PATCH v2 2/2] RISC-V: Add testcases for signed scalar SAT_ADD IMM
form 2
From: pan
ostics-plain-output -O0 -mrvv-vector-bits=scalable -march=rv32gcv
-mabi=ilp32 -fno-tree-vectorize -ffat-lto-objects -fno-ident -S -o
vlmax_complex_loop-1.s
PASS: gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c -O0 (test for
excess errors)
Pan
-Original Message-
From: Li, Pan2
Se
It is better to leave a record in CI system, I will send v3 to trigger another
CI and see, will commit it if CI is OK.
Pan
-Original Message-
From: Robin Dapp
Sent: Friday, June 27, 2025 9:53 PM
To: Li, Pan2 ; Robin Dapp ;
gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch
Message-
From: Robin Dapp
Sent: Friday, June 27, 2025 9:08 PM
To: Robin Dapp ; Li, Pan2 ;
gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; Chen,
Ken ; Liu, Hongtao ; Robin Dapp
Subject: Re: [PATCH v2 0/4] RISC-V: Combine vec_duplicate + vssubu.vv to
> > + DEF_VX_BINARY_CASE_2_WRAP(T, SAT_U_SUB_FUNC(T), sat_add) \
> Shouldn't that be sat_sub here?
Oh, Yes, should be sat_sub, but happen to work for test, let me update it in
v2.
Pan
-Original Message-
From: Robin Dapp
Sent: Friday, June 27, 2025 2:37 PM
To:
hes@gcc.gnu.org
Cc: kito.ch...@gmail.com; richard.guent...@gmail.com; tamar.christ...@arm.com;
juzhe.zh...@rivai.ai; Li, Pan2 ; jeffreya...@gmail.com;
rdapp@gmail.com; panciyan
Subject: [PATCH 2/2] RISC-V: Add testcases for signed scalar SAT_ADD IMM form 2
From: panciyan
This patch adds testcase
m: Jeff Law
Sent: Wednesday, June 25, 2025 5:30 AM
To: Ciyan Pan ; gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; richard.guent...@gmail.com; tamar.christ...@arm.com;
juzhe.zh...@rivai.ai; Li, Pan2 ; rdapp@gmail.com
Subject: Re: [PATCH 2/2] RISC-V: Add testcases for signed scalar SAT_ADD
, June 23, 2025 2:27 PM
To: gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; richard.guent...@gmail.com; tamar.christ...@arm.com;
juzhe.zh...@rivai.ai; Li, Pan2 ; jeffreya...@gmail.com;
rdapp@gmail.com; panciyan
Subject: [PATCH] Match:Support for signed scalar SAT_ADD IMM form 2
From
I see, thanks Jeff, will make sure the online CI is OK before commit.
Pan
-Original Message-
From: Jeff Law
Sent: Saturday, June 21, 2025 10:32 PM
To: Robin Dapp ; Li, Pan2 ;
gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; Chen, Ken ;
Liu, Hongtao
Subject: Re
> Does immediate_operand () work instead of a new predicate?
Thanks Robin, the immediate_operand works well here, let me send v2 if no
surprise from test.
Pan
-Original Message-
From: Robin Dapp
Sent: Friday, June 20, 2025 5:29 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe
day, June 12, 2025 11:22 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com; Chen, Ken
; Liu, Hongtao
Subject: Re: [PATCH v1 0/5] RISC-V: Combine vec_duplicate + vmax.vv to vmax.vx
on GR2VR cost
On 6/11/25 9:12 PM, pan2...@intel.
> OK. ANd if there's a vremu variant in the works that looks basically
> the same from an implementation standpoint, then consider it
> pre-approved as well.
Thanks Jeff, will commit if CI is Ok.
Pan
-Original Message-
From: Jeff Law
Sent: Sunday, June 8, 2025 10:39 P
fixed after test is OK.
I am not very sure it worked before but looks the avg_floor series has the
same test results as avg_ceil.
Pan
-Original Message-
From: Robin Dapp
Sent: Friday, May 30, 2025 9:48 PM
To: Li, Pan2 ; Robin Dapp ;
gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai;
Pan
-Original Message-
From: Li, Pan2
Sent: Friday, May 30, 2025 9:11 PM
To: Robin Dapp ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; Chen,
Ken ; Liu, Hongtao
Subject: RE: [PATCH v1 0/3] Refine the avg_ceil with fixed point vaadd
> The CI s
From: Robin Dapp
Sent: Friday, May 30, 2025 3:42 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com;
rdapp@gmail.com; Chen, Ken ; Liu, Hongtao
; Robin Dapp
Subject: Re: [PATCH v1 0/3] Refine the avg_ceil with fixed point vaadd
Tuesday, May 27, 2025 2:27 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com;
rdapp@gmail.com; Chen, Ken ; Liu, Hongtao
; and...@sifive.com; Robin Dapp
Subject: Re: [PATCH v1 1/3] RISC-V: Leverage vaadd.vv for signed
:06 AM
To: Li Xu ; gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; richard.guent...@gmail.com; tamar.christ...@arm.com;
juzhe.zh...@rivai.ai; Li, Pan2
Subject: Re: [PATCH 2/2] RISC-V: Add testcases for signed vector SAT_ADD IMM
form 1
On 5/19/25 2:42 AM, Li Xu wrote:
> From: xuli
>
>
day, May 21, 2025 2:05 AM
To: Li Xu ; gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; richard.guent...@gmail.com; tamar.christ...@arm.com;
juzhe.zh...@rivai.ai; Li, Pan2
Subject: Re: [PATCH 2/2] RISC-V:Add testcases for signed .SAT_ADD IMM form 1
with IMM = -1.
On 5/19/25 2:41 AM, Li Xu w
> The series LGTM. I didn't check all the tests in detail to be honest :)
Thanks Robin, the tests is similar and expected up to a point.
Pan
-Original Message-
From: Robin Dapp
Sent: Monday, May 19, 2025 7:06 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@
> Excuse the delay, I was attending the RISC-V Summit Europe.
Thanks Robin, and never mind.
Pan
-Original Message-
From: Robin Dapp
Sent: Friday, May 16, 2025 3:26 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com;
rd
ot;vx_binary.h"
+
+DEF_VX_BINARY_CASE_0(int32_t, +)
+DEF_VX_BINARY_CASE_0(int32_t, -)
+
+/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
If that is ok, I will start with this series.
Pan
-Original Message-
From: Robin Dapp
Sent: Mon
Thanks Richard.
> I think it's enough to put :c on one of the (plus
> OK with that change.
Oh, yes, will commit if no surprise from test for this change.
Pan
-Original Message-
From: Richard Biener
Sent: Monday, May 12, 2025 2:57 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.or
> OK, understood. I think that's expected given the fine granularity of the
> tests. IMHO nothing that should block progress.
Thanks Robin, then we can move to other vx/vf insns.
Pan
-Original Message-
From: Robin Dapp
Sent: Thursday, May 8, 2025 11:44 PM
To: Li, Pan2 ;
_binary.h"
+
+DEF_VX_BINARY_CASE_1(int64_t, +, VX_BINARY_BODY)
+
+/* { dg-final { scan-assembler-not {vadd.vx} } } */
Pan
-----Original Message-
From: Robin Dapp
Sent: Thursday, May 8, 2025 8:01 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffr
sive rtx_cost once all the follow ups are
> in.
Sure thing.
Pan
-Original Message-
From: Robin Dapp
Sent: Tuesday, May 6, 2025 8:17 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com;
rdapp@gmail.com; Chen, Ken ; L
Thanks Jeff.
> Make sure to include a function comment in the final patch. Otherwise
> nothing to add above and beyond Robin's comments.
Sure thing, will add comments for the helper.
Pan
-Original Message-
From: Jeff Law
Sent: Monday, May 5, 2025 9:42 PM
To: Li, Pan2 ;
I see, shall we rename all GR to GPR? I mean we have GR2VR define already.
Pan
-Original Message-
From: Robin Dapp
Sent: Monday, May 5, 2025 3:54 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com;
rdapp@gmail.com; Chen,
ta
Sent: Saturday, May 3, 2025 1:04 AM
To: Jeff Law ; Li, Pan2 ;
gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com; Chen, Ken
Subject: Re: [PATCH v1][GCC16-Stage-1] RISC-V: Remove unnecessary frm restore
volatile define_insn
On 4/30/25 20:44, Jeff L
can help.
Pan
-Original Message-
From: Vineet Gupta
Sent: Thursday, May 1, 2025 2:08 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com;
rdapp@gmail.com; Chen, Ken
Subject: Re: [PATCH v1][GCC16-Stage-1] RISC-V: Remove unnecessa
; pal...@dabbelt.com;
jeffreya...@gmail.com; rd...@ventanamicro.com; juzhe.zh...@rivai.ai; Li, Pan2
; vine...@rivosinc.com
Cc: Kito Cheng
Subject: [PATCH] RISC-V: Allow different dynamic floating point mode to be
merged [PR119832]
Although we already try to set the mode needed to FRM_DYN after a function
> Then we should perform the combination for GR2VR == 0 and not for GR2VR > 0.
Yes, that is correct, will resend the v3 within this change.
Pan
-Original Message-
From: Robin Dapp
Sent: Tuesday, April 29, 2025 9:47 PM
To: Li, Pan2 ; Robin Dapp ;
gcc-patches@gcc.gnu.org
Cc: juzhe
m: Robin Dapp
Sent: Tuesday, April 29, 2025 2:31 PM
To: Li, Pan2 ; Robin Dapp ;
gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; Chen,
Ken ; Liu, Hongtao ; Robin Dapp
Subject: Re: [PATCH v2 1/3] RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx
ncy consideration in late-combine's costing.
> When COST (vmv.vx) + COST (vadd.vv) > COST (vadd.vx) it should take place.
I see, will enrich the test cases for above two cases.
Pan
-Original Message-
From: Robin Dapp
Sent: Monday, April 28, 2025 3:39 PM
To: Li, Pan2 ; Robin
Kindly ping.
Pan
-Original Message-
From: Li, Pan2
Sent: Wednesday, April 16, 2025 10:57 PM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com;
rdapp@gmail.com; Chen, Ken ; Li, Pan2
Subject: [PATCH v1][GCC16-Stage-1] RISC-V: Remove
(weighted: 35.923637), replacement cost = 32
(weighted: 258.909092); rejecting replacement
61 │
Pan
-Original Message-
From: Robin Dapp
Sent: Thursday, April 24, 2025 8:13 PM
To: Li, Pan2 ; Robin Dapp ;
gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; je
<--- here.
Pan
-Original Message-
From: Li Xu
Sent: Thursday, January 2, 2025 4:04 PM
To: gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; richard.guent...@gmail.com; tamar.christ...@arm.com;
juzhe.zh...@rivai.ai; Li, Pan2 ; jeffreya...@gmail.com;
rdapp@gmail.com; xuli
Sub
PM
To: xuli1 mailto:xu...@eswincomputing.com>>;
gcc-patches mailto:gcc-patches@gcc.gnu.org>>
Cc: kito.cheng mailto:kito.ch...@gmail.com>>; palmer
mailto:pal...@dabbelt.com>>; Li, Pan2
mailto:pan2...@intel.com>>; xuli1
mailto:xu...@eswincomputing.com>&g
LGTM for the RISC-V part.
Pan
-Original Message-
From: Li Xu
Sent: Thursday, January 2, 2025 4:35 PM
To: gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; richard.guent...@gmail.com; tamar.christ...@arm.com;
juzhe.zh...@rivai.ai; Li, Pan2 ; jeffreya...@gmail.com;
rdapp@gmail.com
to focus on more important stuff. Now that we're looking at
> using rtx costing in more meaningful ways we probably need to rethink
> the hack we've got in place.
I see, will have a try in v3 for this part.
Pan
-Original Message-
From: Jeff Law
Sent: Friday, A
to the series.
Pan
-Original Message-
From: Robin Dapp
Sent: Wednesday, April 23, 2025 3:01 PM
To: Li, Pan2 ; Robin Dapp ;
gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; Chen,
Ken ; Liu, Hongtao ; Robin Dapp
Subject: Re: [PATCH v2 1/3] R
m: Robin Dapp
Sent: Tuesday, April 22, 2025 11:10 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com;
rdapp@gmail.com; Chen, Ken ; Liu, Hongtao
; Robin Dapp
Subject: Re: [PATCH v2 1/3] RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx
es a .vx form could be handled here.
Yes, all binary ops (except widen and narrow) should go here after this series.
With this we could support other binary ops more easily and efficient.
Pan
-Original Message-
From: Jeff Law
Sent: Friday, April 18, 2025 10:34 PM
To: Li, Pan2 ; gcc-patch
consider even more reaons besides testing friendly.
Anyway, we take care of this in other serices patches if no more concerns.
Pan
-Original Message-
From: Robin Dapp
Sent: Thursday, April 17, 2025 4:19 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@g
Hi Robin,
I am not sure if we have some options additional to below, like -march=generic,
to ensure that the late-combine will take action as expected in testcases.
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
Pan
-Original Message-----
From: Li, Pan2
Sent: Thursday
: Wednesday, April 9, 2025 6:47 PM
To: Li, Pan2 ; Robin Dapp ;
gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; Chen,
Ken ; Robin Dapp
Subject: Re: [PATCH v1] RISC-V: Refine the testcases for cond_widen_complicate-3
Hi Pan,
Richard committed combine
Kito Cheng
Sent: Tuesday, April 1, 2025 9:53 AM
To: Robin Dapp
Cc: Kito Cheng ; gcc-patches@gcc.gnu.org;
pal...@dabbelt.com; jeffreya...@gmail.com; rd...@ventanamicro.com;
juzhe.zh...@rivai.ai; Li, Pan2 ; vine...@rivosinc.com;
patr...@rivosinc.com; monk.chi...@sifive.com
Subject: Re: [PATCH v3
in and Jeff, I will re-send the patch of vadd.vv/vx after stage
1 open, and then all other
similar cases.
Pan
-Original Message-
From: Jeff Law
Sent: Sunday, March 30, 2025 8:31 AM
To: Robin Dapp ; Paul-Antoine Arras ;
gcc-patches@gcc.gnu.org; Li, Pan2
Subject: Re: [PATCH] RISC-V:
eems no other failures from rvv.exp now.
Pan
-Original Message-
From: Robin Dapp
Sent: Thursday, March 13, 2025 5:48 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; Chen,
Ken ; Robin Dapp
Subject: Re: [PATCH v1] RISC-V
o meet current behavior.
Pan
-Original Message-
From: Robin Dapp
Sent: Wednesday, March 12, 2025 7:11 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; Chen,
Ken ; Robin Dapp
Subject: Re: [PATCH v1] RISC-V: Refine the testcase
for a while if we need to tweak the vxrm behaviors, like set,
consume, global_reg, ... etc.
Pan
-Original Message-
From: Robin Dapp
Sent: Tuesday, March 4, 2025 8:51 PM
To: Vineet Gupta ; Andrew Waterman
Cc: Li, Pan2 ; jeffreya...@gmail.com;
gcc-patches@gcc.gnu.org; juzhe.zh
: Thursday, February 27, 2025 5:22 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; Robin
Dapp
Subject: Re: [PATCH v4] RISC-V: Fix bug for expand_const_vector interleave
[PR118931]
Hi Pan,
> + poly_int64 base1_poly = rtx_to_poly_in
ate in v4.
Pan
-Original Message-
From: Robin Dapp
Sent: Thursday, February 27, 2025 1:37 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; Robin
Dapp
Subject: Re: [PATCH v2] RISC-V: Fix bug for expand_const_vector interleave
erleave, I think it is safe because it
leverage the
merge to generate the result, instead of IOR. Only the IOR for final result have
this issue.
Pan
-Original Message-----
From: Robin Dapp
Sent: Thursday, February 27, 2025 12:23 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai
be an issue
> and all we needed to check is CONST_VECTOR_NUNITS () * step.
I see, that explains why we have poly shift right in previous, will update in
v3.
Pan
-----Original Message-
From: Robin Dapp
Sent: Wednesday, February 26, 2025 12:46 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc:
Pan
-Original Message-
From: Robin Dapp
Sent: Monday, February 24, 2025 7:44 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; Robin
Dapp
Subject: Re: [PATCH v1] RISC-V: Fix bug for expand_const_vector interleave
[PR118931]
I don't explore more cases here consider we are in stage 4. I think the
expand_const_vector need some
refactor up to a point.
Pan
-Original Message-
From: Robin Dapp
Sent: Monday, February 24, 2025 4:29 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch
support DI as element size.
I will try to reproduce this after this ICE fix.
Pan
-Original Message-
From: Richard Biener
Sent: Tuesday, February 18, 2025 5:36 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya...@gmail.com; rdapp...
diford
Sent: Monday, February 17, 2025 7:48 PM
To: Li, Pan2
Cc: Jeff Law ; Andrew Waterman ;
gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
rdapp@gmail.com
Subject: Re: [PATCH v1] RISC-V: Make VXRM as global register [PR118103]
Richard Sandiford writes:
> The probl
t where set the partial vector to true.
Is there any suggestion here?
Pan
-Original Message-
From: Li, Pan2
Sent: Monday, February 17, 2025 6:08 PM
To: Richard Biener
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya...@gmail.com; rdapp@gmail.com
Subje
> So OK with the two whitespace fixes.
Thanks Jeff, will commit with the whitespace fixes.
Pan
-Original Message-
From: Jeff Law
Sent: Tuesday, February 18, 2025 2:00 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com
Subj
need another place to fix this, let me have a try.
Pan
-Original Message-
From: Richard Biener
Sent: Monday, February 17, 2025 6:02 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya...@gmail.com; rdapp@gmail.com
Subject: Re:
ile before
any potential action to take.
Pan
-Original Message-
From: Richard Sandiford
Sent: Wednesday, February 12, 2025 5:03 PM
To: Jeff Law
Cc: Andrew Waterman ; Li, Pan2 ;
gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
rdapp@gmail.com
Subject: Re: [PATCH
Thanks Jeff and Andrew, committed as the CI passed.
Pan
-Original Message-
From: Andrew Waterman
Sent: Friday, February 7, 2025 9:54 PM
To: Jeff Law
Cc: Li, Pan2 ; gcc-patches@gcc.gnu.org;
juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v1] RISC-V
m: Robin Dapp
Sent: Friday, February 7, 2025 5:50 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; Robin
Dapp
Subject: Re: [PATCH v1] RISC-V: Make VXRM as global register [PR118103]
> Inspired by PR118103, the VXRM register should b
> I think you meant "the value extended into" rather than "the extended to".
> OK with that fix.
Thanks Jeff, will commit the series with that fix.
Pan
-Original Message-
From: Jeff Law
Sent: Tuesday, January 28, 2025 11:18 PM
To: Li, Pan2 ; gcc-patche
> Nit, can you move this check in the caller riscv_emit_mode_set () which
> already
> checks similarly for VXRM (unless there's a corner case.
Sure, I will send v2 after gcc-16 open.
Pan
-Original Message-
From: Vineet Gupta
Sent: Tuesday, January 28, 2025 11:01 AM
To:
Thanks Jeff, I will resolve the conflict and send v3 after test.
Pan
-Original Message-
From: Jeff Law
Sent: Monday, January 27, 2025 12:38 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v2 1/4] RISC-V
> It's a nice cleanup, but let's defer since it doesn't fix a bug.
Sure thing, will defer to gcc-16.
Pan
-Original Message-
From: Jeff Law
Sent: Sunday, January 26, 2025 9:34 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; r
Thanks Jeff and Sam, updated v2 for -fno-strict-aliasing.
Pan
-Original Message-
From: Jeff Law
Sent: Sunday, January 26, 2025 1:06 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com;
vine...@rivosinc.com; richard.sandif
To be efficient, I send the
sssub bugfix first, and then validate the ssadd and sstrunc
in the meantime.
Pan
-Original Message-
From: Jeff Law
Sent: Wednesday, January 22, 2025 6:46 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail
Sent: Tuesday, January 21, 2025 12:47 AM
To: Palmer Dabbelt
Cc: Li, Pan2 ; Vineet Gupta ;
gnu-toolch...@rivosinc.com; Robin Dapp ;
juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org
Subject: Re: gcc mode switching issue (was Re: RISC-V round_away () handling of
non canonical rounding modes)
On 1/1
It is 627.cam4_s or 527.cam4_r? I can help to reproduce this from k1 board.
Pan
-Original Message-
From: Vineet Gupta
Sent: Friday, January 17, 2025 10:23 AM
To: Li, Pan2
Cc: Jeff Law ; Palmer Dabbelt ;
gnu-toolchain ; Robin Dapp ;
juzhe.zh...@rivai.ai; GCC Patches
Subject: Re: gcc
Hi Vineet,
Is there any more information about the issue description here? Like steps for
reproducing, as well as expect behavior but actual result.. etc.
It is not easy to start the investigation with blow mail thread. Thanks a lot.
Pan
-Original Message-
From: Vineet Gupta
Sent: Fri
> OK for the trunk. Sorry for the delay.
Never mind, thanks Jeff and Happ New Year, 😉!
Pan
-Original Message-
From: Jeff Law
Sent: Tuesday, January 7, 2025 9:32 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: richard.guent...@gmail.com; tamar.christ...@arm.com; juzhe.zh...@rivai
Kindly ping for the series.
Pan
-Original Message-
From: Li, Pan2
Sent: Monday, December 23, 2024 3:09 PM
To: gcc-patches@gcc.gnu.org
Cc: richard.guent...@gmail.com; tamar.christ...@arm.com; juzhe.zh...@rivai.ai;
kito.ch...@gmail.com; jeffreya...@gmail.com; rdapp@gmail.com
Subject
Kindly ping for this series, and Merry Christmas!
Pan
-Original Message-
From: Li, Pan2
Sent: Thursday, December 12, 2024 4:42 PM
To: gcc-patches@gcc.gnu.org
Cc: richard.guent...@gmail.com; tamar.christ...@arm.com; juzhe.zh...@rivai.ai;
kito.ch...@gmail.com; jeffreya...@gmail.com
Kindly ping.
Pan
-Original Message-
From: Li, Pan2
Sent: Tuesday, December 10, 2024 2:28 PM
To: gcc-patches@gcc.gnu.org
Cc: richard.guent...@gmail.com; tamar.christ...@arm.com; juzhe.zh...@rivai.ai;
kito.ch...@gmail.com; jeffreya...@gmail.com; rdapp@gmail.com; Li, Pan2
Subject
Thanks Kito, all issues like below of rvv.exp are fixed.
Pan
-Original Message-
From: Kito Cheng
Sent: Monday, December 9, 2024 2:58 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; jeffreya...@gmail.com;
rdapp@gmail.com
Subject: Re: [PATCH v1] RISC-V: Fix
I see, thanks Robin, will have a try for this change.
Pan
-Original Message-
From: Robin Dapp
Sent: Wednesday, November 27, 2024 9:44 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; Robin
Dapp
Subject: Re: [PATCH v1 1/3
from test.
Pan
-Original Message-
From: Uros Bizjak
Sent: Wednesday, November 27, 2024 4:15 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; Liu, Hongtao
Subject: Re: [PATCH v4] I386: Add more testcases for unsigned SAT_ADD vector
pattern
On Wed, Nov 27, 2024 at 3:00 AM wrote:
>
s.
Pan
-Original Message-
From: Robin Dapp
Sent: Wednesday, November 27, 2024 8:48 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; Robin
Dapp
Subject: Re: [PATCH v1 1/3] RISC-V: Combine vec_duplicate + vadd.vv to va
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