> OK. Thanks Robin.
> Not that I see it as absolute necessity but I don't mind either way. > We don't just want to tweak the asm checks, though. The code is indeed > worse than before. I see, will leave other similar cases like cond_widen_complicate-[4|8] as is. And it seems no other failures from rvv.exp now. Pan -----Original Message----- From: Robin Dapp <rdapp....@gmail.com> Sent: Thursday, March 13, 2025 5:48 PM To: Li, Pan2 <pan2...@intel.com>; gcc-patches@gcc.gnu.org Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; Chen, Ken <ken.c...@intel.com>; Robin Dapp <rdapp....@gmail.com> Subject: Re: [PATCH v1] RISC-V: Refine the testcases for cond_widen_complicate-3 >> I'm not opposed to refactoring but what's the reason for it? We have a >> large >> number of similar tests that also include all possible types. And aren't >> all >> the tests you touch FAILing anyway right now? (Due to the combine change...) > > Yes, the cond_widen_complicate-3 need some tweak for the asm check failure. > Simply adjust the count cannot guarantee that each type has generated at least > one vw/vfw. For example, i8 doesn't generate vw but i16 generate 2 vw insn, > and the final asm check times is the same. > > Thus, I refactor them into different types to meet current behavior. OK. Not that I see it as absolute necessity but I don't mind either way. We don't just want to tweak the asm checks, though. The code is indeed worse than before. -- Regards Robin
