> Is that correct?  Don't you need to be testing that the platform has 
> vector in addition to being rv64?

It is riscv.exp test, so I think vector extension is not required here.

Pan

-----Original Message-----
From: Jeff Law <jeffreya...@gmail.com> 
Sent: Tuesday, July 8, 2025 11:45 AM
To: Li, Pan2 <pan2...@intel.com>; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp....@gmail.com; Chen, Ken 
<ken.c...@intel.com>; Liu, Hongtao <hongtao....@intel.com>
Subject: Re: [PATCH v1] RISC-V: Disable uint128_t testcase of SAT_MUL when rv32



On 7/7/25 9:24 PM, pan2...@intel.com wrote:

>   
> /******************************************************************************/
>   /* Saturation Add (unsigned and signed)                                     
>   */
> diff --git 
> a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c 
> b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c
> index 395a4cb060c..79f62973af3 100644
> --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c
> +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c
> @@ -1,4 +1,4 @@
> -/* { dg-do run { target { riscv_v } } } */
> +/* { dg-do run { target { rv64 } } } */
Is that correct?  Don't you need to be testing that the platform has 
vector in addition to being rv64?

jeff

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