> Couldn't we keep the RTL in order for other optimizations? I'm not really > expecting any but at least we'd still have the opportunity. Or does that > interfere with the tests?
I see, let me have a try in v2. Pan -----Original Message----- From: Robin Dapp <rdapp....@gmail.com> Sent: Tuesday, May 27, 2025 2:27 PM To: Li, Pan2 <pan2...@intel.com>; gcc-patches@gcc.gnu.org Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; rdapp....@gmail.com; Chen, Ken <ken.c...@intel.com>; Liu, Hongtao <hongtao....@intel.com>; and...@sifive.com; Robin Dapp <rdapp....@gmail.com> Subject: Re: [PATCH v1 1/3] RISC-V: Leverage vaadd.vv for signed standard name avg_floor > -(define_expand "avg<v_double_trunc>3_floor" > - [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand") > - (truncate:<V_DOUBLE_TRUNC> > - (ashiftrt:VWEXTI > - (plus:VWEXTI > - (sign_extend:VWEXTI > - (match_operand:<V_DOUBLE_TRUNC> 1 "register_operand")) > - (sign_extend:VWEXTI > - (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))))))] > +(define_expand "avg<mode>3_floor" > + [(match_operand:V_VLSI 0 "register_operand") > + (match_operand:V_VLSI 1 "register_operand") > + (match_operand:V_VLSI 2 "register_operand")] > "TARGET_VECTOR" Couldn't we keep the RTL in order for other optimizations? I'm not really expecting any but at least we'd still have the opportunity. Or does that interfere with the tests? Apart from that it LGTM, thanks for digging deeper here. -- Regards Robin
