The CI reported 2 failures but seems unrelated and passed locally, thus will
commit this before the end of next Monday(6/30) if no more concerns.
> FAIL: gcc.dg/vect/pr115669.c -flto -ffat-lto-objects (test for excess errors)
Executing on host:
/home/lipan/gnu-toolchain/build/build-riscv64-unknown-elf-gcc-riscv64/build-gcc-stage2/gcc/xgcc
-B/home/lipan/gnu-toolchain/build/build-riscv64-unknown-elf-gcc-riscv64/build-gcc-stage2/gcc/
/home/lipan/gnu-toolchain/gcc/gcc/testsuite/gcc.dg/vect/pr115669.c
-fdiagnostics-plain-output -flto -ffat-lto-objects -mno-vector-strict-align
-ftree-vectorize -fno-tree-loop-distribute-patterns -fno-vect-cost-model
-fno-common -O2 -fdump-tree-vect-details -fwrapv -lm -o ./pr115669.exe
(timeout = 600)
spawn -ignore SIGHUP
/home/lipan/gnu-toolchain/build/build-riscv64-unknown-elf-gcc-riscv64/build-gcc-stage2/gcc/xgcc
-B/home/lipan/gnu-toolchain/build/build-riscv64-unknown-elf-gcc-riscv64/build-gcc-stage2/gcc/
/home/lipan/gnu-toolchain/gcc/gcc/testsuite/gcc.dg/vect/pr115669.c
-fdiagnostics-plain-output -flto -ffat-lto-objects -mno-vector-strict-align
-ftree-vectorize -fno-tree-loop-distribute-patterns -fno-vect-cost-model
-fno-common -O2 -fdump-tree-vect-details -fwrapv -lm -o ./pr115669.exe
PASS: gcc.dg/vect/pr115669.c -flto -ffat-lto-objects (test for excess errors)
PASS: gcc.dg/vect/pr115669.c -flto -ffat-lto-objects execution test
> FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c -O0 (test for
> excess errors)
Executing on host:
/home/lipan/gnu-toolchain/build/build-riscv64-unknown-elf-gcc-riscv64/build-gcc-stage2/gcc/xgcc
-B/home/lipan/gnu-toolchain/build/build-riscv64-unknown-elf-gcc-riscv64/build-gcc-stage2/gcc/
/home/lipan/gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c
-fdiagnostics-plain-output -O0 -mrvv-vector-bits=scalable -march=rv32gcv
-mabi=ilp32 -fno-tree-vectorize -ffat-lto-objects -fno-ident -S -o
vlmax_complex_loop-1.s (timeout = 600)
spawn -ignore SIGHUP
/home/lipan/gnu-toolchain/build/build-riscv64-unknown-elf-gcc-riscv64/build-gcc-stage2/gcc/xgcc
-B/home/lipan/gnu-toolchain/build/build-riscv64-unknown-elf-gcc-riscv64/build-gcc-stage2/gcc/
/home/lipan/gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c
-fdiagnostics-plain-output -O0 -mrvv-vector-bits=scalable -march=rv32gcv
-mabi=ilp32 -fno-tree-vectorize -ffat-lto-objects -fno-ident -S -o
vlmax_complex_loop-1.s
PASS: gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c -O0 (test for
excess errors)
lipan@ibt-server-09:~/gnu-toolchain$ grep --color vlmax_complex_loop-1
build/build-riscv64-unknown-elf-gcc-riscv64/build-gcc-stage2/gcc/testsuite/gcc/gcc.log
| grep "O0" --color
Executing on host:
/home/lipan/gnu-toolchain/build/build-riscv64-unknown-elf-gcc-riscv64/build-gcc-stage2/gcc/xgcc
-B/home/lipan/gnu-toolchain/build/build-riscv64-unknown-elf-gcc-riscv64/build-gcc-stage2/gcc/
/home/lipan/gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c
-fdiagnostics-plain-output -O0 -mrvv-vector-bits=scalable -march=rv32gcv
-mabi=ilp32 -fno-tree-vectorize -ffat-lto-objects -fno-ident -S -o
vlmax_complex_loop-1.s (timeout = 600)
spawn -ignore SIGHUP
/home/lipan/gnu-toolchain/build/build-riscv64-unknown-elf-gcc-riscv64/build-gcc-stage2/gcc/xgcc
-B/home/lipan/gnu-toolchain/build/build-riscv64-unknown-elf-gcc-riscv64/build-gcc-stage2/gcc/
/home/lipan/gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c
-fdiagnostics-plain-output -O0 -mrvv-vector-bits=scalable -march=rv32gcv
-mabi=ilp32 -fno-tree-vectorize -ffat-lto-objects -fno-ident -S -o
vlmax_complex_loop-1.s
PASS: gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c -O0 (test for
excess errors)
Pan
-----Original Message-----
From: Li, Pan2 <pan2...@intel.com>
Sent: Friday, June 27, 2025 10:00 PM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com;
rdapp....@gmail.com; Chen, Ken <ken.c...@intel.com>; Liu, Hongtao
<hongtao....@intel.com>; Li, Pan2 <pan2...@intel.com>
Subject: [PATCH v3 0/4] RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx
on GR2VR cost
From: Pan Li <pan2...@intel.com>
This patch would like to introduce the combine of vec_dup + vssubu.vv
into vssubu.vx on the cost value of GR2VR. The late-combine will take
place if the cost of GR2VR is zero, or reject the combine if non-zero
like 1, 2, 15 in test. There will be two cases for the combine:
Case 0:
| ...
| vmv.v.x
| L1:
| vssubu.vv
| J L1
| ...
Case 1:
| ...
| L1:
| vmv.v.x
| vssubu.vv
| J L1
| ...
Both will be combined to below if the cost of GR2VR is zero.
| ...
| L1:
| vssubu.vx
| J L1
| ...
The below test suites are passed for this patch series.
* The rv64gcv fully regression test.
Pan Li (4):
RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on GR2VR cost
RISC-V: Reconcile the existing test due to cost model change
RISC-V: Add test for vec_duplicate + vssubu.vv combine case 0 with GR2VR cost
0, 2 and 15
RISC-V: Add test for vec_duplicate + vssubu.vv combine case 1 with GR2VR cost
0, 1 and 2
gcc/config/riscv/riscv-v.cc | 1 +
gcc/config/riscv/riscv.cc | 1 +
gcc/config/riscv/vector-iterators.md | 2 +-
.../autovec/sat/vec_sat_u_sub_trunc-1-u16.c | 2 +-
.../autovec/sat/vec_sat_u_sub_trunc-1-u32.c | 2 +-
.../autovec/sat/vec_sat_u_sub_trunc-1-u8.c | 2 +-
.../riscv/rvv/autovec/vx_vf/vx-1-u16.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-1-u32.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-1-u64.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-1-u8.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-2-u16.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-2-u32.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-2-u64.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-2-u8.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-3-u16.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-3-u32.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-3-u64.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-3-u8.c | 1 +
.../riscv/rvv/autovec/vx_vf/vx-4-u16.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-4-u32.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-4-u64.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-4-u8.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-5-u16.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-5-u32.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-5-u64.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-5-u8.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-6-u16.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-6-u32.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-6-u64.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-6-u8.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx_binary.h | 18 +-
.../riscv/rvv/autovec/vx_vf/vx_binary_data.h | 196 ++++++++++++++++++
.../rvv/autovec/vx_vf/vx_vssub-run-1-u16.c | 17 ++
.../rvv/autovec/vx_vf/vx_vssub-run-1-u32.c | 17 ++
.../rvv/autovec/vx_vf/vx_vssub-run-1-u64.c | 17 ++
.../rvv/autovec/vx_vf/vx_vssub-run-1-u8.c | 17 ++
36 files changed, 323 insertions(+), 5 deletions(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u8.c
--
2.43.0
