> Form2:
> void __attribute__((noinline)) \
> vec_sat_u_sub_imm##IMM##_##T##_fmt_2 (T *out, T *in, unsigned limit) \
> { \
> unsigned i; \
> for (i = 0; i < limit; i++) \
> out[i] = in[i] >= (T)IMM ? in[i] - (T)IMM : 0; \
> }
> Form3:
> void __attribute__((noinline)) \
> vec_sat_u_sub_imm##IMM##_##T##_fmt_3 (T *out, T *in, unsigned limit) \
> { \
> unsigned i; \
> for (i = 0; i < limit; i++) \
> out[i] = (T)IMM > in[i] ? (T)IMM - in[i] : 0; \
> }
> Form4:
> void __attribute__((noinline)) \
> vec_sat_u_sub_imm##IMM##_##T##_fmt_4 (T *out, T *in, unsigned limit) \
> { \
> unsigned i; \
> for (i = 0; i < limit; i++) \
> out[i] = in[i] > (T)IMM ? in[i] - (T)IMM : 0; \
> }
Ideally should be 4 forms here? I mean commutative with 4 forms.
In[i] >= IMM
In[i] > IMM
IMM > in[i]
IMM >= in[i]
Otherwise, LGTM. Please also double check if we need to rebase to upstream.
Pan
From: 钟居哲 <juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>>
Sent: Thursday, January 2, 2025 4:04 PM
To: xuli1 <xu...@eswincomputing.com<mailto:xu...@eswincomputing.com>>;
gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>
Cc: kito.cheng <kito.ch...@gmail.com<mailto:kito.ch...@gmail.com>>; palmer
<pal...@dabbelt.com<mailto:pal...@dabbelt.com>>; Li, Pan2
<pan2...@intel.com<mailto:pan2...@intel.com>>; xuli1
<xu...@eswincomputing.com<mailto:xu...@eswincomputing.com>>
Subject: Re: [PATCH] RISC-V: Add testcases for unsigned imm vec SAT_SUB form2~4
LGTM.
________________________________
juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>
From: Li Xu<mailto:xu...@eswincomputing.com>
Date: 2025-01-02 16:02
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: kito.cheng<mailto:kito.ch...@gmail.com>; palmer<mailto:pal...@dabbelt.com>;
juzhe.zhong<mailto:juzhe.zh...@rivai.ai>; pan2.li<mailto:pan2...@intel.com>;
xuli<mailto:xu...@eswincomputing.com>
Subject: [PATCH] RISC-V: Add testcases for unsigned imm vec SAT_SUB form2~4
From: xuli <xu...@eswincomputing.com<mailto:xu...@eswincomputing.com>>
Form2:
void __attribute__((noinline)) \
vec_sat_u_sub_imm##IMM##_##T##_fmt_2 (T *out, T *in, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
out[i] = in[i] >= (T)IMM ? in[i] - (T)IMM : 0; \
}
Form3:
void __attribute__((noinline)) \
vec_sat_u_sub_imm##IMM##_##T##_fmt_3 (T *out, T *in, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
out[i] = (T)IMM > in[i] ? (T)IMM - in[i] : 0; \
}
Form4:
void __attribute__((noinline)) \
vec_sat_u_sub_imm##IMM##_##T##_fmt_4 (T *out, T *in, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
out[i] = in[i] > (T)IMM ? in[i] - (T)IMM : 0; \
}
Passed the rv64gcv full regression test.
Signed-off-by: Li Xu <xu...@eswincomputing.com<mailto:xu...@eswincomputing.com>>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h: add unsigned imm vec
sat_sub form2~4.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h: add data for vec sat_sub.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-2-u16.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-2-u32.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-2-u64.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-2-u8.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-3-u16.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-3-u32.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-3-u64.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-3-u8.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-4-u16.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-4-u32.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-4-u64.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-4-u8.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u16.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u32.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u64.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u8.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-3-u16.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-3-u32.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-3-u64.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-3-u8.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u16.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u32.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u64.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u8.c: New test.
…
