[gcc r16-2351] RISC-V: Support RVVDImode for avg3_ceil auto vect

https://gcc.gnu.org/g:c1a34e80991c85d02af6be3edb4f8c4e1116e363 commit r16-2351-gc1a34e80991c85d02af6be3edb4f8c4e1116e363 Author: Pan Li Date: Wed Jul 16 21:40:14 2025 +0800 RISC-V: Support RVVDImode for avg3_ceil auto vect Like the avg3_floor pattern, the avg3_ceil has the sim

[gcc r16-2277] RISC-V: Support RVVDImode for avg3_floor auto vect

https://gcc.gnu.org/g:430be3b933bfac1f1caace4f0ef393a4d434ea0f commit r16-2277-g430be3b933bfac1f1caace4f0ef393a4d434ea0f Author: Pan Li Date: Tue Jul 15 09:45:05 2025 +0800 RISC-V: Support RVVDImode for avg3_floor auto vect The avg3_floor pattern leverage the add and shift rtl

[gcc r16-2235] RISC-V: Add testcase for rv32 SAT_MUL from uint64

https://gcc.gnu.org/g:f7f0539ae9c7fbd33c29c6e73b6970d85b7394b7 commit r16-2235-gf7f0539ae9c7fbd33c29c6e73b6970d85b7394b7 Author: Pan Li Date: Fri Jul 11 08:58:31 2025 +0800 RISC-V: Add testcase for rv32 SAT_MUL from uint64 Add the run and asm testcase for rv32 SAT_MUL, widen mul f

[gcc r16-2234] Match: Refine the widen mul check for SAT_MUL pattern

https://gcc.gnu.org/g:f01216a0b71a3e88c796ed302d6a6bc2fdb35d44 commit r16-2234-gf01216a0b71a3e88c796ed302d6a6bc2fdb35d44 Author: Pan Li Date: Fri Jul 11 08:38:09 2025 +0800 Match: Refine the widen mul check for SAT_MUL pattern The widen mul will have source type from N-bits to

[gcc r16-2157] RISCV: Remove the v extension requirement for sat scalar run test

https://gcc.gnu.org/g:e3d1b3cce876630380e6c2e3782c2fb0f4e7fb42 commit r16-2157-ge3d1b3cce876630380e6c2e3782c2fb0f4e7fb42 Author: Pan Li Date: Wed Jul 9 10:40:52 2025 +0800 RISCV: Remove the v extension requirement for sat scalar run test The sat scalar run test should not require

[gcc r16-2140] RISC-V: Combine vec_duplicate + vssub.vv to vssub.vx on GR2VR cost

https://gcc.gnu.org/g:8877ab269e1408522839377c3ef725efe1589277 commit r16-2140-g8877ab269e1408522839377c3ef725efe1589277 Author: Pan Li Date: Mon Jul 7 11:07:11 2025 +0800 RISC-V: Combine vec_duplicate + vssub.vv to vssub.vx on GR2VR cost This patch would like to combine the vec_d

[gcc r16-2142] RISC-V: Add test for vec_duplicate + vssub.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:503e1680ccaffbc90b394191a2bc1ac88b1d113f commit r16-2142-g503e1680ccaffbc90b394191a2bc1ac88b1d113f Author: Pan Li Date: Mon Jul 7 11:17:00 2025 +0800 RISC-V: Add test for vec_duplicate + vssub.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check t

[gcc r16-2141] RISC-V: Add test for vec_duplicate + vssub.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:e8bb09a0050046082204eb28b26ecf1594edc2d0 commit r16-2141-ge8bb09a0050046082204eb28b26ecf1594edc2d0 Author: Pan Li Date: Mon Jul 7 11:13:15 2025 +0800 RISC-V: Add test for vec_duplicate + vssub.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check

[gcc r16-2117] RISC-V: Disable uint128_t testcase of SAT_MUL when rv32

https://gcc.gnu.org/g:a09b415b87cd98e3a4f3e197ad4e9e67a335c1d4 commit r16-2117-ga09b415b87cd98e3a4f3e197ad4e9e67a335c1d4 Author: Pan Li Date: Tue Jul 8 10:46:29 2025 +0800 RISC-V: Disable uint128_t testcase of SAT_MUL when rv32 The rv32 doesn't support __uint128, and then we will

[gcc r16-2061] RISC-V: Add test cases for unsigned scalar SAT_MUL from uint128_t

https://gcc.gnu.org/g:65c40c0211f01579d1e7f259271cb79a8a19d533 commit r16-2061-g65c40c0211f01579d1e7f259271cb79a8a19d533 Author: Pan Li Date: Wed Jul 2 10:52:25 2025 +0800 RISC-V: Add test cases for unsigned scalar SAT_MUL from uint128_t Add run and tree-optimized check for unsign

[gcc r16-2060] RISC-V: Implement unsigned scalar SAT_MUL from uint128_t

https://gcc.gnu.org/g:62b99e84b886fbdd70118cc260ae0f2516c2f3f5 commit r16-2060-g62b99e84b886fbdd70118cc260ae0f2516c2f3f5 Author: Pan Li Date: Wed Jul 2 10:35:10 2025 +0800 RISC-V: Implement unsigned scalar SAT_MUL from uint128_t This patch would like to implement the SAT_MUL scala

[gcc r16-2059] Widening-Mul: Support unsigned scalar SAT_MUL form 1

https://gcc.gnu.org/g:dc30f404170f538af6bf2457ccff252b08302dec commit r16-2059-gdc30f404170f538af6bf2457ccff252b08302dec Author: Pan Li Date: Wed Jul 2 09:59:26 2025 +0800 Widening-Mul: Support unsigned scalar SAT_MUL form 1 This patch would like to try to match the SAT_MUL during

[gcc r16-2058] Internal-fn: Introduce new IFN_SAT_MUL for unsigned int

https://gcc.gnu.org/g:35f5a18872127e18aadcbbc08df7885974280c79 commit r16-2058-g35f5a18872127e18aadcbbc08df7885974280c79 Author: Pan Li Date: Wed Jul 2 09:46:08 2025 +0800 Internal-fn: Introduce new IFN_SAT_MUL for unsigned int This patch would like to add the middle-end presentat

[gcc r16-2023] RISC-V: Add test for vec_duplicate + vsadd.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:2f19d9408477829ab7de465310fa0068be0f43ff commit r16-2023-g2f19d9408477829ab7de465310fa0068be0f43ff Author: Pan Li Date: Thu Jul 3 17:17:28 2025 +0800 RISC-V: Add test for vec_duplicate + vsadd.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check t

[gcc r16-2022] RISC-V: Add test for vec_duplicate + vsadd.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:ea86a5a111f3bc883035b0783fe419e5bd2722a0 commit r16-2022-gea86a5a111f3bc883035b0783fe419e5bd2722a0 Author: Pan Li Date: Thu Jul 3 17:16:21 2025 +0800 RISC-V: Add test for vec_duplicate + vsadd.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check

[gcc r16-2021] RISC-V: Combine vec_duplicate + vsadd.vv to vsadd.vx on GR2VR cost

https://gcc.gnu.org/g:0601f461649323c7d6c7bb33c6839f60949116c2 commit r16-2021-g0601f461649323c7d6c7bb33c6839f60949116c2 Author: Pan Li Date: Thu Jul 3 17:07:44 2025 +0800 RISC-V: Combine vec_duplicate + vsadd.vv to vsadd.vx on GR2VR cost This patch would like to combine the vec_d

[gcc r16-1823] RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on GR2VR cost

https://gcc.gnu.org/g:b7fe719e449db56d665da17ca4f4ba7977da34ed commit r16-1823-gb7fe719e449db56d665da17ca4f4ba7977da34ed Author: Pan Li Date: Fri Jun 27 09:02:03 2025 +0800 RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on GR2VR cost This patch would like to combine the ve

[gcc r16-1826] RISC-V: Add test for vec_duplicate + vssubu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:ff87aefc061d7de3b233bfe034fb29cc253f77a9 commit r16-1826-gff87aefc061d7de3b233bfe034fb29cc253f77a9 Author: Pan Li Date: Fri Jun 27 09:09:08 2025 +0800 RISC-V: Add test for vec_duplicate + vssubu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check

[gcc r16-1825] RISC-V: Add test for vec_duplicate + vssubu.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:342694acd59c87f35d97805609ba54f547b52881 commit r16-1825-g342694acd59c87f35d97805609ba54f547b52881 Author: Pan Li Date: Fri Jun 27 09:06:38 2025 +0800 RISC-V: Add test for vec_duplicate + vssubu.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump chec

[gcc r16-1824] RISC-V: Reconcile the existing test due to cost model change

https://gcc.gnu.org/g:db267b0d1dcabd09d9064093383e38f2596345a4 commit r16-1824-gdb267b0d1dcabd09d9064093383e38f2596345a4 Author: Pan Li Date: Fri Jun 27 11:35:18 2025 +0800 RISC-V: Reconcile the existing test due to cost model change The cost model change will make the default cos

[gcc r16-1629] RISC-V: Add test for vec_duplicate + vsaddu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:11811e698b460b5fe45777f4c333aa74655cff39 commit r16-1629-g11811e698b460b5fe45777f4c333aa74655cff39 Author: Pan Li Date: Sat Jun 21 10:07:38 2025 +0800 RISC-V: Add test for vec_duplicate + vsaddu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check

[gcc r16-1628] RISC-V: Add test for vec_duplicate + vsaddu.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:9a8f82d6a63e36ffba883b365101b58955ca7c64 commit r16-1628-g9a8f82d6a63e36ffba883b365101b58955ca7c64 Author: Pan Li Date: Sat Jun 21 09:10:07 2025 +0800 RISC-V: Add test for vec_duplicate + vsaddu.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump chec

[gcc r16-1627] RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on GR2VR cost

https://gcc.gnu.org/g:a2d018b642019165511e89d47bfb46af55f81f98 commit r16-1627-ga2d018b642019165511e89d47bfb46af55f81f98 Author: Pan Li Date: Sat Jun 21 09:00:16 2025 +0800 RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on GR2VR cost This patch would like to combine the ve

[gcc r16-1597] RISC-V: Fix ICE for expand_select_vldi [PR120652]

https://gcc.gnu.org/g:52582b40a9bf839ae3771de1557ce6691eb8eedd commit r16-1597-g52582b40a9bf839ae3771de1557ce6691eb8eedd Author: Pan Li Date: Thu Jun 19 18:58:17 2025 +0800 RISC-V: Fix ICE for expand_select_vldi [PR120652] The will be one ICE when expand pass, the bt similar as be

[gcc r16-1583] RISC-V: Add test for vec_duplicate + vminu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:89ec7ba1b1815aa9ba68d17f01e1b5a4dc20bde5 commit r16-1583-g89ec7ba1b1815aa9ba68d17f01e1b5a4dc20bde5 Author: Pan Li Date: Thu Jun 19 10:49:07 2025 +0800 RISC-V: Add test for vec_duplicate + vminu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check

[gcc r16-1582] RISC-V: Add test for vec_duplicate + vminu.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:289220af97f712d253d0b9d649e57e7da3dd37ea commit r16-1582-g289220af97f712d253d0b9d649e57e7da3dd37ea Author: Pan Li Date: Thu Jun 19 10:47:33 2025 +0800 RISC-V: Add test for vec_duplicate + vminu.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check

[gcc r16-1581] RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2VR cost

https://gcc.gnu.org/g:7ea9105f2609efe089461d7e92533324eb5b1103 commit r16-1581-g7ea9105f2609efe089461d7e92533324eb5b1103 Author: Pan Li Date: Thu Jun 19 10:44:14 2025 +0800 RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2VR cost This patch would like to combine the vec_

[gcc r16-1553] RISC-V: Add test for vec_duplicate + vmin.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:29da9a40d1a1e21808dc596e3535058231004492 commit r16-1553-g29da9a40d1a1e21808dc596e3535058231004492 Author: Pan Li Date: Tue Jun 17 10:05:33 2025 +0800 RISC-V: Add test for vec_duplicate + vmin.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check

[gcc r16-1554] RISC-V: Add test for vec_duplicate + vmin.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:a0ffc9b1bfd45da5ce676a0cef419381c021f54b commit r16-1554-ga0ffc9b1bfd45da5ce676a0cef419381c021f54b Author: Pan Li Date: Tue Jun 17 10:08:44 2025 +0800 RISC-V: Add test for vec_duplicate + vmin.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check t

[gcc r16-1552] RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR cost

https://gcc.gnu.org/g:13c0ad1611eae7f0cd2a412b2f549a368d7d8be2 commit r16-1552-g13c0ad1611eae7f0cd2a412b2f549a368d7d8be2 Author: Pan Li Date: Tue Jun 17 10:00:54 2025 +0800 RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR cost This patch would like to combine the vec_du

[gcc r16-1526] RISC-V: Refine VX combine test case 0 to avoid code duplication

https://gcc.gnu.org/g:ad909d5c0ce7fcd0bcbacd0ee20c15bf479fd990 commit r16-1526-gad909d5c0ce7fcd0bcbacd0ee20c15bf479fd990 Author: Pan Li Date: Sun Jun 15 16:28:38 2025 +0800 RISC-V: Refine VX combine test case 0 to avoid code duplication The case 0 for vx combine def functions are

[gcc r16-1514] RISC-V: Add test for vec_duplicate + vmaxu.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:50034d8f109a4d40c5bd63b63d8e8c8d3ea69e56 commit r16-1514-g50034d8f109a4d40c5bd63b63d8e8c8d3ea69e56 Author: Pan Li Date: Sat Jun 14 22:32:23 2025 +0800 RISC-V: Add test for vec_duplicate + vmaxu.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check

[gcc r16-1515] RISC-V: Add test for vec_duplicate + vmaxu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:afe3401f2e73e21d0e54ea8529642e37ae4a23d5 commit r16-1515-gafe3401f2e73e21d0e54ea8529642e37ae4a23d5 Author: Pan Li Date: Sat Jun 14 22:34:36 2025 +0800 RISC-V: Add test for vec_duplicate + vmaxu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check

[gcc r16-1513] RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2VR cost

https://gcc.gnu.org/g:7f153b96aa84773e7b18cf66db73afab55850c2a commit r16-1513-g7f153b96aa84773e7b18cf66db73afab55850c2a Author: Pan Li Date: Sat Jun 14 22:29:40 2025 +0800 RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2VR cost This patch would like to combine the vec_

[gcc r16-1477] RISC-V: Combine vec_duplicate + vmax.vv to vmax.vx on GR2VR cost

https://gcc.gnu.org/g:55e9547b87c60d5807e24a80e79a0d219ac12d9c commit r16-1477-g55e9547b87c60d5807e24a80e79a0d219ac12d9c Author: Pan Li Date: Wed Jun 11 21:49:21 2025 +0800 RISC-V: Combine vec_duplicate + vmax.vv to vmax.vx on GR2VR cost This patch would like to combine the vec_du

[gcc r16-1481] RISC-V: Add test for vec_dup + vmax.vv combine case 1 with max func 1 and GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:f3001dd5fe57738be222c3af690f7fdd86f531a1 commit r16-1481-gf3001dd5fe57738be222c3af690f7fdd86f531a1 Author: Pan Li Date: Thu Jun 12 10:42:39 2025 +0800 RISC-V: Add test for vec_dup + vmax.vv combine case 1 with max func 1 and GR2VR cost 0, 1 and 2 Add asm dum

[gcc r16-1479] RISC-V: Add test for vec_dup + vmax.vv combine case 0 with max func 1 and GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:2ae6cd8cd19962441403e5975d15f0fd14d662e2 commit r16-1479-g2ae6cd8cd19962441403e5975d15f0fd14d662e2 Author: Pan Li Date: Thu Jun 12 09:12:09 2025 +0800 RISC-V: Add test for vec_dup + vmax.vv combine case 0 with max func 1 and GR2VR cost 0, 2 and 15 Add asm du

[gcc r16-1480] RISC-V: Add test for vec_dup + vmax.vv combine case 1 with max func 0 and GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:86d1b55da654c05343279a54ffe2cbcc0cbebb21 commit r16-1480-g86d1b55da654c05343279a54ffe2cbcc0cbebb21 Author: Pan Li Date: Thu Jun 12 10:23:49 2025 +0800 RISC-V: Add test for vec_dup + vmax.vv combine case 1 with max func 0 and GR2VR cost 0, 1 and 2 Add asm dum

[gcc r16-1478] RISC-V: Add test for vec_dup + vmax.vv combine case 0 with max func 0 and GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:2ebb805fe2f29262a455aaf412b3f77060e05fe2 commit r16-1478-g2ebb805fe2f29262a455aaf412b3f77060e05fe2 Author: Pan Li Date: Wed Jun 11 21:51:08 2025 +0800 RISC-V: Add test for vec_dup + vmax.vv combine case 0 with max func 0 and GR2VR cost 0, 2 and 15 Add asm du

[gcc r16-1359] RISC-V: Add test for vec_duplicate + vremu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:bcabb6b0c707271b86a59be755f295ab7c125df1 commit r16-1359-gbcabb6b0c707271b86a59be755f295ab7c125df1 Author: Pan Li Date: Mon Jun 9 16:35:47 2025 +0800 RISC-V: Add test for vec_duplicate + vremu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check t

[gcc r16-1358] RISC-V: Add test for vec_duplicate + vremu.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:0bdea31036e8268edd1b4ea3ed07478c07c96ad1 commit r16-1358-g0bdea31036e8268edd1b4ea3ed07478c07c96ad1 Author: Pan Li Date: Mon Jun 9 16:33:52 2025 +0800 RISC-V: Add test for vec_duplicate + vremu.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check

[gcc r16-1357] RISC-V: Reconcile the existing test for vremu.vx combine

https://gcc.gnu.org/g:b59354cf309052de6a1c297f06411691c03bfd24 commit r16-1357-gb59354cf309052de6a1c297f06411691c03bfd24 Author: Pan Li Date: Mon Jun 9 16:28:50 2025 +0800 RISC-V: Reconcile the existing test for vremu.vx combine Some existing vrem related test need some adjust for

[gcc r16-1356] RISC-V: Combine vec_duplicate + vremu.vv to vremu.vx on GR2VR cost

https://gcc.gnu.org/g:85de2b8b58e1644f6d5f0f182426122416b19e6f commit r16-1356-g85de2b8b58e1644f6d5f0f182426122416b19e6f Author: Pan Li Date: Mon Jun 9 16:24:34 2025 +0800 RISC-V: Combine vec_duplicate + vremu.vv to vremu.vx on GR2VR cost This patch would like to combine the vec_d

[gcc r16-1296] RISC-V: Add test for vec_duplicate + vrem.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:daee1935f4e366c09fc085905cb49bbf264c5663 commit r16-1296-gdaee1935f4e366c09fc085905cb49bbf264c5663 Author: Pan Li Date: Sun Jun 8 16:53:05 2025 +0800 RISC-V: Add test for vec_duplicate + vrem.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check t

[gcc r16-1295] RISC-V: Reconcile the existing test for vrem.vx combine

https://gcc.gnu.org/g:4df4acf002cc3672478edb43f374cef3ffbd1f54 commit r16-1295-g4df4acf002cc3672478edb43f374cef3ffbd1f54 Author: Pan Li Date: Sun Jun 8 16:50:52 2025 +0800 RISC-V: Reconcile the existing test for vrem.vx combine Some existing vrem related test need some adjust for

[gcc r16-1297] RISC-V: Add test for vec_duplicate + vrem.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:8d745f6d70172132a594dcc650a6d489e7246eda commit r16-1297-g8d745f6d70172132a594dcc650a6d489e7246eda Author: Pan Li Date: Sun Jun 8 16:55:34 2025 +0800 RISC-V: Add test for vec_duplicate + vrem.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check te

[gcc r16-1294] RISC-V: Combine vec_duplicate + vrem.vv to vrem.vx on GR2VR cost

https://gcc.gnu.org/g:b96e319dbd19328a2243b2950155be57532c213b commit r16-1294-gb96e319dbd19328a2243b2950155be57532c213b Author: Pan Li Date: Sun Jun 8 16:48:33 2025 +0800 RISC-V: Combine vec_duplicate + vrem.vv to vrem.vx on GR2VR cost This patch would like to combine the vec_dup

[gcc r16-1257] RISC-V: Add test for vec_duplicate + vdivu.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:c01830fa809fa18d1d54b29a89cb65f3bb8f5676 commit r16-1257-gc01830fa809fa18d1d54b29a89cb65f3bb8f5676 Author: Pan Li Date: Fri Jun 6 09:51:10 2025 +0800 RISC-V: Add test for vec_duplicate + vdivu.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check t

[gcc r16-1256] RISC-V: Add test for vec_duplicate + vdivu.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:2ca7622fd7b32fd538edea8fd8bd8b97ba07ef16 commit r16-1256-g2ca7622fd7b32fd538edea8fd8bd8b97ba07ef16 Author: Pan Li Date: Fri Jun 6 09:49:56 2025 +0800 RISC-V: Add test for vec_duplicate + vdivu.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check

[gcc r16-1255] RISC-V: Combine vec_duplicate + vidvu.vv to vdivu.vx on GR2VR cost

https://gcc.gnu.org/g:be205ec675ed79275e694dda90f0f97fc6ac0e7a commit r16-1255-gbe205ec675ed79275e694dda90f0f97fc6ac0e7a Author: Pan Li Date: Fri Jun 6 09:33:21 2025 +0800 RISC-V: Combine vec_duplicate + vidvu.vv to vdivu.vx on GR2VR cost This patch would like to combine the vec_d

[gcc r16-1258] RISC-V: Reconcile the existing test for vdivu.vx combine

https://gcc.gnu.org/g:08a0b6dabd76c8ca4366a59c2fdcd1ef8f8b1cb9 commit r16-1258-g08a0b6dabd76c8ca4366a59c2fdcd1ef8f8b1cb9 Author: Pan Li Date: Fri Jun 6 10:03:50 2025 +0800 RISC-V: Reconcile the existing test for vdivu.vx combine Some existing vdiv related test need some adjust for

[gcc r16-1182] RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv

https://gcc.gnu.org/g:8cf31de8c8fec295c5f627b399d9e015df266297 commit r16-1182-g8cf31de8c8fec295c5f627b399d9e015df266297 Author: Pan Li Date: Thu Jun 5 11:04:33 2025 +0800 RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv The div of rvv has not such insn v2 = div (vec_dup

[gcc r16-1098] RISC-V: Leverage get_vector_binary_rtx_cost to avoid code dup [NFC]

https://gcc.gnu.org/g:a8b38447efe2c74094b865e1cc44723659dac2e4 commit r16-1098-ga8b38447efe2c74094b865e1cc44723659dac2e4 Author: Pan Li Date: Wed Jun 4 11:06:52 2025 +0800 RISC-V: Leverage get_vector_binary_rtx_cost to avoid code dup [NFC] Some similar code could be wrapped to fun

[gcc r16-1080] RISC-V: Combine vec_duplicate + vidv.vv to vdiv.vx on GR2VR cost

https://gcc.gnu.org/g:451737734b8913c5de8cfe597d5d20477af6c5ef commit r16-1080-g451737734b8913c5de8cfe597d5d20477af6c5ef Author: Pan Li Date: Mon Jun 2 16:56:59 2025 +0800 RISC-V: Combine vec_duplicate + vidv.vv to vdiv.vx on GR2VR cost This patch would like to combine the vec_dup

[gcc r16-1083] RISC-V: Reconcile the existing test for vdiv.vx combine

https://gcc.gnu.org/g:4c2d94aed41778226ae08c718459eed5ee65d455 commit r16-1083-g4c2d94aed41778226ae08c718459eed5ee65d455 Author: Pan Li Date: Mon Jun 2 21:21:18 2025 +0800 RISC-V: Reconcile the existing test for vdiv.vx combine Some existing vdiv related test need some adjust for

[gcc r16-1081] RISC-V: Add test for vec_duplicate + vdiv.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:a5222407c993c01dcce53590c5fa799f7a927b4f commit r16-1081-ga5222407c993c01dcce53590c5fa799f7a927b4f Author: Pan Li Date: Mon Jun 2 17:01:27 2025 +0800 RISC-V: Add test for vec_duplicate + vdiv.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check t

[gcc r16-1082] RISC-V: Add test for vec_duplicate + vdiv.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:661c7377df05010ffae8a81c17b3870f8d927608 commit r16-1082-g661c7377df05010ffae8a81c17b3870f8d927608 Author: Pan Li Date: Mon Jun 2 17:03:02 2025 +0800 RISC-V: Add test for vec_duplicate + vdiv.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check te

[gcc r16-1034] RISC-V: Fix line too long format issue for autovect.md [NFC]

https://gcc.gnu.org/g:c33ad4f3f2a652fcd07d249736b6c5233fa1da8e commit r16-1034-gc33ad4f3f2a652fcd07d249736b6c5233fa1da8e Author: Pan Li Date: Sat May 31 11:01:06 2025 +0800 RISC-V: Fix line too long format issue for autovect.md [NFC] Inspired by the avg_ceil patches, notice there

[gcc r16-1015] RISC-V: Add test cases for avg_ceil vaadd implementation

https://gcc.gnu.org/g:72972bc3a1b35bcfc83d801a9da45121210bc3c3 commit r16-1015-g72972bc3a1b35bcfc83d801a9da45121210bc3c3 Author: Pan Li Date: Thu May 29 21:33:44 2025 +0800 RISC-V: Add test cases for avg_ceil vaadd implementation Add asm and run testcase for avg_ceil vaadd impleme

[gcc r16-1014] RISC-V: Reconcile the existing test for avg_ceil

https://gcc.gnu.org/g:6d4c38b232e1d58c85de7959411cc1562a7a0bdc commit r16-1014-g6d4c38b232e1d58c85de7959411cc1562a7a0bdc Author: Pan Li Date: Thu May 29 21:31:54 2025 +0800 RISC-V: Reconcile the existing test for avg_ceil Some existing avg_floor test need updated due to change to

[gcc r16-1013] RISC-V: Leverage vaadd.vv for signed standard name avg_ceil

https://gcc.gnu.org/g:6bcd522438250d014d0fa1e4bcf2aa049934c887 commit r16-1013-g6bcd522438250d014d0fa1e4bcf2aa049934c887 Author: Pan Li Date: Thu May 29 21:19:36 2025 +0800 RISC-V: Leverage vaadd.vv for signed standard name avg_ceil The avg_ceil has the rounding mode towards +inf,

[gcc r16-947] RISC-V: Add test for vec_duplicate + vmul.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:663cb52b0e8df70830a8def86a5254a59d373732 commit r16-947-g663cb52b0e8df70830a8def86a5254a59d373732 Author: Pan Li Date: Wed May 28 16:22:04 2025 +0800 RISC-V: Add test for vec_duplicate + vmul.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check te

[gcc r16-946] RISC-V: Add test for vec_duplicate + vmul.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:b36bde2fc5cc7048f294adee45fb9a0be0092d13 commit r16-946-gb36bde2fc5cc7048f294adee45fb9a0be0092d13 Author: Pan Li Date: Wed May 28 16:20:32 2025 +0800 RISC-V: Add test for vec_duplicate + vmul.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check t

[gcc r16-945] RISC-V: Combine vec_duplicate + vmul.vv to vmul.vx on GR2VR cost

https://gcc.gnu.org/g:2e4267a6fe143bd72376653812f59f343cb1c101 commit r16-945-g2e4267a6fe143bd72376653812f59f343cb1c101 Author: Pan Li Date: Wed May 28 16:16:49 2025 +0800 RISC-V: Combine vec_duplicate + vmul.vv to vmul.vx on GR2VR cost This patch would like to combine the vec_dup

[gcc r16-932] RISC-V: Reconcile the existing test for avg_floor

https://gcc.gnu.org/g:ef0c2ed1382d6edc26ba63322e1009f9acf97efd commit r16-932-gef0c2ed1382d6edc26ba63322e1009f9acf97efd Author: Pan Li Date: Tue May 27 10:24:56 2025 +0800 RISC-V: Reconcile the existing test for avg_floor Some existing avg_floor test need updated due to change to

[gcc r16-933] RISC-V: Add test cases for avg_floor vaadd implementation

https://gcc.gnu.org/g:d4a2f9ba6ece32fb8500f10204fcf409aa26fbfb commit r16-933-gd4a2f9ba6ece32fb8500f10204fcf409aa26fbfb Author: Pan Li Date: Tue May 27 10:27:01 2025 +0800 RISC-V: Add test cases for avg_floor vaadd implementation Add asm and run testcase for avg_floor vaadd implem

[gcc r16-931] RISC-V: Leverage vaadd.vv for signed standard name avg_floor

https://gcc.gnu.org/g:f4456ea9e955b971573cdfebd1d10797fd30ad3a commit r16-931-gf4456ea9e955b971573cdfebd1d10797fd30ad3a Author: Pan Li Date: Tue May 27 09:53:56 2025 +0800 RISC-V: Leverage vaadd.vv for signed standard name avg_floor The signed avg_floor totally match the sematics

[gcc r16-898] RISC-V: Add test for vec_duplicate + vxor.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:f11e5e96cac227885d444318a60fa2a1cf614867 commit r16-898-gf11e5e96cac227885d444318a60fa2a1cf614867 Author: Pan Li Date: Sun May 25 17:17:34 2025 +0800 RISC-V: Add test for vec_duplicate + vxor.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check te

[gcc r16-897] RISC-V: Add test for vec_duplicate + vxor.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:8c6f583d3d87b63c5ecace779ef359b568f7b747 commit r16-897-g8c6f583d3d87b63c5ecace779ef359b568f7b747 Author: Pan Li Date: Sun May 25 17:16:09 2025 +0800 RISC-V: Add test for vec_duplicate + vxor.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check t

[gcc r16-896] RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR cost

https://gcc.gnu.org/g:df691d8de1f4ea21763ca579bc6fb1fab38512da commit r16-896-gdf691d8de1f4ea21763ca579bc6fb1fab38512da Author: Pan Li Date: Sun May 25 17:13:09 2025 +0800 RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR cost This patch would like to combine the vec_dup

[gcc r16-860] RISC-V: Add test for vec_duplicate + vor.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:736ae0a005d21230b141e9eb94cfd61032f8db19 commit r16-860-g736ae0a005d21230b141e9eb94cfd61032f8db19 Author: Pan Li Date: Fri May 23 13:29:32 2025 +0800 RISC-V: Add test for vec_duplicate + vor.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check tes

[gcc r16-859] RISC-V: Add test for vec_duplicate + vor.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:2e09013aef8326b52a9bd0b4baf8cd16ebe5fece commit r16-859-g2e09013aef8326b52a9bd0b4baf8cd16ebe5fece Author: Pan Li Date: Fri May 23 13:26:41 2025 +0800 RISC-V: Add test for vec_duplicate + vor.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check te

[gcc r16-858] RISC-V: Combine vec_duplicate + vor.vv to vor.vx on GR2VR cost

https://gcc.gnu.org/g:2fab99bb95db4dd47dbd07137a4c03776f476c55 commit r16-858-g2fab99bb95db4dd47dbd07137a4c03776f476c55 Author: Pan Li Date: Fri May 23 13:22:35 2025 +0800 RISC-V: Combine vec_duplicate + vor.vv to vor.vx on GR2VR cost This patch would like to combine the vec_dupli

[gcc r16-805] RISC-V: Add test for vec_duplicate + vand.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:b7b914622e8da0d5f10027d9a4db418f21ed2ddc commit r16-805-gb7b914622e8da0d5f10027d9a4db418f21ed2ddc Author: Pan Li Date: Tue May 20 15:06:34 2025 +0800 RISC-V: Add test for vec_duplicate + vand.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check t

[gcc r16-806] RISC-V: Add test for vec_duplicate + vand.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:4f02bfb62da3a0e32a86cc2ac1171b11da026e7c commit r16-806-g4f02bfb62da3a0e32a86cc2ac1171b11da026e7c Author: Pan Li Date: Tue May 20 22:30:04 2025 +0800 RISC-V: Add test for vec_duplicate + vand.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check te

[gcc r16-804] RISC-V: RISC-V: Combine vec_duplicate + vand.vv to vand.vx on GR2VR cost

https://gcc.gnu.org/g:ad041944f1060be0c9280421a065037aa14e169e commit r16-804-gad041944f1060be0c9280421a065037aa14e169e Author: Pan Li Date: Tue May 20 15:00:15 2025 +0800 RISC-V: RISC-V: Combine vec_duplicate + vand.vv to vand.vx on GR2VR cost This patch would like to combine the

[gcc r16-746] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 0

https://gcc.gnu.org/g:82de5c5c13925b3e23e3bef86ab6386f7b971bba commit r16-746-g82de5c5c13925b3e23e3bef86ab6386f7b971bba Author: Pan Li Date: Sun May 18 19:53:46 2025 +0800 RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 0 Add asm dump check test for v

[gcc r16-748] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 2

https://gcc.gnu.org/g:d1697f3d685ac9df6136eefc305b5f1297087fbe commit r16-748-gd1697f3d685ac9df6136eefc305b5f1297087fbe Author: Pan Li Date: Sun May 18 20:09:05 2025 +0800 RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 2 Add asm dump check test for v

[gcc r16-749] RISC-V: Tweak the asm check test of vx combine on GR2VR cost [NFC]

https://gcc.gnu.org/g:dd8ee1df28e0a26b666d64a6098a121fd22aa90d commit r16-749-gdd8ee1df28e0a26b666d64a6098a121fd22aa90d Author: Pan Li Date: Mon May 19 10:06:35 2025 +0800 RISC-V: Tweak the asm check test of vx combine on GR2VR cost [NFC] Tweak the asm check with define T uint8_t

[gcc r16-745] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 0 with GR2VR cost 15

https://gcc.gnu.org/g:7e12feefb457b2c674fafea0d0f39823cc376cd4 commit r16-745-g7e12feefb457b2c674fafea0d0f39823cc376cd4 Author: Pan Li Date: Sun May 18 17:17:46 2025 +0800 RISC-V: Add test for vec_duplicate + vrsub.vv combine case 0 with GR2VR cost 15 Add asm dump check test for

[gcc r16-747] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 1

https://gcc.gnu.org/g:a05beea2b87778bcf1007ce5790f9a8e6d940af7 commit r16-747-ga05beea2b87778bcf1007ce5790f9a8e6d940af7 Author: Pan Li Date: Sun May 18 20:02:11 2025 +0800 RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 1 Add asm dump check test for v

[gcc r16-743] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 0 with GR2VR cost 0

https://gcc.gnu.org/g:7c5c12b938e2eec6384d733494651a8fb474e222 commit r16-743-g7c5c12b938e2eec6384d733494651a8fb474e222 Author: Pan Li Date: Sun May 18 16:49:29 2025 +0800 RISC-V: Add test for vec_duplicate + vrsub.vv combine case 0 with GR2VR cost 0 Add asm dump check and run te

[gcc r16-742] RISC-V: Combine vec_duplicate + vrsub.vv to vrsub.vx on GR2VR cost

https://gcc.gnu.org/g:4a8ce14a58177905878400bae5980eed32973085 commit r16-742-g4a8ce14a58177905878400bae5980eed32973085 Author: Pan Li Date: Sun May 18 16:41:01 2025 +0800 RISC-V: Combine vec_duplicate + vrsub.vv to vrsub.vx on GR2VR cost This patch would like to combine the vec_d

[gcc r16-744] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 0 with GR2VR cost 1

https://gcc.gnu.org/g:e604b48288b41402539d22531cfd96003382aff8 commit r16-744-ge604b48288b41402539d22531cfd96003382aff8 Author: Pan Li Date: Sun May 18 17:07:37 2025 +0800 RISC-V: Add test for vec_duplicate + vrsub.vv combine case 0 with GR2VR cost 1 Add asm dump check test for v

[gcc r16-707] RISC-V: Avoid scalar unsigned SAT_ADD test data duplication

https://gcc.gnu.org/g:83477c3f6650429a7cdcb1b6da950c421aa2f77d commit r16-707-g83477c3f6650429a7cdcb1b6da950c421aa2f77d Author: Pan Li Date: Fri May 16 15:34:51 2025 +0800 RISC-V: Avoid scalar unsigned SAT_ADD test data duplication Some of the previous scalar unsigned SAT_ADD test

[gcc r16-681] RISC-V: Reuse test name for vx combine test data [NFC]

https://gcc.gnu.org/g:6eead9665eaf0d26aa162000df0aef142c55527e commit r16-681-g6eead9665eaf0d26aa162000df0aef142c55527e Author: Pan Li Date: Tue May 13 22:54:17 2025 +0800 RISC-V: Reuse test name for vx combine test data [NFC] For run test, we have a name like add/sub to indicate

[gcc r16-680] RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 2

https://gcc.gnu.org/g:a484b523e3e4d78c810bb9a70a86a8fa567378b7 commit r16-680-ga484b523e3e4d78c810bb9a70a86a8fa567378b7 Author: Pan Li Date: Tue May 13 22:47:13 2025 +0800 RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 2 Add asm dump check test for ve

[gcc r16-679] RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 1

https://gcc.gnu.org/g:5f523f6255cc48643adab431839557dc3d73d70f commit r16-679-g5f523f6255cc48643adab431839557dc3d73d70f Author: Pan Li Date: Tue May 13 22:38:57 2025 +0800 RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 1 Add asm dump check test for ve

[gcc r16-678] RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 0

https://gcc.gnu.org/g:621cb3dc9996a160e3e65bce4a8e61da26caafa7 commit r16-678-g621cb3dc9996a160e3e65bce4a8e61da26caafa7 Author: Pan Li Date: Tue May 13 22:32:03 2025 +0800 RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 0 Add asm dump check test for vec

[gcc r16-677] RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 15

https://gcc.gnu.org/g:f8cdcca76f28fae932079ebdf208b7586282369c commit r16-677-gf8cdcca76f28fae932079ebdf208b7586282369c Author: Pan Li Date: Sun May 11 16:32:51 2025 +0800 RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 15 Add asm dump check test for v

[gcc r16-676] RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 1

https://gcc.gnu.org/g:ee2dcc2236e28e8b86a9c953d4723364add61128 commit r16-676-gee2dcc2236e28e8b86a9c953d4723364add61128 Author: Pan Li Date: Sun May 11 16:31:16 2025 +0800 RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 1 Add asm dump check test for ve

[gcc r16-675] RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 0

https://gcc.gnu.org/g:2e459a5466dc66f90f108418e4cbfd5d2d91daa1 commit r16-675-g2e459a5466dc66f90f108418e4cbfd5d2d91daa1 Author: Pan Li Date: Sun May 11 16:27:48 2025 +0800 RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 0 Add asm dump check and run test

[gcc r16-674] RISC-V: Adjust vx combine test case to avoid name conflict

https://gcc.gnu.org/g:4f4eb9b7dd7dad0eec4eae8443a98eeded4fe070 commit r16-674-g4f4eb9b7dd7dad0eec4eae8443a98eeded4fe070 Author: Pan Li Date: Tue May 13 11:12:53 2025 +0800 RISC-V: Adjust vx combine test case to avoid name conflict Given we will put all vx combine for int8 in a sin

[gcc r16-673] RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combine [NFC]

https://gcc.gnu.org/g:414d8f3d8574ec30e585404d7fc5c7268a006444 commit r16-673-g414d8f3d8574ec30e585404d7fc5c7268a006444 Author: Pan Li Date: Tue May 13 10:00:35 2025 +0800 RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combine [NFC] We would like to arrange all vx combine as

[gcc r16-672] RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost

https://gcc.gnu.org/g:8814d5d50c6d4103f35545ec934be64a82b70d23 commit r16-672-g8814d5d50c6d4103f35545ec934be64a82b70d23 Author: Pan Li Date: Sun May 11 16:20:28 2025 +0800 RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost This patch would like to combine the vec_dup

[gcc r16-574] Match: Support form 7 for unsigned integer SAT_ADD

https://gcc.gnu.org/g:656db31e4448e7b51a919dc1acfb3080c82f43de commit r16-574-g656db31e4448e7b51a919dc1acfb3080c82f43de Author: Pan Li Date: Mon Apr 28 20:35:08 2025 +0800 Match: Support form 7 for unsigned integer SAT_ADD This patch would like to support the form 7 of the unsigne

[gcc r16-576] RISC-V: Add testcases for vector unsigned integer SAT_ADD form 7

https://gcc.gnu.org/g:c273a1c1846207082b60fe10c18f5c86dbcfd413 commit r16-576-gc273a1c1846207082b60fe10c18f5c86dbcfd413 Author: Pan Li Date: Mon Apr 28 20:35:10 2025 +0800 RISC-V: Add testcases for vector unsigned integer SAT_ADD form 7 This patch will add testcase for unsigned in

[gcc r16-575] RISC-V: Add testcases for scalar unsigned integer SAT_ADD form 7

https://gcc.gnu.org/g:f6535d433e250421f6c1f2f691c04e613d63a694 commit r16-575-gf6535d433e250421f6c1f2f691c04e613d63a694 Author: Pan Li Date: Mon Apr 28 20:35:09 2025 +0800 RISC-V: Add testcases for scalar unsigned integer SAT_ADD form 7 This patch will add testcase for unsigned in

[gcc r16-484] RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 0

https://gcc.gnu.org/g:5ee51001ec056356eb8f6cbece73cff6d73003e5 commit r16-484-g5ee51001ec056356eb8f6cbece73cff6d73003e5 Author: Pan Li Date: Thu May 8 11:19:11 2025 +0800 RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 0 Add asm dump check and for

[gcc r16-485] RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 1

https://gcc.gnu.org/g:6a718d401d37880a5ed74210b1a75783e8ea9c38 commit r16-485-g6a718d401d37880a5ed74210b1a75783e8ea9c38 Author: Pan Li Date: Thu May 8 11:21:35 2025 +0800 RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 1 Add asm dump check and for

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