[gcc r16-1034] RISC-V: Fix line too long format issue for autovect.md [NFC]

https://gcc.gnu.org/g:c33ad4f3f2a652fcd07d249736b6c5233fa1da8e commit r16-1034-gc33ad4f3f2a652fcd07d249736b6c5233fa1da8e Author: Pan Li Date: Sat May 31 11:01:06 2025 +0800 RISC-V: Fix line too long format issue for autovect.md [NFC] Inspired by the avg_ceil patches, notice there

[gcc r16-1015] RISC-V: Add test cases for avg_ceil vaadd implementation

https://gcc.gnu.org/g:72972bc3a1b35bcfc83d801a9da45121210bc3c3 commit r16-1015-g72972bc3a1b35bcfc83d801a9da45121210bc3c3 Author: Pan Li Date: Thu May 29 21:33:44 2025 +0800 RISC-V: Add test cases for avg_ceil vaadd implementation Add asm and run testcase for avg_ceil vaadd impleme

[gcc r16-1014] RISC-V: Reconcile the existing test for avg_ceil

https://gcc.gnu.org/g:6d4c38b232e1d58c85de7959411cc1562a7a0bdc commit r16-1014-g6d4c38b232e1d58c85de7959411cc1562a7a0bdc Author: Pan Li Date: Thu May 29 21:31:54 2025 +0800 RISC-V: Reconcile the existing test for avg_ceil Some existing avg_floor test need updated due to change to

[gcc r16-1013] RISC-V: Leverage vaadd.vv for signed standard name avg_ceil

https://gcc.gnu.org/g:6bcd522438250d014d0fa1e4bcf2aa049934c887 commit r16-1013-g6bcd522438250d014d0fa1e4bcf2aa049934c887 Author: Pan Li Date: Thu May 29 21:19:36 2025 +0800 RISC-V: Leverage vaadd.vv for signed standard name avg_ceil The avg_ceil has the rounding mode towards +inf,

[gcc r16-947] RISC-V: Add test for vec_duplicate + vmul.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:663cb52b0e8df70830a8def86a5254a59d373732 commit r16-947-g663cb52b0e8df70830a8def86a5254a59d373732 Author: Pan Li Date: Wed May 28 16:22:04 2025 +0800 RISC-V: Add test for vec_duplicate + vmul.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check te

[gcc r16-946] RISC-V: Add test for vec_duplicate + vmul.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:b36bde2fc5cc7048f294adee45fb9a0be0092d13 commit r16-946-gb36bde2fc5cc7048f294adee45fb9a0be0092d13 Author: Pan Li Date: Wed May 28 16:20:32 2025 +0800 RISC-V: Add test for vec_duplicate + vmul.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check t

[gcc r16-945] RISC-V: Combine vec_duplicate + vmul.vv to vmul.vx on GR2VR cost

https://gcc.gnu.org/g:2e4267a6fe143bd72376653812f59f343cb1c101 commit r16-945-g2e4267a6fe143bd72376653812f59f343cb1c101 Author: Pan Li Date: Wed May 28 16:16:49 2025 +0800 RISC-V: Combine vec_duplicate + vmul.vv to vmul.vx on GR2VR cost This patch would like to combine the vec_dup

[gcc r16-932] RISC-V: Reconcile the existing test for avg_floor

https://gcc.gnu.org/g:ef0c2ed1382d6edc26ba63322e1009f9acf97efd commit r16-932-gef0c2ed1382d6edc26ba63322e1009f9acf97efd Author: Pan Li Date: Tue May 27 10:24:56 2025 +0800 RISC-V: Reconcile the existing test for avg_floor Some existing avg_floor test need updated due to change to

[gcc r16-933] RISC-V: Add test cases for avg_floor vaadd implementation

https://gcc.gnu.org/g:d4a2f9ba6ece32fb8500f10204fcf409aa26fbfb commit r16-933-gd4a2f9ba6ece32fb8500f10204fcf409aa26fbfb Author: Pan Li Date: Tue May 27 10:27:01 2025 +0800 RISC-V: Add test cases for avg_floor vaadd implementation Add asm and run testcase for avg_floor vaadd implem

[gcc r16-931] RISC-V: Leverage vaadd.vv for signed standard name avg_floor

https://gcc.gnu.org/g:f4456ea9e955b971573cdfebd1d10797fd30ad3a commit r16-931-gf4456ea9e955b971573cdfebd1d10797fd30ad3a Author: Pan Li Date: Tue May 27 09:53:56 2025 +0800 RISC-V: Leverage vaadd.vv for signed standard name avg_floor The signed avg_floor totally match the sematics

[gcc r16-898] RISC-V: Add test for vec_duplicate + vxor.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:f11e5e96cac227885d444318a60fa2a1cf614867 commit r16-898-gf11e5e96cac227885d444318a60fa2a1cf614867 Author: Pan Li Date: Sun May 25 17:17:34 2025 +0800 RISC-V: Add test for vec_duplicate + vxor.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check te

[gcc r16-897] RISC-V: Add test for vec_duplicate + vxor.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:8c6f583d3d87b63c5ecace779ef359b568f7b747 commit r16-897-g8c6f583d3d87b63c5ecace779ef359b568f7b747 Author: Pan Li Date: Sun May 25 17:16:09 2025 +0800 RISC-V: Add test for vec_duplicate + vxor.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check t

[gcc r16-896] RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR cost

https://gcc.gnu.org/g:df691d8de1f4ea21763ca579bc6fb1fab38512da commit r16-896-gdf691d8de1f4ea21763ca579bc6fb1fab38512da Author: Pan Li Date: Sun May 25 17:13:09 2025 +0800 RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR cost This patch would like to combine the vec_dup

[gcc r16-860] RISC-V: Add test for vec_duplicate + vor.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:736ae0a005d21230b141e9eb94cfd61032f8db19 commit r16-860-g736ae0a005d21230b141e9eb94cfd61032f8db19 Author: Pan Li Date: Fri May 23 13:29:32 2025 +0800 RISC-V: Add test for vec_duplicate + vor.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check tes

[gcc r16-859] RISC-V: Add test for vec_duplicate + vor.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:2e09013aef8326b52a9bd0b4baf8cd16ebe5fece commit r16-859-g2e09013aef8326b52a9bd0b4baf8cd16ebe5fece Author: Pan Li Date: Fri May 23 13:26:41 2025 +0800 RISC-V: Add test for vec_duplicate + vor.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check te

[gcc r16-858] RISC-V: Combine vec_duplicate + vor.vv to vor.vx on GR2VR cost

https://gcc.gnu.org/g:2fab99bb95db4dd47dbd07137a4c03776f476c55 commit r16-858-g2fab99bb95db4dd47dbd07137a4c03776f476c55 Author: Pan Li Date: Fri May 23 13:22:35 2025 +0800 RISC-V: Combine vec_duplicate + vor.vv to vor.vx on GR2VR cost This patch would like to combine the vec_dupli

[gcc r16-805] RISC-V: Add test for vec_duplicate + vand.vv combine case 0 with GR2VR cost 0, 2 and 15

https://gcc.gnu.org/g:b7b914622e8da0d5f10027d9a4db418f21ed2ddc commit r16-805-gb7b914622e8da0d5f10027d9a4db418f21ed2ddc Author: Pan Li Date: Tue May 20 15:06:34 2025 +0800 RISC-V: Add test for vec_duplicate + vand.vv combine case 0 with GR2VR cost 0, 2 and 15 Add asm dump check t

[gcc r16-806] RISC-V: Add test for vec_duplicate + vand.vv combine case 1 with GR2VR cost 0, 1 and 2

https://gcc.gnu.org/g:4f02bfb62da3a0e32a86cc2ac1171b11da026e7c commit r16-806-g4f02bfb62da3a0e32a86cc2ac1171b11da026e7c Author: Pan Li Date: Tue May 20 22:30:04 2025 +0800 RISC-V: Add test for vec_duplicate + vand.vv combine case 1 with GR2VR cost 0, 1 and 2 Add asm dump check te

[gcc r16-804] RISC-V: RISC-V: Combine vec_duplicate + vand.vv to vand.vx on GR2VR cost

https://gcc.gnu.org/g:ad041944f1060be0c9280421a065037aa14e169e commit r16-804-gad041944f1060be0c9280421a065037aa14e169e Author: Pan Li Date: Tue May 20 15:00:15 2025 +0800 RISC-V: RISC-V: Combine vec_duplicate + vand.vv to vand.vx on GR2VR cost This patch would like to combine the

[gcc r16-746] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 0

https://gcc.gnu.org/g:82de5c5c13925b3e23e3bef86ab6386f7b971bba commit r16-746-g82de5c5c13925b3e23e3bef86ab6386f7b971bba Author: Pan Li Date: Sun May 18 19:53:46 2025 +0800 RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 0 Add asm dump check test for v

[gcc r16-748] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 2

https://gcc.gnu.org/g:d1697f3d685ac9df6136eefc305b5f1297087fbe commit r16-748-gd1697f3d685ac9df6136eefc305b5f1297087fbe Author: Pan Li Date: Sun May 18 20:09:05 2025 +0800 RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 2 Add asm dump check test for v

[gcc r16-749] RISC-V: Tweak the asm check test of vx combine on GR2VR cost [NFC]

https://gcc.gnu.org/g:dd8ee1df28e0a26b666d64a6098a121fd22aa90d commit r16-749-gdd8ee1df28e0a26b666d64a6098a121fd22aa90d Author: Pan Li Date: Mon May 19 10:06:35 2025 +0800 RISC-V: Tweak the asm check test of vx combine on GR2VR cost [NFC] Tweak the asm check with define T uint8_t

[gcc r16-745] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 0 with GR2VR cost 15

https://gcc.gnu.org/g:7e12feefb457b2c674fafea0d0f39823cc376cd4 commit r16-745-g7e12feefb457b2c674fafea0d0f39823cc376cd4 Author: Pan Li Date: Sun May 18 17:17:46 2025 +0800 RISC-V: Add test for vec_duplicate + vrsub.vv combine case 0 with GR2VR cost 15 Add asm dump check test for

[gcc r16-747] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 1

https://gcc.gnu.org/g:a05beea2b87778bcf1007ce5790f9a8e6d940af7 commit r16-747-ga05beea2b87778bcf1007ce5790f9a8e6d940af7 Author: Pan Li Date: Sun May 18 20:02:11 2025 +0800 RISC-V: Add test for vec_duplicate + vrsub.vv combine case 1 with GR2VR cost 1 Add asm dump check test for v

[gcc r16-743] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 0 with GR2VR cost 0

https://gcc.gnu.org/g:7c5c12b938e2eec6384d733494651a8fb474e222 commit r16-743-g7c5c12b938e2eec6384d733494651a8fb474e222 Author: Pan Li Date: Sun May 18 16:49:29 2025 +0800 RISC-V: Add test for vec_duplicate + vrsub.vv combine case 0 with GR2VR cost 0 Add asm dump check and run te

[gcc r16-742] RISC-V: Combine vec_duplicate + vrsub.vv to vrsub.vx on GR2VR cost

https://gcc.gnu.org/g:4a8ce14a58177905878400bae5980eed32973085 commit r16-742-g4a8ce14a58177905878400bae5980eed32973085 Author: Pan Li Date: Sun May 18 16:41:01 2025 +0800 RISC-V: Combine vec_duplicate + vrsub.vv to vrsub.vx on GR2VR cost This patch would like to combine the vec_d

[gcc r16-744] RISC-V: Add test for vec_duplicate + vrsub.vv combine case 0 with GR2VR cost 1

https://gcc.gnu.org/g:e604b48288b41402539d22531cfd96003382aff8 commit r16-744-ge604b48288b41402539d22531cfd96003382aff8 Author: Pan Li Date: Sun May 18 17:07:37 2025 +0800 RISC-V: Add test for vec_duplicate + vrsub.vv combine case 0 with GR2VR cost 1 Add asm dump check test for v

[gcc r16-707] RISC-V: Avoid scalar unsigned SAT_ADD test data duplication

https://gcc.gnu.org/g:83477c3f6650429a7cdcb1b6da950c421aa2f77d commit r16-707-g83477c3f6650429a7cdcb1b6da950c421aa2f77d Author: Pan Li Date: Fri May 16 15:34:51 2025 +0800 RISC-V: Avoid scalar unsigned SAT_ADD test data duplication Some of the previous scalar unsigned SAT_ADD test

[gcc r16-681] RISC-V: Reuse test name for vx combine test data [NFC]

https://gcc.gnu.org/g:6eead9665eaf0d26aa162000df0aef142c55527e commit r16-681-g6eead9665eaf0d26aa162000df0aef142c55527e Author: Pan Li Date: Tue May 13 22:54:17 2025 +0800 RISC-V: Reuse test name for vx combine test data [NFC] For run test, we have a name like add/sub to indicate

[gcc r16-680] RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 2

https://gcc.gnu.org/g:a484b523e3e4d78c810bb9a70a86a8fa567378b7 commit r16-680-ga484b523e3e4d78c810bb9a70a86a8fa567378b7 Author: Pan Li Date: Tue May 13 22:47:13 2025 +0800 RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 2 Add asm dump check test for ve

[gcc r16-679] RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 1

https://gcc.gnu.org/g:5f523f6255cc48643adab431839557dc3d73d70f commit r16-679-g5f523f6255cc48643adab431839557dc3d73d70f Author: Pan Li Date: Tue May 13 22:38:57 2025 +0800 RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 1 Add asm dump check test for ve

[gcc r16-678] RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 0

https://gcc.gnu.org/g:621cb3dc9996a160e3e65bce4a8e61da26caafa7 commit r16-678-g621cb3dc9996a160e3e65bce4a8e61da26caafa7 Author: Pan Li Date: Tue May 13 22:32:03 2025 +0800 RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 0 Add asm dump check test for vec

[gcc r16-677] RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 15

https://gcc.gnu.org/g:f8cdcca76f28fae932079ebdf208b7586282369c commit r16-677-gf8cdcca76f28fae932079ebdf208b7586282369c Author: Pan Li Date: Sun May 11 16:32:51 2025 +0800 RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 15 Add asm dump check test for v

[gcc r16-676] RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 1

https://gcc.gnu.org/g:ee2dcc2236e28e8b86a9c953d4723364add61128 commit r16-676-gee2dcc2236e28e8b86a9c953d4723364add61128 Author: Pan Li Date: Sun May 11 16:31:16 2025 +0800 RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 1 Add asm dump check test for ve

[gcc r16-675] RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 0

https://gcc.gnu.org/g:2e459a5466dc66f90f108418e4cbfd5d2d91daa1 commit r16-675-g2e459a5466dc66f90f108418e4cbfd5d2d91daa1 Author: Pan Li Date: Sun May 11 16:27:48 2025 +0800 RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 0 Add asm dump check and run test

[gcc r16-674] RISC-V: Adjust vx combine test case to avoid name conflict

https://gcc.gnu.org/g:4f4eb9b7dd7dad0eec4eae8443a98eeded4fe070 commit r16-674-g4f4eb9b7dd7dad0eec4eae8443a98eeded4fe070 Author: Pan Li Date: Tue May 13 11:12:53 2025 +0800 RISC-V: Adjust vx combine test case to avoid name conflict Given we will put all vx combine for int8 in a sin

[gcc r16-673] RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combine [NFC]

https://gcc.gnu.org/g:414d8f3d8574ec30e585404d7fc5c7268a006444 commit r16-673-g414d8f3d8574ec30e585404d7fc5c7268a006444 Author: Pan Li Date: Tue May 13 10:00:35 2025 +0800 RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combine [NFC] We would like to arrange all vx combine as

[gcc r16-672] RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost

https://gcc.gnu.org/g:8814d5d50c6d4103f35545ec934be64a82b70d23 commit r16-672-g8814d5d50c6d4103f35545ec934be64a82b70d23 Author: Pan Li Date: Sun May 11 16:20:28 2025 +0800 RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost This patch would like to combine the vec_dup

[gcc r16-574] Match: Support form 7 for unsigned integer SAT_ADD

https://gcc.gnu.org/g:656db31e4448e7b51a919dc1acfb3080c82f43de commit r16-574-g656db31e4448e7b51a919dc1acfb3080c82f43de Author: Pan Li Date: Mon Apr 28 20:35:08 2025 +0800 Match: Support form 7 for unsigned integer SAT_ADD This patch would like to support the form 7 of the unsigne

[gcc r16-576] RISC-V: Add testcases for vector unsigned integer SAT_ADD form 7

https://gcc.gnu.org/g:c273a1c1846207082b60fe10c18f5c86dbcfd413 commit r16-576-gc273a1c1846207082b60fe10c18f5c86dbcfd413 Author: Pan Li Date: Mon Apr 28 20:35:10 2025 +0800 RISC-V: Add testcases for vector unsigned integer SAT_ADD form 7 This patch will add testcase for unsigned in

[gcc r16-575] RISC-V: Add testcases for scalar unsigned integer SAT_ADD form 7

https://gcc.gnu.org/g:f6535d433e250421f6c1f2f691c04e613d63a694 commit r16-575-gf6535d433e250421f6c1f2f691c04e613d63a694 Author: Pan Li Date: Mon Apr 28 20:35:09 2025 +0800 RISC-V: Add testcases for scalar unsigned integer SAT_ADD form 7 This patch will add testcase for unsigned in

[gcc r16-484] RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 0

https://gcc.gnu.org/g:5ee51001ec056356eb8f6cbece73cff6d73003e5 commit r16-484-g5ee51001ec056356eb8f6cbece73cff6d73003e5 Author: Pan Li Date: Thu May 8 11:19:11 2025 +0800 RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 0 Add asm dump check and for

[gcc r16-485] RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 1

https://gcc.gnu.org/g:6a718d401d37880a5ed74210b1a75783e8ea9c38 commit r16-485-g6a718d401d37880a5ed74210b1a75783e8ea9c38 Author: Pan Li Date: Thu May 8 11:21:35 2025 +0800 RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 1 Add asm dump check and for

[gcc r16-486] RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 2

https://gcc.gnu.org/g:8dba9c7ec97ef6e5e891c77a0f0d536860172beb commit r16-486-g8dba9c7ec97ef6e5e891c77a0f0d536860172beb Author: Pan Li Date: Thu May 8 11:25:04 2025 +0800 RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 2 Add asm dump check and for

[gcc r16-483] RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0

https://gcc.gnu.org/g:cd694ab6c758cdbcf5f8816a0f2bd70448681c6a commit r16-483-gcd694ab6c758cdbcf5f8816a0f2bd70448681c6a Author: Pan Li Date: Wed May 7 20:48:40 2025 +0800 RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0 This patch would like to rename the VX_BINARY within

[gcc r16-482] RISC-V: Separate the test running of rvv vx_vf

https://gcc.gnu.org/g:b81e970de6f6ec6e8d2afa850c9abe07280c91ff commit r16-482-gb81e970de6f6ec6e8d2afa850c9abe07280c91ff Author: Pan Li Date: Thu May 8 10:00:50 2025 +0800 RISC-V: Separate the test running of rvv vx_vf The default test running in rvv.exp takes the -fno-vect-cost-mo

[gcc r16-409] RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 1

https://gcc.gnu.org/g:c10491efc108bd4fc2d983bcabb50506d09e2a17 commit r16-409-gc10491efc108bd4fc2d983bcabb50506d09e2a17 Author: Pan Li Date: Sat May 3 11:27:50 2025 +0800 RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 1 Add asm dump check and for vec_dup

[gcc r16-408] RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 0

https://gcc.gnu.org/g:1276430a48e4f6bb592d9e3f8c92e62341f09446 commit r16-408-g1276430a48e4f6bb592d9e3f8c92e62341f09446 Author: Pan Li Date: Sat May 3 10:40:20 2025 +0800 RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 0 Add asm dump check and run test fo

[gcc r16-406] RISC-V: Add gr2vr cost helper function

https://gcc.gnu.org/g:9e9eb78bf4b77a049be00fb9ab0047170f19c9ea commit r16-406-g9e9eb78bf4b77a049be00fb9ab0047170f19c9ea Author: Pan Li Date: Tue May 6 16:42:16 2025 +0800 RISC-V: Add gr2vr cost helper function After we introduced the --param=gpr2vr-cost option to set the cost

[gcc r16-405] RISC-V: Add new option --param=gpr2vr-cost= for rvv insn

https://gcc.gnu.org/g:17c1602d5e7b237357b94808399a68ab77d42640 commit r16-405-g17c1602d5e7b237357b94808399a68ab77d42640 Author: Pan Li Date: Tue May 6 16:26:06 2025 +0800 RISC-V: Add new option --param=gpr2vr-cost= for rvv insn During investigate the combine from vec_dup and vop.v

[gcc r16-410] RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 15

https://gcc.gnu.org/g:b3a32804bebb9520b327b7cbf3e8f8b4730f9bd6 commit r16-410-gb3a32804bebb9520b327b7cbf3e8f8b4730f9bd6 Author: Pan Li Date: Sat May 3 11:37:09 2025 +0800 RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 15 Add asm dump check and for vec_du

[gcc r16-407] RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR cost

https://gcc.gnu.org/g:2b5baada614af7a4d0ee49aa962c7e1f7be3 commit r16-407-g2b5baada614af7a4d0ee49aa962c7e1f7be3 Author: Pan Li Date: Thu May 1 21:23:54 2025 +0800 RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR cost This patch would like to combine the vec_dupl

[gcc r16-371] RISC-V: Remove unnecessary frm restore volatile define_insn

https://gcc.gnu.org/g:e5a4663bc6367920a1cce6babb367424790d9bc8 commit r16-371-ge5a4663bc6367920a1cce6babb367424790d9bc8 Author: Pan Li Date: Sun May 4 09:26:02 2025 +0800 RISC-V: Remove unnecessary frm restore volatile define_insn After we add the frm register to the global_regs,

[gcc r16-168] RISC-V: Extract vector stepped for expand_const_vector [NFC]

https://gcc.gnu.org/g:ab22b8c630769330b4f37eb64d2bc285344a647a commit r16-168-gab22b8c630769330b4f37eb64d2bc285344a647a Author: Pan Li Date: Thu Apr 17 10:27:17 2025 +0800 RISC-V: Extract vector stepped for expand_const_vector [NFC] Consider the expand_const_vector is quit long (a

[gcc r16-167] RISC-V: Extract vector duplicate for expand_const_vector [NFC]

https://gcc.gnu.org/g:cf0283a8ed035e382a3870a8dce554acf7dfc82e commit r16-167-gcf0283a8ed035e382a3870a8dce554acf7dfc82e Author: Pan Li Date: Wed Apr 16 15:47:21 2025 +0800 RISC-V: Extract vector duplicate for expand_const_vector [NFC] Consider the expand_const_vector is quit long

[gcc r16-166] RISC-V: Extract vec_series for expand_const_vector [NFC]

https://gcc.gnu.org/g:cf366b62f48fc5c06b76a9a78320888a9591031b commit r16-166-gcf366b62f48fc5c06b76a9a78320888a9591031b Author: Pan Li Date: Wed Apr 16 14:43:23 2025 +0800 RISC-V: Extract vec_series for expand_const_vector [NFC] Consider the expand_const_vector is quit long (about

[gcc r16-165] RISC-V: Extract vec_duplicate for expand_const_vector [NFC]

https://gcc.gnu.org/g:e6e42a709f3cd87e7a5efca72267cab57e0385cb commit r16-165-ge6e42a709f3cd87e7a5efca72267cab57e0385cb Author: Pan Li Date: Wed Apr 16 11:16:21 2025 +0800 RISC-V: Extract vec_duplicate for expand_const_vector [NFC] Consider the expand_const_vector is quit long (ab

[gcc r15-9332] Revert "RISC-V: Refine the testcases for cond_widen_complicate-3"

https://gcc.gnu.org/g:24d1832e0d6edce4f6f717135fcec65d6939e199 commit r15-9332-g24d1832e0d6edce4f6f717135fcec65d6939e199 Author: Pan Li Date: Wed Apr 9 19:08:21 2025 +0800 Revert "RISC-V: Refine the testcases for cond_widen_complicate-3" This reverts commit f70f4b60debce4a22372578

[gcc r15-8066] RISC-V: Refine the testcases for cond_widen_complicate-3

https://gcc.gnu.org/g:f70f4b60debce4a223725781d1973c05d8d1dfa9 commit r15-8066-gf70f4b60debce4a223725781d1973c05d8d1dfa9 Author: Pan Li Date: Wed Mar 12 11:26:52 2025 +0800 RISC-V: Refine the testcases for cond_widen_complicate-3 Rearrange the test cases of cond_widen_complicate-3

[gcc r15-7848] RISC-V: Tweak asm check for test case multiple_rgroup_zbb.c

https://gcc.gnu.org/g:0aa9b079aec260b120b7c9fdba8c21066425c73d commit r15-7848-g0aa9b079aec260b120b7c9fdba8c21066425c73d Author: Pan Li Date: Thu Mar 6 09:24:18 2025 +0800 RISC-V: Tweak asm check for test case multiple_rgroup_zbb.c The changes to vsetvl pass since 14 result in the

[gcc r15-7801] RISC-V: Fix the test case bug-3.c failure

https://gcc.gnu.org/g:bfb9276f344cbc6794379d61d0279dfc3a7441b3 commit r15-7801-gbfb9276f344cbc6794379d61d0279dfc3a7441b3 Author: Pan Li Date: Mon Mar 3 14:51:21 2025 +0800 RISC-V: Fix the test case bug-3.c failure The bug-3.c would like to check the slli a[0-9]+, a[0-9]+, 33 for t

[gcc r15-7743] RISC-V: Fix bug for expand_const_vector interleave [PR118931]

https://gcc.gnu.org/g:e7287cbbb208b676991096dd9081ff8a61c49781 commit r15-7743-ge7287cbbb208b676991096dd9081ff8a61c49781 Author: Pan Li Date: Sat Feb 22 19:34:52 2025 +0800 RISC-V: Fix bug for expand_const_vector interleave [PR118931] This patch would like to fix one bug when expa

[gcc r15-7625] Vect: Fix ICE when vect_verify_loop_lens acts on relevant mode [PR116351]

https://gcc.gnu.org/g:25256ec1df10f2eb183e1c1ab0c890e9fdd94384 commit r15-7625-g25256ec1df10f2eb183e1c1ab0c890e9fdd94384 Author: Pan Li Date: Wed Feb 19 09:37:51 2025 +0800 Vect: Fix ICE when vect_verify_loop_lens acts on relevant mode [PR116351] This patch would like to fix the I

[gcc r15-7600] RISC-V: Fix ICE for target attributes has different xlen size

https://gcc.gnu.org/g:17b95cfc310c0b3ef191cd47ceb3b4ee1205e8bf commit r15-7600-g17b95cfc310c0b3ef191cd47ceb3b4ee1205e8bf Author: Pan Li Date: Sat Feb 15 14:33:35 2025 +0800 RISC-V: Fix ICE for target attributes has different xlen size This patch would like to avoid the ICE when th

[gcc r15-7421] RISC-V: Make VXRM as global register [PR118103]

https://gcc.gnu.org/g:1c8e6734d2dd3a6236d94c6e4e0c6780f35ede9f commit r15-7421-g1c8e6734d2dd3a6236d94c6e4e0c6780f35ede9f Author: Pan Li Date: Fri Feb 7 14:21:35 2025 +0800 RISC-V: Make VXRM as global register [PR118103] Inspired by PR118103, the VXRM register should be treated alm

[gcc r15-7267] RISC-V: Fix incorrect code gen for scalar signed SAT_SUB [PR117688]

https://gcc.gnu.org/g:bfb57d62c743235284f9b31a88c6ceed9971d27a commit r15-7267-gbfb57d62c743235284f9b31a88c6ceed9971d27a Author: Pan Li Date: Thu Jan 23 12:14:43 2025 +0800 RISC-V: Fix incorrect code gen for scalar signed SAT_SUB [PR117688] This patch would like to fix the wroing

[gcc r15-7268] RISC-V: Fix incorrect code gen for scalar signed SAT_TRUNC [PR117688]

https://gcc.gnu.org/g:5a48079c15fda4863b02eb253e473c57a5105528 commit r15-7268-g5a48079c15fda4863b02eb253e473c57a5105528 Author: Pan Li Date: Thu Jan 23 14:28:39 2025 +0800 RISC-V: Fix incorrect code gen for scalar signed SAT_TRUNC [PR117688] This patch would like to fix the wroin

[gcc r15-7265] RISC-V: Refactor SAT_* operand rtx extend to reg help func [NFC]

https://gcc.gnu.org/g:7ab7829aef6b02d4022650566b2806af986be0cb commit r15-7265-g7ab7829aef6b02d4022650566b2806af986be0cb Author: Pan Li Date: Mon Jan 27 11:01:08 2025 +0800 RISC-V: Refactor SAT_* operand rtx extend to reg help func [NFC] This patch would like to refactor the helpe

[gcc r15-7266] RISC-V: Fix incorrect code gen for scalar signed SAT_ADD [PR117688]

https://gcc.gnu.org/g:81aa9488321dea5ed1d55d0dfb1a72f362a1a24f commit r15-7266-g81aa9488321dea5ed1d55d0dfb1a72f362a1a24f Author: Pan Li Date: Thu Jan 23 12:08:17 2025 +0800 RISC-V: Fix incorrect code gen for scalar signed SAT_ADD [PR117688] This patch would like to fix the wroing

[gcc r15-7215] RISC-V: Make FRM as global register [PR118103]

https://gcc.gnu.org/g:55d288d4ff5360c572f2a017ba9385840ac5134e commit r15-7215-g55d288d4ff5360c572f2a017ba9385840ac5134e Author: Pan Li Date: Sat Jan 25 15:45:10 2025 +0800 RISC-V: Make FRM as global register [PR118103] After we enabled the labe-combine pass after the mode-switchi

[gcc r15-6677] Match: Update the comments for indicating SAT_* pattern

https://gcc.gnu.org/g:4435e82708872f705c47eeb63bbcdfc54b0449fc commit r15-6677-g4435e82708872f705c47eeb63bbcdfc54b0449fc Author: Pan Li Date: Thu Dec 12 10:56:35 2024 +0800 Match: Update the comments for indicating SAT_* pattern Given the SAT_* patterns are grouped for each alu an

[gcc r15-6676] Match: Refactor the signed SAT_* match for saturated value [NFC]

https://gcc.gnu.org/g:cfe45ab382488313d8635ccaac970a11891a2c8c commit r15-6676-gcfe45ab382488313d8635ccaac970a11891a2c8c Author: Pan Li Date: Thu Dec 12 10:48:08 2024 +0800 Match: Refactor the signed SAT_* match for saturated value [NFC] This patch would like to refactor the all s

[gcc r15-6675] Match: Refactor the signed SAT_TRUNC match patterns [NFC]

https://gcc.gnu.org/g:d20e9b7b5a4dd99f0486d2b0a946208a9563e196 commit r15-6675-gd20e9b7b5a4dd99f0486d2b0a946208a9563e196 Author: Pan Li Date: Wed Dec 11 19:37:06 2024 +0800 Match: Refactor the signed SAT_TRUNC match patterns [NFC] This patch would like to refactor the all signed S

[gcc r15-6674] Match: Refactor the signed SAT_SUB match patterns [NFC]

https://gcc.gnu.org/g:5080dbb807063061dbbe0a497d04629575f8c2af commit r15-6674-g5080dbb807063061dbbe0a497d04629575f8c2af Author: Pan Li Date: Wed Dec 11 19:09:08 2024 +0800 Match: Refactor the signed SAT_SUB match patterns [NFC] This patch would like to refactor the all signed SAT

[gcc r15-6411] RISC-V: Fix the the operand alignment for strided load/store pattern [NFC]

https://gcc.gnu.org/g:cf59bf844037ae952f5058d0fd49e1f4f0cf907e commit r15-6411-gcf59bf844037ae952f5058d0fd49e1f4f0cf907e Author: Pan Li Date: Fri Dec 20 14:44:10 2024 +0800 RISC-V: Fix the the operand alignment for strided load/store pattern [NFC] Just notice the unalignment opera

[gcc r15-6406] Match: Refactor the signed SAT_ADD match patterns [NFC]

https://gcc.gnu.org/g:59e3abcb3625fd3d6f452a27671c8806c7a27b1b commit r15-6406-g59e3abcb3625fd3d6f452a27671c8806c7a27b1b Author: Pan Li Date: Tue Dec 10 14:27:53 2024 +0800 Match: Refactor the signed SAT_ADD match patterns [NFC] This patch would like to refactor the all signed SAT

[gcc r15-6388] RISC-V: Refine strided load/store testcase dump check to tree optimized

https://gcc.gnu.org/g:4779dd022927c41d2c261cdf5289e8bdecd0697d commit r15-6388-g4779dd022927c41d2c261cdf5289e8bdecd0697d Author: Pan Li Date: Fri Dec 20 09:11:20 2024 +0800 RISC-V: Refine strided load/store testcase dump check to tree optimized Like the sat alu related testcase, t

[gcc r15-6363] RISC-V: Adjust the strided store testcases check times on options

https://gcc.gnu.org/g:d0635492172781ac1af73e671e19a53471a30038 commit r15-6363-gd0635492172781ac1af73e671e19a53471a30038 Author: Pan Li Date: Thu Dec 19 09:03:59 2024 +0800 RISC-V: Adjust the strided store testcases check times on options The vsse* dump check times changes on opti

[gcc r15-6362] RISC-V: Make vector strided store alias all other memories

https://gcc.gnu.org/g:46194b912780452e80c1ef9867cbcff1050231a2 commit r15-6362-g46194b912780452e80c1ef9867cbcff1050231a2 Author: Pan Li Date: Thu Dec 19 08:58:20 2024 +0800 RISC-V: Make vector strided store alias all other memories Almost the same as the RVV strided load, the vect

[gcc r15-6208] RISC-V: Make vector strided load alias all other memories

https://gcc.gnu.org/g:9b4cc2710f97138805a1db6a89bc792e22f02db2 commit r15-6208-g9b4cc2710f97138805a1db6a89bc792e22f02db2 Author: Pan Li Date: Fri Dec 13 10:45:38 2024 +0800 RISC-V: Make vector strided load alias all other memories The vector strided load doesn't include the (mem:B

[gcc r15-6064] RISC-V: Refine unsigned vector SAT_ADD testcase dump check to tree optimized

https://gcc.gnu.org/g:a6aa0719aaadf0014910852a049634357e1779ff commit r15-6064-ga6aa0719aaadf0014910852a049634357e1779ff Author: Pan Li Date: Sun Dec 8 19:56:15 2024 +0800 RISC-V: Refine unsigned vector SAT_ADD testcase dump check to tree optimized The sat alu related testcase che

[gcc r15-6067] RISC-V: Refine signed vector SAT_ADD testcase dump check to tree optimized

https://gcc.gnu.org/g:1850da91610aa6df1f69f816aff6fecbb43e1fdd commit r15-6067-g1850da91610aa6df1f69f816aff6fecbb43e1fdd Author: Pan Li Date: Sun Dec 8 19:56:18 2024 +0800 RISC-V: Refine signed vector SAT_ADD testcase dump check to tree optimized The sat alu related testcase check

[gcc r15-6069] RISC-V: Refine signed vector SAT_SUB testcase dump check to tree optimized

https://gcc.gnu.org/g:6fbff06f9e39d75962b1cf5bfefb3d717ba4ace4 commit r15-6069-g6fbff06f9e39d75962b1cf5bfefb3d717ba4ace4 Author: Pan Li Date: Sun Dec 8 19:56:19 2024 +0800 RISC-V: Refine signed vector SAT_SUB testcase dump check to tree optimized The sat alu related testcase check

[gcc r15-6066] RISC-V: Refine unsigned vector SAT_TRUNC testcase dump check to tree optimized

https://gcc.gnu.org/g:b5c99314b80ba132ffd70541fde6bc5c215f324c commit r15-6066-gb5c99314b80ba132ffd70541fde6bc5c215f324c Author: Pan Li Date: Sun Dec 8 19:56:17 2024 +0800 RISC-V: Refine unsigned vector SAT_TRUNC testcase dump check to tree optimized The sat alu related testcase

[gcc r15-6068] RISC-V: Refine signed vector SAT_TRUNC testcase dump check to tree optimized

https://gcc.gnu.org/g:75d518100ed7554b0d4ae7df72e25110f3a4e180 commit r15-6068-g75d518100ed7554b0d4ae7df72e25110f3a4e180 Author: Pan Li Date: Sun Dec 8 19:56:20 2024 +0800 RISC-V: Refine signed vector SAT_TRUNC testcase dump check to tree optimized The sat alu related testcase che

[gcc r15-6065] RISC-V: Refine unsigned vector SAT_SUB testcase dump check to tree optimized

https://gcc.gnu.org/g:aa8c20e32e54f2aa15bd138c0a22cfb3f1278852 commit r15-6065-gaa8c20e32e54f2aa15bd138c0a22cfb3f1278852 Author: Pan Li Date: Sun Dec 8 19:56:16 2024 +0800 RISC-V: Refine unsigned vector SAT_SUB testcase dump check to tree optimized The sat alu related testcase che

[gcc r15-6033] RISC-V: Refine unsigned SAT_SUB testcase dump check to tree optimized

https://gcc.gnu.org/g:4a783eb38a0f12b3d6f905e5085e51686f4f482b commit r15-6033-g4a783eb38a0f12b3d6f905e5085e51686f4f482b Author: Pan Li Date: Sun Dec 8 09:32:26 2024 +0800 RISC-V: Refine unsigned SAT_SUB testcase dump check to tree optimized The sat alu related testcase check the

[gcc r15-6037] RISC-V: Refine signed SAT_TRUNC testcase dump check to tree optimized

https://gcc.gnu.org/g:dbd6e147aaed246251351a4d48586fa965b6ee71 commit r15-6037-gdbd6e147aaed246251351a4d48586fa965b6ee71 Author: Pan Li Date: Sun Dec 8 09:32:30 2024 +0800 RISC-V: Refine signed SAT_TRUNC testcase dump check to tree optimized The sat alu related testcase check the

[gcc r15-6036] RISC-V: Refine signed SAT_SUB testcase dump check to tree optimized

https://gcc.gnu.org/g:da448408682aeb0f02c39ce36b1312eee6a2ca5d commit r15-6036-gda448408682aeb0f02c39ce36b1312eee6a2ca5d Author: Pan Li Date: Sun Dec 8 09:32:29 2024 +0800 RISC-V: Refine signed SAT_SUB testcase dump check to tree optimized The sat alu related testcase check the rt

[gcc r15-6035] RISC-V: Refine signed SAT_ADD testcase dump check to tree optimized

https://gcc.gnu.org/g:e3c378aabb4120cd78f9a2b4cfddca2a1f71b7f5 commit r15-6035-ge3c378aabb4120cd78f9a2b4cfddca2a1f71b7f5 Author: Pan Li Date: Sun Dec 8 09:32:28 2024 +0800 RISC-V: Refine signed SAT_ADD testcase dump check to tree optimized The sat alu related testcase check the rt

[gcc r15-6034] RISC-V: Refine unsigned SAT_TRUNC testcase dump check to tree optimized

https://gcc.gnu.org/g:31778b48dd5fe6ae2bb089293a9a256918008d96 commit r15-6034-g31778b48dd5fe6ae2bb089293a9a256918008d96 Author: Pan Li Date: Sun Dec 8 09:32:27 2024 +0800 RISC-V: Refine unsigned SAT_TRUNC testcase dump check to tree optimized The sat alu related testcase check th

[gcc r15-6032] RISC-V: Refine unsigned SAT_ADD testcase dump check to tree optimized

https://gcc.gnu.org/g:0404fd56aeae56ba9bbe50d3fe8e2911d4079f7b commit r15-6032-g0404fd56aeae56ba9bbe50d3fe8e2911d4079f7b Author: Pan Li Date: Sun Dec 8 09:32:25 2024 +0800 RISC-V: Refine unsigned SAT_ADD testcase dump check to tree optimized The sat alu related testcase check the

[gcc r15-6020] RISC-V: Fix incorrect optimization options passing to partial

https://gcc.gnu.org/g:cd4daddf6c3f977469c51dac518000b16668364f commit r15-6020-gcd4daddf6c3f977469c51dac518000b16668364f Author: Pan Li Date: Mon Dec 9 14:07:22 2024 +0800 RISC-V: Fix incorrect optimization options passing to partial Like the strided load/store, the testcases of v

[gcc r15-6019] RISC-V: Refactor the testcases for rvv binop and cmp

https://gcc.gnu.org/g:6205144d6b566f32a58c4fa4f5e7e2343ad07c62 commit r15-6019-g6205144d6b566f32a58c4fa4f5e7e2343ad07c62 Author: Pan Li Date: Fri Dec 6 12:22:53 2024 +0800 RISC-V: Refactor the testcases for rvv binop and cmp This patch would like to refactor the testcases for rvv

[gcc r15-6018] RISC-V: Fix incorrect optimization options passing to binop and cmp

https://gcc.gnu.org/g:f873c602d5ea5212e504426a56556a2e1415a40f commit r15-6018-gf873c602d5ea5212e504426a56556a2e1415a40f Author: Pan Li Date: Fri Dec 6 12:22:52 2024 +0800 RISC-V: Fix incorrect optimization options passing to binop and cmp Like the strided load/store, the testcase

[gcc r15-5953] RISC-V: Fix incorrect optimization options passing to convert and unop

https://gcc.gnu.org/g:b7baa22e47421d0a81202a333f43d88b5bbb39f5 commit r15-5953-gb7baa22e47421d0a81202a333f43d88b5bbb39f5 Author: Pan Li Date: Wed Dec 4 10:08:11 2024 +0800 RISC-V: Fix incorrect optimization options passing to convert and unop Like the strided load/store, the testc

[gcc r15-5954] RISC-V: Refactor the testcases for bswap16-0

https://gcc.gnu.org/g:3ac3093756cd00f50e63e8dcde4d278606722105 commit r15-5954-g3ac3093756cd00f50e63e8dcde4d278606722105 Author: Pan Li Date: Wed Dec 4 10:08:12 2024 +0800 RISC-V: Refactor the testcases for bswap16-0 This patch would like to refactor the testcases of bswap16-0

[gcc r15-5944] Match: Refactor the unsigned SAT_TRUNC match patterns [NFC]

https://gcc.gnu.org/g:9163d16e4f56ced25839ff246c56e166ae62e962 commit r15-5944-g9163d16e4f56ced25839ff246c56e166ae62e962 Author: Pan Li Date: Thu Dec 5 09:19:39 2024 +0800 Match: Refactor the unsigned SAT_TRUNC match patterns [NFC] This patch would like to refactor the all unsigne

[gcc r15-5917] RISC-V: Add assert for insn operand out of range access [PR117878][NFC]

https://gcc.gnu.org/g:fb64a7b0e1d7488e6e3ae96af8d97fd2226b6d21 commit r15-5917-gfb64a7b0e1d7488e6e3ae96af8d97fd2226b6d21 Author: Pan Li Date: Wed Dec 4 13:53:52 2024 +0800 RISC-V: Add assert for insn operand out of range access [PR117878][NFC] According to the the initial analysis

[gcc r15-5879] Match: Refactor the unsigned SAT_SUB match patterns [NFC]

https://gcc.gnu.org/g:f2d91164a5c54f4c246a7cc73f23aa79bc5e commit r15-5879-gf2d91164a5c54f4c246a7cc73f23aa79bc5e Author: Pan Li Date: Fri Nov 29 20:33:19 2024 +0800 Match: Refactor the unsigned SAT_SUB match patterns [NFC] This patch would like to refactor the all unsigned

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