https://gcc.gnu.org/g:d0635492172781ac1af73e671e19a53471a30038
commit r15-6363-gd0635492172781ac1af73e671e19a53471a30038
Author: Pan Li <pan2...@intel.com>
Date: Thu Dec 19 09:03:59 2024 +0800
RISC-V: Adjust the strided store testcases check times on options
The vsse* dump check times changes on options (O2, O3) after we add
(mem:BLK (scratch)) to the define_insn of strided load.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c: Adjust
the vsse check times based on optimization option.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c: Ditto.
Signed-off-by: Pan Li <pan2...@intel.com>
Diff:
---
.../gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c | 3 ++-
.../gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c | 3 ++-
.../gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c | 3 ++-
3 files changed, 6 insertions(+), 3 deletions(-)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c
index e4f6a40873be..2be8854a0b64 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c
@@ -10,4 +10,5 @@ DEF_STRIDED_LD_ST_FORM_1(double)
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" {
target { any-opts "-O2" } } } } */
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" {
target { any-opts "-O2" } } } } */
/* { dg-final { scan-assembler-times {vlse64.v} 1 } } */
-/* { dg-final { scan-assembler-times {vsse64.v} 1 } } */
+/* { dg-final { scan-assembler-times {vsse64.v} 1 { target { any-opts "-O2" }
} } } */
+/* { dg-final { scan-assembler-times {vsse64.v} 2 { target { any-opts "-O3" }
} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c
index afbce2263681..13003e2ccdcb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c
@@ -10,4 +10,5 @@ DEF_STRIDED_LD_ST_FORM_1(int64_t)
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" {
target { any-opts "-O2" } } } } */
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" {
target { any-opts "-O2" } } } } */
/* { dg-final { scan-assembler-times {vlse64.v} 1 } } */
-/* { dg-final { scan-assembler-times {vsse64.v} 1 } } */
+/* { dg-final { scan-assembler-times {vsse64.v} 1 { target { any-opts "-O2" }
} } } */
+/* { dg-final { scan-assembler-times {vsse64.v} 2 { target { any-opts "-O3" }
} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c
index a66eb5bcfd41..5df2caa793b4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c
@@ -10,4 +10,5 @@ DEF_STRIDED_LD_ST_FORM_1(uint64_t)
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_LOAD " 2 "expand" {
target { any-opts "-O2" } } } } */
/* { dg-final { scan-rtl-dump-times ".MASK_LEN_STRIDED_STORE " 2 "expand" {
target { any-opts "-O2" } } } } */
/* { dg-final { scan-assembler-times {vlse64.v} 1 } } */
-/* { dg-final { scan-assembler-times {vsse64.v} 1 } } */
+/* { dg-final { scan-assembler-times {vsse64.v} 1 { target { any-opts "-O2" }
} } } */
+/* { dg-final { scan-assembler-times {vsse64.v} 2 { target { any-opts "-O3" }
} } } */
