https://gcc.gnu.org/g:17b95cfc310c0b3ef191cd47ceb3b4ee1205e8bf
commit r15-7600-g17b95cfc310c0b3ef191cd47ceb3b4ee1205e8bf
Author: Pan Li <pan2...@intel.com>
Date: Sat Feb 15 14:33:35 2025 +0800
RISC-V: Fix ICE for target attributes has different xlen size
This patch would like to avoid the ICE when the target attribute
specific the xlen different to the cmd. Aka compile with rv64gc
but target attribute with rv32gcv_zbb. For example as blow:
1 │ long foo (long a, long b)
2 │ __attribute__((target("arch=rv32gcv_zbb")));
3 │
4 │ long foo (long a, long b)
5 │ {
6 │ return a + (b * 2);
7 │ }
when compile with rv64gc -O3, it will have ICE similar as below
during RTL pass: fwprop1
test.c: In function ‘foo’:
test.c:10:1: internal compiler error: in add_use, at
rtl-ssa/accesses.cc:1234
10 | }
| ^
0x44d6b9d internal_error(char const*, ...)
/home/pli/gcc/111/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/diagnostic-global-context.cc:517
0x44a26a6 fancy_abort(char const*, int, char const*)
/home/pli/gcc/111/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/diagnostic.cc:1722
0x408fac9 rtl_ssa::function_info::add_use(rtl_ssa::use_info*)
/home/pli/gcc/111/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/rtl-ssa/accesses.cc:1234
0x40a5eea
rtl_ssa::function_info::create_reg_use(rtl_ssa::function_info::build_info&,
rtl_ssa::insn_info*, rtl_ssa::resource_info)
/home/pli/gcc/111/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/rtl-ssa/insns.cc:496
0x4456738
rtl_ssa::function_info::add_artificial_accesses(rtl_ssa::function_info::build_info&,
df_ref_flags)
/home/pli/gcc/111/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/rtl-ssa/blocks.cc:900
0x4457297
rtl_ssa::function_info::start_block(rtl_ssa::function_info::build_info&,
rtl_ssa::bb_info*)
/home/pli/gcc/111/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/rtl-ssa/blocks.cc:1082
0x4453627
rtl_ssa::function_info::bb_walker::before_dom_children(basic_block_def*)
/home/pli/gcc/111/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/rtl-ssa/blocks.cc:118
0x3e9f3fb dom_walker::walk(basic_block_def*)
/home/pli/gcc/111/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/domwalk.cc:311
0x445806f rtl_ssa::function_info::process_all_blocks()
/home/pli/gcc/111/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/rtl-ssa/blocks.cc:1298
0x40a22d3 rtl_ssa::function_info::function_info(function*)
/home/pli/gcc/111/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/rtl-ssa/functions.cc:51
0x3ec3f80 fwprop_init
/home/pli/gcc/111/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/fwprop.cc:893
0x3ec420d fwprop
/home/pli/gcc/111/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/fwprop.cc:963
0x3ec43ad execute
Consider stage 4, we just report error for the above scenario when
detect the cmd xlen is different to the target attribute during the
target hook TARGET_OPTION_VALID_ATTRIBUTE_P implementation.
PR target/118540
gcc/ChangeLog:
* config/riscv/riscv-target-attr.cc
(riscv_target_attr_parser::parse_arch):
Report error when cmd xlen is different with target attribute.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr118540-1.c: New test.
* gcc.target/riscv/rvv/base/pr118540-2.c: New test.
Signed-off-by: Pan Li <pan2...@intel.com>
Diff:
---
gcc/config/riscv/riscv-target-attr.cc | 14 ++++++++++++++
gcc/testsuite/gcc.target/riscv/rvv/base/pr118540-1.c | 12 ++++++++++++
gcc/testsuite/gcc.target/riscv/rvv/base/pr118540-2.c | 12 ++++++++++++
3 files changed, 38 insertions(+)
diff --git a/gcc/config/riscv/riscv-target-attr.cc
b/gcc/config/riscv/riscv-target-attr.cc
index 615f1b9c6ce1..1d968655f95d 100644
--- a/gcc/config/riscv/riscv-target-attr.cc
+++ b/gcc/config/riscv/riscv-target-attr.cc
@@ -100,6 +100,20 @@ riscv_target_attr_parser::parse_arch (const char *str)
/* Check if it's setting full arch string. */
if (strncmp ("rv", str, strlen ("rv")) == 0)
{
+ if (TARGET_64BIT && strncmp ("32", str + 2, strlen ("32")) == 0)
+ {
+ error_at (m_loc, "unexpected arch for %<target()%> attribute: "
+ "must start with rv64 but found %qs", str);
+ goto fail;
+ }
+
+ if (!TARGET_64BIT && strncmp ("64", str + 2, strlen ("64")) == 0)
+ {
+ error_at (m_loc, "unexpected arch for %<target()%> attribute: "
+ "must start with rv32 but found %qs", str);
+ goto fail;
+ }
+
m_subset_list = riscv_subset_list::parse (str, m_loc);
if (m_subset_list == nullptr)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr118540-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr118540-1.c
new file mode 100644
index 000000000000..0b52a7b2ab55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr118540-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { rv64 } } } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" { target { rv64 } } } */
+
+long foo (long a, long b)
+__attribute__((target("arch=rv32gcv_zbb")));
+
+long foo (long a, long b)
+{
+ return a + (b * 2);
+}
+
+/* { dg-error "must start with rv64 but found 'rv32gcv_zbb'" "" { target {
rv64 } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr118540-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr118540-2.c
new file mode 100644
index 000000000000..d7c4e00cf4d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr118540-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { rv32 } } } */
+/* { dg-options "-march=rv32gc -mabi=ilp32d -O3" { target { rv32 } } } */
+
+long foo (long a, long b)
+__attribute__((target("arch=rv64gcv_zbb")));
+
+long foo (long a, long b)
+{
+ return a + (b * 2);
+}
+
+/* { dg-error "must start with rv32 but found 'rv64gcv_zbb'" "" { target {
rv32 } } 0 } */
