https://gcc.gnu.org/g:aa8c20e32e54f2aa15bd138c0a22cfb3f1278852
commit r15-6065-gaa8c20e32e54f2aa15bd138c0a22cfb3f1278852
Author: Pan Li <pan2...@intel.com>
Date: Sun Dec 8 19:56:16 2024 +0800
RISC-V: Refine unsigned vector SAT_SUB testcase dump check to tree optimized
The sat alu related testcase check the rtl dump for the standard name
like .SAT_SUB exist or not. But the rtl pass expand is somehow
impressionable by the middle-end change or debug information. Like
below new appearance recently.
Replacing Expressions
_5 replace with --> _5 = .SAT_SUB (x_3(D), y_4(D)); [tail call]
After that we need to adjust the dump check time and again. This
patch would like to switch to tree optimized pass for the standard
name check, which is more stable up to a point.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u16.c: Take
tree-optimized pass for standard name check, and adjust the times.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c: Ditto.
Signed-off-by: Pan Li <pan2...@intel.com>
Diff:
---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u64.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u64.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u64.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u64.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u64.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u64.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u64.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u64.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u64.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u64.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u64.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c | 8 ++++----
48 files changed, 100 insertions(+), 100 deletions(-)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u16.c
index 0cb782ab1121..6f6640b9289b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u16.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_1(uint16_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u32.c
index 375a06fa57fb..32513709129f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u32.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_1(uint32_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u64.c
index 4a011a66b06d..ced2ac84ba72 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u64.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_1(uint64_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { no-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target {
no-opts
"-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m1"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target {
any-opts
"-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m1"
} } } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u8.c
index 8de33735fb5c..ea6394f66168 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u8.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_1(uint8_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u16.c
index 3a6e3a5f00b2..ee703634a4ea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u16.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_10(uint16_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u32.c
index f7618741cb41..8704096ee2a0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u32.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_10(uint32_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u64.c
index e510a536c9c9..ba35ca1dc17d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u64.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_10(uint64_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u8.c
index 12b1267cf5e5..0a0334b6ed30 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u8.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_10(uint8_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u16.c
index 3d456bfd4a9f..b7297f45354e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u16.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_2(uint16_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u32.c
index 4bad003868cb..c394f512437b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u32.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_2(uint32_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u64.c
index cfe7eef5a0b4..f9baa2ebf98c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u64.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_2(uint64_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { no-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target {
no-opts
"-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m1"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target {
any-opts
"-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m1"
} } } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u8.c
index 5be4e44b4596..3c20829525bb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u8.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_2(uint8_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u16.c
index 10b96921fc5e..125286c1332e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u16.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_3(uint16_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u32.c
index 8714ca4daff1..07f89d441812 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u32.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_3(uint32_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u64.c
index a0e3caaf7cf8..15c684d82b9a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u64.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_3(uint64_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u8.c
index b36e2f23e990..eff19c640b85 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u8.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_3(uint8_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u16.c
index 9ae89f9a4d51..df6760548656 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u16.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_4(uint16_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u32.c
index 870979013fa0..43e53188a19c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u32.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_4(uint32_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u64.c
index b658fe6053eb..dd951fbceb1b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u64.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_4(uint64_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u8.c
index 602616b5e7db..8421ef6d34d6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u8.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_4(uint8_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u16.c
index d65f5b7c2202..35a12b8da330 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u16.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_5(uint16_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u32.c
index fa65f9607a72..0348b043fb81 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u32.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_5(uint32_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u64.c
index c129df955d83..184bd10cc66b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u64.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_5(uint64_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u8.c
index 5dc1eed26a56..497850bf0e89 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u8.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_5(uint8_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u16.c
index b4cfdd35eaa6..fa8064ab6171 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u16.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_6(uint16_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u32.c
index 7c45b782dc32..d6156929ca87 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u32.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_6(uint32_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u64.c
index de7adf076aba..4c634803e9f9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u64.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_6(uint64_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u8.c
index ea20185d0978..ec808abba4f8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u8.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_6(uint8_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u16.c
index b4b78f8a31b6..9e2921f7281d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u16.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_7(uint16_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u32.c
index 76f454fc727b..3ee56262f2e8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u32.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_7(uint32_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u64.c
index 484ac4a1683a..a775aed0bff5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u64.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_7(uint64_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u8.c
index 1e9ede2f7a4c..0107c3c70409 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u8.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_7(uint8_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u16.c
index 3b66539a1540..2a6504bf36ab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u16.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_8(uint16_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u32.c
index 19daa9b42f1b..086f1e2f98e4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u32.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_8(uint32_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u64.c
index 2123ff6866a5..0f8121e0080e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u64.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_8(uint64_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u8.c
index 70c515338055..1dd7415c5d68 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u8.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_8(uint8_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u16.c
index 461049d2e9b5..aefd717d3b5a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u16.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_9(uint16_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u32.c
index c7295ad6a326..517664293632 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u32.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_9(uint32_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u64.c
index b325e21ac07a..b5f29125c1db 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u64.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_9(uint64_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u8.c
index dbd2421a927a..b16f3c020634 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u8.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_FMT_9(uint8_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u16.c
index 72a00c28f8ad..edd05d1b27f3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u16.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_IMM_FMT_1(uint16_t, 70)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u32.c
index d415c3ed9516..1102a540d46f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u32.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_IMM_FMT_1(uint32_t, 5)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u64.c
index 79b5e5259b6e..3d3eed531ea4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u64.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_IMM_FMT_1(uint64_t, 9)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u8.c
index 999574741c78..b96391231ae2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u8.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_IMM_FMT_1(uint8_t, 10)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c
index bd5897aabc51..2d00b9bbb82e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c
@@ -1,10 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint16_t, uint32_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */
/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c
index 37440ee66a9d..287adf0480cd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c
@@ -1,10 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint32_t, uint64_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */
/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c
index 06aa7eb173d6..946480ce8565 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c
@@ -1,10 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint8_t, uint16_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */
/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */
/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c
index 51f1ee505f61..5988df689d01 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c
@@ -1,20 +1,20 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_SUB_ZIP_WRAP(uint16_t, uint32_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 6 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 6 "optimized" { target {
any-opts
"-mrvv-vector-bits=scalable"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target {
any-opts
"-mrvv-vector-bits=zvl"
} } } } */
/* { dg-final { scan-assembler-times {vssubu\.vv} 3 { target { any-ops
"-mrvv-vector-bits=scalable"
} } } } */
-/* { dg-final { scan-assembler-times {vssubu\.vv} 2 { target { any-ops
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 { target { any-ops
"-mrvv-vector-bits=zvl"
} } } } */
/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */
