https://gcc.gnu.org/g:75d518100ed7554b0d4ae7df72e25110f3a4e180
commit r15-6068-g75d518100ed7554b0d4ae7df72e25110f3a4e180
Author: Pan Li <pan2...@intel.com>
Date: Sun Dec 8 19:56:20 2024 +0800
RISC-V: Refine signed vector SAT_TRUNC testcase dump check to tree optimized
The sat alu related testcase check the rtl dump for the standard name
like .SAT_TRUNC exist or not. But the rtl pass expand is somehow
impressionable by the middle-end change or debug information. Like
below new appearance recently.
Replacing Expressions
_5 replace with --> _5 = .SAT_TRUNC (x_3(D), y_4(D)); [tail call]
After that we need to adjust the dump check time and again. This
patch would like to switch to tree optimized pass for the standard
name check, which is more stable up to a point.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c:
Take
tree-optimized pass for standard name check, and adjust the times.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c:
Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c:
Ditto.
Signed-off-by: Pan Li <pan2...@intel.com>
Diff:
---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c | 6 +++---
48 files changed, 141 insertions(+), 141 deletions(-)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c
index 51a3b1d065e3..53f84b49dff0 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_1(int8_t, int16_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c
index 95a11e96a66d..aea91799712e 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_1(int16_t, int32_t, INT16_MIN, INT16_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c
index 1f40a2e8fc7b..2b464e14e269 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_1(int8_t, int32_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c
index 4a5bdfc1fd4a..7c52fe00bd75 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_1(int16_t, int64_t, INT16_MIN, INT16_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c
index 034bff3b34f3..7ab441b30507 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_1(int32_t, int64_t, INT32_MIN, INT32_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c
index f437c54508c0..5dd207852ab1 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_1(int8_t, int64_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c
index 1a0e2d58dbac..a6b755fc0592 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_2(int8_t, int16_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c
index 88bc1f77cc54..0eaf12a46d94 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_2(int16_t, int32_t, INT16_MIN, INT16_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c
index d56dd050ab26..62476968a657 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_2(int8_t, int32_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c
index db23955415f3..87ac9a4dbec4 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_2(int16_t, int64_t, INT16_MIN, INT16_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c
index f9c30fadb48f..d198aa185699 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_2(int32_t, int64_t, INT32_MIN, INT32_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c
index a1b21ab805ed..9e1d9919d3be 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_2(int8_t, int64_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c
index 933043717608..9713893ccf89 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_3(int8_t, int16_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c
index c17b25fd68b1..cfaf32b3c607 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_3(int16_t, int32_t, INT16_MIN, INT16_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c
index 1adc420078cc..aa7c278fe80a 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_3(int8_t, int32_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c
index b215b4dbd631..60cfc282d512 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_3(int16_t, int64_t, INT16_MIN, INT16_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c
index 13e68df011ab..be6054791023 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_3(int32_t, int64_t, INT32_MIN, INT32_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c
index 7bd230393e58..22fe85ecb87d 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_3(int8_t, int64_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c
index 9b85ac5250fa..f1392d27256e 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_4(int8_t, int16_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c
index 912e2b73526a..f132ec67ae88 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_4(int16_t, int32_t, INT16_MIN, INT16_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c
index f831f79b05f9..2bdce5793c3e 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_4(int8_t, int32_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c
index f67afcd4e098..cfe150faddb6 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_4(int16_t, int64_t, INT16_MIN, INT16_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c
index d0bf273df336..a8db981e9044 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_4(int32_t, int64_t, INT32_MIN, INT32_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c
index d7ea8582184a..f9a2e103183a 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_4(int8_t, int64_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c
index c62175ecbf75..cedb8d4662d6 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_5(int8_t, int16_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c
index 0e5fe79d9630..0b72b19eb192 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_5(int16_t, int32_t, INT16_MIN, INT16_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c
index 90f1a3a2f6ce..cee4f162f882 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_5(int8_t, int32_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c
index 69f397a90a7d..6522129df2d9 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_5(int16_t, int64_t, INT16_MIN, INT16_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c
index 53a8f86f0f30..bd4d74841ff1 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_5(int32_t, int64_t, INT32_MIN, INT32_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c
index af49f56d1929..a1e8ec94bee7 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_5(int8_t, int64_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c
index f2790d8ead08..62a5b6a65a66 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_6(int8_t, int16_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c
index c68eaf7b45ff..972a69ea4040 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_6(int16_t, int32_t, INT16_MIN, INT16_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c
index 7f81ee119cf8..89f18e05f0a2 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_6(int8_t, int32_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c
index f7da85278245..40bec6bfc9bc 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_6(int16_t, int64_t, INT16_MIN, INT16_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c
index b3d3d07cc142..1b378d9a982f 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_6(int32_t, int64_t, INT32_MIN, INT32_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c
index c16337cdc682..22452992f900 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_6(int8_t, int64_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c
index 171efe722a32..be8a470b5779 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_7(int8_t, int16_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c
index 9d0e1fdd82d7..9526ca1c89c4 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_7(int16_t, int32_t, INT16_MIN, INT16_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c
index 8175a70239c5..de1c6bd5e886 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_7(int8_t, int32_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c
index 2f6a1ea60ee3..33576664602b 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_7(int16_t, int64_t, INT16_MIN, INT16_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c
index 3862e85b513a..5469621276d2 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_7(int32_t, int64_t, INT32_MIN, INT32_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c
index dcde698db485..86698a86a3ea 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_7(int8_t, int64_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c
index 4fc64a281c48..f38ebdfee290 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_8(int8_t, int16_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c
index c80621a10479..5838b7cd44ba 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_8(int16_t, int32_t, INT16_MIN, INT16_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c
index a60ff87c8a7a..f266f5452ef1 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_8(int8_t, int32_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c
index 1257dc6427e6..2f42b1eb2241 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_8(int16_t, int64_t, INT16_MIN, INT16_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c
index 9a1fe30bc51b..741f6bcab5d4 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_8(int32_t, int64_t, INT32_MIN, INT32_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c
index 7d6a8e26703d..5c7b53c9ad68 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_TRUNC_FMT_8(int8_t, int64_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target {
any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */
