https://gcc.gnu.org/g:a6aa0719aaadf0014910852a049634357e1779ff
commit r15-6064-ga6aa0719aaadf0014910852a049634357e1779ff
Author: Pan Li <pan2...@intel.com>
Date: Sun Dec 8 19:56:15 2024 +0800
RISC-V: Refine unsigned vector SAT_ADD testcase dump check to tree optimized
The sat alu related testcase check the rtl dump for the standard name
like .SAT_ADD exist or not. But the rtl pass expand is somehow
impressionable by the middle-end change or debug information. Like
below new appearance recently.
Replacing Expressions
_5 replace with --> _5 = .SAT_ADD (x_3(D), y_4(D)); [tail call]
After that we need to adjust the dump check time and again. This
patch would like to switch to tree optimized pass for the standard
name check, which is more stable up to a point.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c: Take
tree-optimized pass for standard name check, and adjust the times.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c: Ditto.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c: Ditto.
Signed-off-by: Pan Li <pan2...@intel.com>
Diff:
---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c | 4 ++--
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c | 4 ++--
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c | 4 ++--
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c | 4 ++--
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c | 4 ++--
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c | 4 ++--
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c | 4 ++--
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c | 4 ++--
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c | 4 ++--
.../riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c | 4 ++--
63 files changed, 127 insertions(+), 127 deletions(-)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c
index 88450517657b..440156b77182 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c
@@ -1,11 +1,11 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_1(uint16_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target {
no-opts
"-O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m1"
"-O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m2"
"-O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m3"
@@ -15,7 +15,7 @@ DEF_VEC_SAT_U_ADD_FMT_1(uint16_t)
"-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m3"
"-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target
any-opts
"-O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m1"
"-O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m2"
"-O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m3"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c
index c740c693c01e..f489480b3d59 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_1(uint32_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c
index 1cc577f6c8b6..0a62cbb9a357 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_1(uint64_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c
index ecbc27725c7d..70a1d3175712 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_1(uint8_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c
index 73a23fadf13b..48f3e2ef6594 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_2(uint16_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c
index b62f30133e1f..8f98b7de58aa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_2(uint32_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c
index 8bb2fbc87a29..ac0bbb025586 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_2(uint64_t)
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c
index ffc4342be9be..e90ccdec4c41 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_2(uint8_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c
index effb4d48e271..fe25add43a4e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
@@ -13,5 +13,5 @@
*/
DEF_VEC_SAT_U_ADD_FMT_3(uint16_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c
index 1b64fc18a901..3bd74ba2fbc6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_3(uint32_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c
index fdda300d6053..b24d1f1d4e20 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_3(uint64_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c
index 35e98475895a..fc8b5bb26948 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_3(uint8_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c
index aaac0f0eb286..431cc7b1f374 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_4(uint16_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c
index 6ad6904335cd..a35fbf65a439 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_4(uint32_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c
index adb27bbf56c6..5b0b80bcdc9c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_4(uint64_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c
index 4b337b3649b1..87037af382de 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_4(uint8_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c
index acfe5b558845..b27ef0fafed0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_5(uint16_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c
index aba5b0449e8d..c28edf490a55 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_5(uint32_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c
index 7d5d8cc99ebb..e337b9aceeab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_5(uint64_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c
index 592c976019a1..5280c10824c4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_5(uint8_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c
index 1bd4cf5715dd..e362d50061c2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_6(uint16_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c
index f358bf4b42af..76fa03596531 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_6(uint32_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c
index 715974ef3a7d..671e345ddc72 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_6(uint64_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c
index 055e44d64877..8271797a7f98 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_6(uint8_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c
index e5b5d7e5902e..8b7749d7902b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_7(uint16_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c
index be71df2aee7f..8a829c7ded61 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_7(uint32_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c
index 442be2109bb9..d3973e0421c3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_7(uint64_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c
index a9f9c858c7f5..df676f423b51 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_7(uint8_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c
index 7ed1d1211fe5..fd88fd23325d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_8(uint16_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c
index 6527af2d210d..ee8104b6f8f7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_8(uint32_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c
index 971795cad082..64c742e42a1c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_8(uint64_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c
index 99deffea15bc..28eb2d4429ce 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_FMT_8(uint8_t)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c
index bd549f7882d7..f9421745d68a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_1(uint16_t, 15)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c
index 75d5a67e1c85..002c1e35bcb1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_1(uint32_t, 33)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c
index 2195dce98ef3..a7cb685dee3c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_1(uint64_t, 129)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c
index f61df646c73d..ade8f4c36f51 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_1(uint8_t, 9)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c
index fa99826135cf..f3eaf33f341e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_2(uint16_t, 15)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c
index a343104a6283..8e0da58e98b7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_2(uint32_t, 33)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c
index ee8d8e675e3e..29db61945039 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_2(uint64_t, 129)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c
index b35cdbe9207b..fe936f718e08 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_2(uint8_t, 9)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c
index d8a7da79c5cd..09ef00273d59 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint16_t, 15)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c
index be4e263a956b..5c827a8b8614 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint32_t, 33u)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c
index d29807a7981f..d8cab1c3e132 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint64_t, 129ull)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c
index b190b28e3440..09441f9e5e44 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint8_t, 9u)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c
index f528b95fd2c1..c9a4ecb06187 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint16_t, 15)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c
index de6570bb32d4..0342a734265f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint32_t, 33u)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c
index f2aa70816b31..5e8ce1ff5757 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint64_t, 129ull)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c
index a3045ad0a008..5bba140acc45 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint8_t, 9u)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
/* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c
index 74793603bc2b..6bab0fe4da6d 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint8_t, 219)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c
index 38402a34aefe..c8f28625b5e6 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint8_t, 299)
-/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
+/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c
index 90b0bff92b71..f822e1ae1b27 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint8_t, 301u)
-/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
+/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c
index 2aaef2f66367..05cb6379ae0e 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint8_t, 9u)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c
index 94a8e6715bd6..e3b7ad25b866 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint16_t, 65530)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c
index 5c5dc25c72e0..78de31badea1 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint16_t, 65559)
-/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
+/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c
index 5d99e79b6237..e54b3577b8b8 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint16_t, 75559u)
-/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
+/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c
index 02f07ff0cdc7..f5a228dc3ae2 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint16_t, 9u)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c
index 8f18b82819f7..aa033b6bf3e1 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint32_t, 4294967205u)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c
index 2ddecd8e0054..3127ff167384 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint32_t, 4294967495ll)
-/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
+/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c
index 222ec989b34c..85c7bab13a30 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint32_t, 9294967495ull)
-/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
+/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c
index 2f6da167c621..04d591180138 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint32_t, 911u)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c
index 7e2df06ebf4a..00ee173df043 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint64_t, 18446744073709551615ull)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c
index 5ab4f162d846..eb7284e60a9e 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint64_t, 9223372036854775807ull)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c
index 64c112d222dc..b910ed87e4e6 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c
@@ -1,9 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
/* { dg-skip-if "" { *-*-* } { "-flto" } } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint64_t, 119u)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
