https://gcc.gnu.org/g:1850da91610aa6df1f69f816aff6fecbb43e1fdd
commit r15-6067-g1850da91610aa6df1f69f816aff6fecbb43e1fdd
Author: Pan Li <pan2...@intel.com>
Date: Sun Dec 8 19:56:18 2024 +0800
RISC-V: Refine signed vector SAT_ADD testcase dump check to tree optimized
The sat alu related testcase check the rtl dump for the standard name
like .SAT_ADD exist or not. But the rtl pass expand is somehow
impressionable by the middle-end change or debug information. Like
below new appearance recently.
Replacing Expressions
_5 replace with --> _5 = .SAT_ADD (x_3(D), y_4(D)); [tail call]
After that we need to adjust the dump check time and again. This
patch would like to switch to tree optimized pass for the standard
name check, which is more stable up to a point.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c: Take
tree-optimized pass for standard name check, and adjust the times.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c: Ditto.
Signed-off-by: Pan Li <pan2...@intel.com>
Diff:
---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c | 6 +++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c | 6 +++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c | 6 +++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c | 6 +++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c | 6 +++---
16 files changed, 48 insertions(+), 48 deletions(-)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c
index 6ef8ecbc1701..6147e7ab56ee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c
@@ -1,10 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_1(int16_t, uint16_t, INT16_MIN, INT16_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target {
no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target {
no-opts "-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c
index 46a4b6fdbd08..2312b5b60743 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c
@@ -1,10 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_1(int32_t, uint32_t, INT32_MIN, INT32_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target {
no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target {
no-opts "-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c
index 43c0e6306249..820bbaca52a1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c
@@ -1,10 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_1(int64_t, uint64_t, INT64_MIN, INT64_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target {
no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target {
no-opts "-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c
index cc2bd5c9a79c..5fd4741ee47f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c
@@ -1,10 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_1(int8_t, uint8_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target {
no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target {
no-opts "-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c
index 4c496300d8e6..f838dfc1e297 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c
@@ -1,10 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_2(int16_t, uint16_t, INT16_MIN, INT16_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target {
no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target {
no-opts "-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c
index 34d25f7a46dc..64b4d953b294 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c
@@ -1,10 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_2(int32_t, uint32_t, INT32_MIN, INT32_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target {
no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target {
no-opts "-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c
index 28544471a994..2daf299775ae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c
@@ -1,10 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_2(int64_t, uint64_t, INT64_MIN, INT64_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target {
no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target {
no-opts "-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c
index 0bba22667e4c..7d2c290f18dd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c
@@ -1,10 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_2(int8_t, uint8_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target {
no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target {
no-opts "-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c
index ccbe65a330e8..de121556891b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c
@@ -1,10 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_3(int16_t, uint16_t, INT16_MIN, INT16_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target {
no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target {
no-opts "-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c
index d1c67c8cbe0d..187c8b1f62f5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c
@@ -1,10 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_3(int32_t, uint32_t, INT32_MIN, INT32_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target {
no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target {
no-opts "-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c
index 49ca8d6d26e4..61ca265125a1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c
@@ -1,10 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_3(int64_t, uint64_t, INT64_MIN, INT64_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target {
no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target {
no-opts "-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c
index 3a2c887983ce..eaffe5f4fd10 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c
@@ -1,10 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_3(int8_t, uint8_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target {
no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target {
no-opts "-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c
index aa13604ca279..9808fc5be1ef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c
@@ -1,10 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_4(int16_t, uint16_t, INT16_MIN, INT16_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target {
no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target {
no-opts "-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c
index 2f47e5ba5498..ab691cbc2c73 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c
@@ -1,10 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_4(int32_t, uint32_t, INT32_MIN, INT32_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target {
no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target {
no-opts "-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c
index 1a943d2404f3..30326886a806 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c
@@ -1,10 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_4(int64_t, uint64_t, INT64_MIN, INT64_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target {
no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target {
no-opts "-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c
index 9ec120df69d8..928b4b66867b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c
@@ -1,10 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_ADD_FMT_4(int8_t, uint8_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts
"-O2" } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
"-O3" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target {
no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target {
no-opts "-O3" } } } } */
/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
