https://gcc.gnu.org/g:8c6f583d3d87b63c5ecace779ef359b568f7b747
commit r16-897-g8c6f583d3d87b63c5ecace779ef359b568f7b747
Author: Pan Li <pan2...@intel.com>
Date: Sun May 25 17:16:09 2025 +0800
RISC-V: Add test for vec_duplicate + vxor.vv combine case 0 with GR2VR cost
0, 2 and 15
Add asm dump check test for vec_duplicate + vxor.vv combine to vxor.vx,
with the GR2VR cost is 0, 2 and 15.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check
for vxor.vx combine.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
data for vxor run test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i8.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u8.c: New test.
Signed-off-by: Pan Li <pan2...@intel.com>
Diff:
---
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c | 2 +
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx_binary_data.h | 392 +++++++++++++++++++++
.../riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i16.c | 15 +
.../riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i32.c | 15 +
.../riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i64.c | 15 +
.../riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i8.c | 15 +
.../riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u16.c | 15 +
.../riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u32.c | 15 +
.../riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u64.c | 15 +
.../riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u8.c | 15 +
33 files changed, 560 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
index b15cb4cb8e6f..b9be0f674aec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vand.vx} 1 } } */
/* { dg-final { scan-assembler-times {vor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
index df3d3a33a342..2a84980cb503 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vand.vx} 1 } } */
/* { dg-final { scan-assembler-times {vor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
index ed17b8315776..9c7ea5fa4132 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vand.vx} 1 } } */
/* { dg-final { scan-assembler-times {vor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
index aa11dafc677f..fc23f1c49f96 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vand.vx} 1 } } */
/* { dg-final { scan-assembler-times {vor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
index 15db5887a035..7e107d30191d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vand.vx} 1 } } */
/* { dg-final { scan-assembler-times {vor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
index f15592c40eb2..f8ffab78067a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vand.vx} 1 } } */
/* { dg-final { scan-assembler-times {vor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
index 80e32afe8435..31d294567e83 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vand.vx} 1 } } */
/* { dg-final { scan-assembler-times {vor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
index 9b19276f2e6b..59e033401b21 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vand.vx} 1 } } */
/* { dg-final { scan-assembler-times {vor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
index 596488c87703..de250864e2d2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
/* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
index 8b4b7ebd2897..5cac7c685f66 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
/* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
index 544c9074a15c..4b2885a0da91 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
/* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
index af53f2b9ca43..e14683198e54 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
/* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
index a8ff915d7073..9612e3f66cc4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
/* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
index d587a88463e1..964180243b47 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
/* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
index ff205d53a55f..0d173e0dbbb9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
/* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
index e8e2c7fb6e70..931295ec0fb3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
/* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
index bd38b86bc552..d9e6e7b03891 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
/* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
index e0bdd2259fac..13d219ec73ad 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
/* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
index aab3b4afc7ff..037a713a60dd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
/* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
index 825988b04cce..c97fff4b09f5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
/* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
index a750510c1cee..24b4aa7efba1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
/* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
index 2d279cfa478f..0c1552a20541 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
/* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
index 5a90883c1df4..8364f19b1787 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
/* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
index 69af97a3a994..8a3111157ffe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
@@ -10,9 +10,11 @@ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
/* { dg-final { scan-assembler-not {vor.vx} } } */
+/* { dg-final { scan-assembler-not {vxor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
index cd3cede15c82..60f47f864bcd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
@@ -1966,4 +1966,396 @@ uint64_t TEST_BINARY_DATA(uint64_t, or)[][3][N] =
},
};
+int8_t TEST_BINARY_DATA(int8_t, xor)[][3][N] =
+{
+ {
+ { 0x1 },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x2, 0x2, 0x2, 0x2,
+ 0x0, 0x0, 0x0, 0x0,
+ 0xff, 0xff, 0xff, 0xff,
+ },
+ {
+ 0x0, 0x0, 0x0, 0x0,
+ 0x3, 0x3, 0x3, 0x3,
+ 0x1, 0x1, 0x1, 0x1,
+ 0xfe, 0xfe, 0xfe, 0xfe,
+ },
+ },
+ {
+ { 0x7f },
+ {
+ 0x7f, 0x7f, 0x7f, 0x7f,
+ 0x80, 0x80, 0x80, 0x80,
+ 0xf, 0xf, 0xf, 0xf,
+ 0x70, 0x70, 0x70, 0x70,
+ },
+ {
+ 0x0, 0x0, 0x0, 0x0,
+ 0xff, 0xff, 0xff, 0xff,
+ 0x70, 0x70, 0x70, 0x70,
+ 0xf, 0xf, 0xf, 0xf,
+ },
+ },
+ {
+ { 0xf0 },
+ {
+ 0xff, 0xff, 0xff, 0xff,
+ 0x1f, 0x1f, 0x1f, 0x1f,
+ 0x80, 0x80, 0x80, 0x80,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ {
+ 0xf, 0xf, 0xf, 0xf,
+ 0xef, 0xef, 0xef, 0xef,
+ 0x70, 0x70, 0x70, 0x70,
+ 0xf1, 0xf1, 0xf1, 0xf1,
+ },
+ },
+};
+
+int16_t TEST_BINARY_DATA(int16_t, xor)[][3][N] =
+{
+ {
+ { 0x1 },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x2, 0x2, 0x2, 0x2,
+ 0x0, 0x0, 0x0, 0x0,
+ 0xffff, 0xffff, 0xffff, 0xffff,
+ },
+ {
+ 0x0, 0x0, 0x0, 0x0,
+ 0x3, 0x3, 0x3, 0x3,
+ 0x1, 0x1, 0x1, 0x1,
+ 0xfffe, 0xfffe, 0xfffe, 0xfffe,
+ },
+ },
+ {
+ { 0x7fff },
+ {
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x8000, 0x8000, 0x8000, 0x8000,
+ 0xf, 0xf, 0xf, 0xf,
+ 0x7000, 0x7000, 0x7000, 0x7000,
+ },
+ {
+ 0x0, 0x0, 0x0, 0x0,
+ 0xffff, 0xffff, 0xffff, 0xffff,
+ 0x7ff0, 0x7ff0, 0x7ff0, 0x7ff0,
+ 0x0fff, 0x0fff, 0x0fff, 0x0fff,
+ },
+ },
+ {
+ { 0xfff0 },
+ {
+ 0xffff, 0xffff, 0xffff, 0xffff,
+ 0x1f, 0x1f, 0x1f, 0x1f,
+ 0x8000, 0x8000, 0x8000, 0x8000,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ {
+ 0xf, 0xf, 0xf, 0xf,
+ 0xffef, 0xffef, 0xffef, 0xffef,
+ 0x7ff0, 0x7ff0, 0x7ff0, 0x7ff0,
+ 0xfff1, 0xfff1, 0xfff1, 0xfff1,
+ },
+ },
+};
+
+int32_t TEST_BINARY_DATA(int32_t, xor)[][3][N] =
+{
+ {
+ { 0x1 },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x2, 0x2, 0x2, 0x2,
+ 0x0, 0x0, 0x0, 0x0,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ },
+ {
+ 0x0, 0x0, 0x0, 0x0,
+ 0x3, 0x3, 0x3, 0x3,
+ 0x1, 0x1, 0x1, 0x1,
+ 0xfffffffe, 0xfffffffe, 0xfffffffe, 0xfffffffe,
+ },
+ },
+ {
+ { 0x7fffffff },
+ {
+ 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+ 0x80000000, 0x80000000, 0x80000000, 0x80000000,
+ 0xf, 0xf, 0xf, 0xf,
+ 0x70000000, 0x70000000, 0x70000000, 0x70000000,
+ },
+ {
+ 0x0, 0x0, 0x0, 0x0,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x7ffffff0, 0x7ffffff0, 0x7ffffff0, 0x7ffffff0,
+ 0xfffffff, 0xfffffff, 0xfffffff, 0xfffffff,
+ },
+ },
+ {
+ { 0xfffffff0 },
+ {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x1f, 0x1f, 0x1f, 0x1f,
+ 0x80000000, 0x80000000, 0x80000000, 0x80000000,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ {
+ 0xf, 0xf, 0xf, 0xf,
+ 0xffffffef, 0xffffffef, 0xffffffef, 0xffffffef,
+ 0x7ffffff0, 0x7ffffff0, 0x7ffffff0, 0x7ffffff0,
+ 0xfffffff1, 0xfffffff1, 0xfffffff1, 0xfffffff1,
+ },
+ },
+};
+
+int64_t TEST_BINARY_DATA(int64_t, xor)[][3][N] =
+{
+ {
+ { 0x1 },
+ {
+ 0x1, 0x1, 0x1,
0x1,
+ 0x2, 0x2, 0x2,
0x2,
+ 0x0, 0x0, 0x0,
0x0,
+ 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
0xffffffffffffffffull,
+ },
+ {
+ 0x0, 0x0, 0x0,
0x0,
+ 0x3, 0x3, 0x3,
0x3,
+ 0x1, 0x1, 0x1,
0x1,
+ 0xfffffffffffffffeull, 0xfffffffffffffffeull, 0xfffffffffffffffeull,
0xfffffffffffffffeull,
+ },
+ },
+ {
+ { 0x7fffffffffffffffull },
+ {
+ 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
0x7fffffffffffffffull,
+ 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
0x8000000000000000ull,
+ 0xf, 0xf, 0xf,
0xf,
+ 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull,
0x7000000000000000ull,
+ },
+ {
+ 0x0, 0x0, 0x0,
0x0,
+ 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
0xffffffffffffffffull,
+ 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull,
0x7ffffffffffffff0ull,
+ 0xfffffffffffffffull, 0xfffffffffffffffull, 0xfffffffffffffffull,
0xfffffffffffffffull,
+ },
+ },
+ {
+ { 0xfffffffffffffff0ull },
+ {
+ 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
0xffffffffffffffffull,
+ 0x1f, 0x1f, 0x1f,
0x1f,
+ 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
0x8000000000000000ull,
+ 0x1, 0x1, 0x1,
0x1,
+ },
+ {
+ 0xf, 0xf, 0xf,
0xf,
+ 0xffffffffffffffefull, 0xffffffffffffffefull, 0xffffffffffffffefull,
0xffffffffffffffefull,
+ 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull,
0x7ffffffffffffff0ull,
+ 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull,
0xfffffffffffffff1ull,
+ },
+ },
+};
+
+uint8_t TEST_BINARY_DATA(uint8_t, xor)[][3][N] =
+{
+ {
+ { 0x1 },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x2, 0x2, 0x2, 0x2,
+ 0x0, 0x0, 0x0, 0x0,
+ 0xff, 0xff, 0xff, 0xff,
+ },
+ {
+ 0x0, 0x0, 0x0, 0x0,
+ 0x3, 0x3, 0x3, 0x3,
+ 0x1, 0x1, 0x1, 0x1,
+ 0xfe, 0xfe, 0xfe, 0xfe,
+ },
+ },
+ {
+ { 0x7f },
+ {
+ 0x7f, 0x7f, 0x7f, 0x7f,
+ 0x80, 0x80, 0x80, 0x80,
+ 0xf, 0xf, 0xf, 0xf,
+ 0x70, 0x70, 0x70, 0x70,
+ },
+ {
+ 0x0, 0x0, 0x0, 0x0,
+ 0xff, 0xff, 0xff, 0xff,
+ 0x70, 0x70, 0x70, 0x70,
+ 0xf, 0xf, 0xf, 0xf,
+ },
+ },
+ {
+ { 0xf0 },
+ {
+ 0xff, 0xff, 0xff, 0xff,
+ 0x1f, 0x1f, 0x1f, 0x1f,
+ 0x80, 0x80, 0x80, 0x80,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ {
+ 0xf, 0xf, 0xf, 0xf,
+ 0xef, 0xef, 0xef, 0xef,
+ 0x70, 0x70, 0x70, 0x70,
+ 0xf1, 0xf1, 0xf1, 0xf1,
+ },
+ },
+};
+
+uint16_t TEST_BINARY_DATA(uint16_t, xor)[][3][N] =
+{
+ {
+ { 0x1 },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x2, 0x2, 0x2, 0x2,
+ 0x0, 0x0, 0x0, 0x0,
+ 0xffff, 0xffff, 0xffff, 0xffff,
+ },
+ {
+ 0x0, 0x0, 0x0, 0x0,
+ 0x3, 0x3, 0x3, 0x3,
+ 0x1, 0x1, 0x1, 0x1,
+ 0xfffe, 0xfffe, 0xfffe, 0xfffe,
+ },
+ },
+ {
+ { 0x7fff },
+ {
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x8000, 0x8000, 0x8000, 0x8000,
+ 0xf, 0xf, 0xf, 0xf,
+ 0x7000, 0x7000, 0x7000, 0x7000,
+ },
+ {
+ 0x0, 0x0, 0x0, 0x0,
+ 0xffff, 0xffff, 0xffff, 0xffff,
+ 0x7ff0, 0x7ff0, 0x7ff0, 0x7ff0,
+ 0x0fff, 0x0fff, 0x0fff, 0x0fff,
+ },
+ },
+ {
+ { 0xfff0 },
+ {
+ 0xffff, 0xffff, 0xffff, 0xffff,
+ 0x1f, 0x1f, 0x1f, 0x1f,
+ 0x8000, 0x8000, 0x8000, 0x8000,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ {
+ 0xf, 0xf, 0xf, 0xf,
+ 0xffef, 0xffef, 0xffef, 0xffef,
+ 0x7ff0, 0x7ff0, 0x7ff0, 0x7ff0,
+ 0xfff1, 0xfff1, 0xfff1, 0xfff1,
+ },
+ },
+};
+
+uint32_t TEST_BINARY_DATA(uint32_t, xor)[][3][N] =
+{
+ {
+ { 0x1 },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x2, 0x2, 0x2, 0x2,
+ 0x0, 0x0, 0x0, 0x0,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ },
+ {
+ 0x0, 0x0, 0x0, 0x0,
+ 0x3, 0x3, 0x3, 0x3,
+ 0x1, 0x1, 0x1, 0x1,
+ 0xfffffffe, 0xfffffffe, 0xfffffffe, 0xfffffffe,
+ },
+ },
+ {
+ { 0x7fffffff },
+ {
+ 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+ 0x80000000, 0x80000000, 0x80000000, 0x80000000,
+ 0xf, 0xf, 0xf, 0xf,
+ 0x70000000, 0x70000000, 0x70000000, 0x70000000,
+ },
+ {
+ 0x0, 0x0, 0x0, 0x0,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x7ffffff0, 0x7ffffff0, 0x7ffffff0, 0x7ffffff0,
+ 0xfffffff, 0xfffffff, 0xfffffff, 0xfffffff,
+ },
+ },
+ {
+ { 0xfffffff0 },
+ {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x1f, 0x1f, 0x1f, 0x1f,
+ 0x80000000, 0x80000000, 0x80000000, 0x80000000,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ {
+ 0xf, 0xf, 0xf, 0xf,
+ 0xffffffef, 0xffffffef, 0xffffffef, 0xffffffef,
+ 0x7ffffff0, 0x7ffffff0, 0x7ffffff0, 0x7ffffff0,
+ 0xfffffff1, 0xfffffff1, 0xfffffff1, 0xfffffff1,
+ },
+ },
+};
+
+uint64_t TEST_BINARY_DATA(uint64_t, xor)[][3][N] =
+{
+ {
+ { 0x1 },
+ {
+ 0x1, 0x1, 0x1,
0x1,
+ 0x2, 0x2, 0x2,
0x2,
+ 0x0, 0x0, 0x0,
0x0,
+ 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
0xffffffffffffffffull,
+ },
+ {
+ 0x0, 0x0, 0x0,
0x0,
+ 0x3, 0x3, 0x3,
0x3,
+ 0x1, 0x1, 0x1,
0x1,
+ 0xfffffffffffffffeull, 0xfffffffffffffffeull, 0xfffffffffffffffeull,
0xfffffffffffffffeull,
+ },
+ },
+ {
+ { 0x7fffffffffffffffull },
+ {
+ 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
0x7fffffffffffffffull,
+ 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
0x8000000000000000ull,
+ 0xf, 0xf, 0xf,
0xf,
+ 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull,
0x7000000000000000ull,
+ },
+ {
+ 0x0, 0x0, 0x0,
0x0,
+ 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
0xffffffffffffffffull,
+ 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull,
0x7ffffffffffffff0ull,
+ 0xfffffffffffffffull, 0xfffffffffffffffull, 0xfffffffffffffffull,
0xfffffffffffffffull,
+ },
+ },
+ {
+ { 0xfffffffffffffff0ull },
+ {
+ 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
0xffffffffffffffffull,
+ 0x1f, 0x1f, 0x1f,
0x1f,
+ 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
0x8000000000000000ull,
+ 0x1, 0x1, 0x1,
0x1,
+ },
+ {
+ 0xf, 0xf, 0xf,
0xf,
+ 0xffffffffffffffefull, 0xffffffffffffffefull, 0xffffffffffffffefull,
0xffffffffffffffefull,
+ 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull,
0x7ffffffffffffff0ull,
+ 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull,
0xfffffffffffffff1ull,
+ },
+ },
+};
+
#endif
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i16.c
new file mode 100644
index 000000000000..844172033297
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i16.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int16_t
+#define NAME xor
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i32.c
new file mode 100644
index 000000000000..cdb773fe2136
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int32_t
+#define NAME xor
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i64.c
new file mode 100644
index 000000000000..8618b9e0f76e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int64_t
+#define NAME xor
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i8.c
new file mode 100644
index 000000000000..13724ceab9cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i8.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int8_t
+#define NAME xor
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u16.c
new file mode 100644
index 000000000000..e6030f377a45
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u16.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T uint16_t
+#define NAME xor
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u32.c
new file mode 100644
index 000000000000..cdb773fe2136
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int32_t
+#define NAME xor
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u64.c
new file mode 100644
index 000000000000..44f0fff438ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T uint64_t
+#define NAME xor
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u8.c
new file mode 100644
index 000000000000..2e983e56e899
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u8.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T uint8_t
+#define NAME xor
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
