https://gcc.gnu.org/g:6fbff06f9e39d75962b1cf5bfefb3d717ba4ace4
commit r15-6069-g6fbff06f9e39d75962b1cf5bfefb3d717ba4ace4
Author: Pan Li <pan2...@intel.com>
Date: Sun Dec 8 19:56:19 2024 +0800
RISC-V: Refine signed vector SAT_SUB testcase dump check to tree optimized
The sat alu related testcase check the rtl dump for the standard name
like .SAT_SUB exist or not. But the rtl pass expand is somehow
impressionable by the middle-end change or debug information. Like
below new appearance recently.
Replacing Expressions
_5 replace with --> _5 = .SAT_SUB (x_3(D), y_4(D)); [tail call]
After that we need to adjust the dump check time and again. This
patch would like to switch to tree optimized pass for the standard
name check, which is more stable up to a point.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c: Take
tree-optimized pass for standard name check, and adjust the times.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c: Ditto.
Signed-off-by: Pan Li <pan2...@intel.com>
Diff:
---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c | 6 +++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c | 6 +++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c | 6 +++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c | 6 +++---
.../gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c | 6 +++---
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c | 6 +++---
16 files changed, 48 insertions(+), 48 deletions(-)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c
index 38d105752377..5ae4515d2543 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_SUB_FMT_1(int16_t, uint16_t, INT16_MIN, INT16_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c
index b1d0ad03dae3..1f8457912315 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_SUB_FMT_1(int32_t, uint32_t, INT32_MIN, INT32_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c
index a7cb22d2fb4a..f16326651c71 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_SUB_FMT_1(int64_t, uint64_t, INT64_MIN, INT64_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c
index 28c24296dab9..fa9fbe693b8c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_SUB_FMT_1(int8_t, uint8_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c
index 19c76774a9ce..c0a220d9b405 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_SUB_FMT_2(int16_t, uint16_t, INT16_MIN, INT16_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c
index 572a4bd11277..367589580b7b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_SUB_FMT_2(int32_t, uint32_t, INT32_MIN, INT32_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c
index f41e939cd370..80a8470a6bcb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_SUB_FMT_2(int64_t, uint64_t, INT64_MIN, INT64_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c
index af21bf3b8576..a6ca17c748ba 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_SUB_FMT_2(int8_t, uint8_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c
index 88304e985fab..9fb3646e0e38 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_SUB_FMT_3(int16_t, uint16_t, INT16_MIN, INT16_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c
index f5a312e67f4a..fb7ca8f6ae3c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_SUB_FMT_3(int32_t, uint32_t, INT32_MIN, INT32_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c
index 327572152828..37ac03ccad78 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_SUB_FMT_3(int64_t, uint64_t, INT64_MIN, INT64_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c
index 8b3953f18613..d2c95519c1de 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_SUB_FMT_3(int8_t, uint8_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c
index 7057c6a275e1..8c77b34f94dc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_SUB_FMT_4(int16_t, uint16_t, INT16_MIN, INT16_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c
index f9c968d6b27c..ee2840fefb8d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_SUB_FMT_4(int32_t, uint32_t, INT32_MIN, INT32_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c
index cd96056d43c0..edf669e69270 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_SUB_FMT_4(int64_t, uint64_t, INT64_MIN, INT64_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c
index 24dfbe946394..b0e9e94277b1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c
@@ -1,14 +1,14 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
#include "vec_sat_arith.h"
DEF_VEC_SAT_S_SUB_FMT_4(int8_t, uint8_t, INT8_MIN, INT8_MAX)
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target {
any-opts
"-O3"
} } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target {
any-opts
"-O2"
} } } } */
/* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
