Re: Fix PR 118541, do not generate unordered fp cmoves for IEEE compares

Hi! On Wed, May 21, 2025 at 06:27:38AM +0200, Richard Biener wrote: > On Wed, May 21, 2025 at 12:30 AM Segher Boessenkool > wrote: > > > > On Mon, May 12, 2025 at 06:35:15PM -0400, Michael Meissner wrote: > > > On Mon, May 12, 2025 at 01:24:04PM +0530, Surya Kumari Jangala wrote: > > > > Hi Mike,

[PATCH] doc: Document the 'q' constraint for LoongArch

The kernel developers have requested such a constraint to use csrxchg in inline assembly. gcc/ChangeLog: * doc/md.texi: Document the 'q' constraint for LoongArch. --- Ok for trunk? gcc/doc/md.texi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi

Avoid double indirection in function_ref

This commit series implements double indirection avoidance for the function_ref and it is based on my patch for function_ref implementation. This patch is send as RFC instead of PATCH ready for review, as I have noticed that performing this implementation is user-observable and not allowed in the

[RFC 2/2] libstdc++: Avoid double indirection when cosntructing function_ref owning wrappers [PR119126]

This patch uses the additional provisions from LWG 4264, to avoid double indirection when function_ref is constructed from move_only_function or copyable_function with compatible signature. The details of compatible signatures follows the move_only_function as described in r16-617-g708d40ff109c6e49

Re: [RFC PATCH 0/3] _BitInt(N) support for LoongArch

On Wed, May 21, 2025 at 10:13:27AM +0800, Yang Yujie wrote: > On Tue, May 20, 2025 at 03:44:09PM GMT, Jakub Jelinek wrote: > > I'd suggest working on it incrementally rather than with a full patch set. > > In one or multiple patches handle the promote_mode stuff, the atomic > > extension and expr.c

[RFC 1/2] libstdc++: Avoid double indirection in function_ref when possible [PR119126]

This patch uses the additional provisions from LWG 4264, to avoid double indirection when function_ref is constructed from function_ref with compatible signature. The details of compatible signatures follows the move_only_function as described in r16-617-g708d40ff109c6e49d02b684a368571722a160af8.

Re: [PATCH] doc: Document the 'q' constraint for LoongArch

在 2025/5/21 下午3:14, Xi Ruoyao 写道: The kernel developers have requested such a constraint to use csrxchg in inline assembly. gcc/ChangeLog: * doc/md.texi: Document the 'q' constraint for LoongArch. --- Ok for trunk? LGTM! Thanks! gcc/doc/md.texi | 3 +++ 1 file changed, 3 ins

Re: [PATCH v2 1/6] libstdc++: Implement layout_left from mdspan.

On 5/21/25 08:29, Tomasz Kaminski wrote: On Tue, May 20, 2025 at 3:16 PM Luc Grosheintz wrote: Implements the parts of layout_left that don't depend on any of the other layouts. libstdc++-v3/ChangeLog: * include/std/mdspan (layout_left): New class. Signed-off-by: Luc Grosheintz

Re: [PATCH 3/5] libstdc++: keep subtree sizes in pb_ds binary search trees (PR 81806)

On Wed, 21 May 2025 at 06:57, Xi Ruoyao wrote: > > On Tue, 2025-05-20 at 13:06 +0100, Jonathan Wakely wrote: > > On 13/07/20 16:45 +0800, Xi Ruoyao via Libstdc++ wrote: > > > > > > > The second and third patch together resolve PR 81806. > > > > > > The attached patch modifies split_finish to use t

[PATCH] [aarch64] [vxworks] mark x18 as fixed, adjust tests

VxWorks uses x18 as the TCB, so STATIC_CHAIN_REGNUM has long been set (in gcc/config/aarch64/aarch64-vxworks.h) to use x9 instead. This patch marks x18 as fixed on TARGET_VXWORKS, so that it is not chosen by the register allocator, and adjusts tests that depend on x18 or on the static chain regi

Re: [PATCH] sparc: Avoid operandN variables in .md files

> gcc/ > * config/sparc/sparc.md (zero_extendhisi2, zero_extendhidi2) > (extendhisi2, extendqihi2, extendqisi2, extendqidi2) > (extendhidi2): Use operands[0] and operands[1] instead of > operand0 and operand1. OK, thanks. -- Eric Botcazou

Re: [PATCH v2 1/6] libstdc++: Implement layout_left from mdspan.

On Wed, May 21, 2025 at 10:20 AM Luc Grosheintz wrote: > > > On 5/21/25 08:29, Tomasz Kaminski wrote: > > On Tue, May 20, 2025 at 3:16 PM Luc Grosheintz > > > wrote: > > > >> Implements the parts of layout_left that don't depend on any of the > >> other layouts. > >> > >> libstdc++-v3/ChangeLog:

[PATCH] Fix IPA-SRA issue with reverse SSO on specific pattern

Hi, IPA-SRA generally works fine in the presence of reverse Scalar_Storage_Order by propagating the relevant flag onto the newly generated MEM_REFs. However we have been recently faced with a specific Ada pattern that it doesn't handle correctly: 'Valid applied to a floating-point component of

Re: [PATCH] testsuite: aarch64: arm: Fix -mcpu=unset support in shared effective targets

On Wed, 21 May 2025 at 10:56, Richard Sandiford wrote: > > Christophe Lyon writes: > > Many tests became unsupported on aarch64 when -mcpu=unset was added to > > several arm_* effective targets, because this flag is only supported > > on arm. > > > > Since these effective targets are used on arm

[PATCH v6] libstdc++: Implement C++26 function_ref [PR119126]

This patch implements C++26 function_ref as specified in P0792R14, with correction for constraints for constructor accepting nontype_t parameter from LWG 4256. As function_ref may store a pointer to the const object, __Ptrs::_M_obj is changed to const void*, so again we do not cast away const from

Re: [RFC PATCH 0/3] _BitInt(N) support for LoongArch

On Wed, May 21, 2025 at 09:21:40AM GMT, Jakub Jelinek wrote: > > The existing testsuite never tests whether the padding bits are sign or zero > extended or contain unknown values. > In the s390x patch, info->extended is set to true, yet all bitint tests but > bitint-64.c at -O3 pass. > > So, I'm

Re: [PATCH] testsuite: aarch64: arm: Fix -mcpu=unset support in shared effective targets

On Tue, May 20, 2025, 1:47 PM Christophe Lyon wrote: > Many tests became unsupported on aarch64 when -mcpu=unset was added to > several arm_* effective targets, because this flag is only supported > on arm. > > Since these effective targets are used on arm and aarch64, the patch > adds -mcpu=unse

[PATCH v3 2/9] libstdc++: Rename extents::_M_dynamic_extents.

The new name is _M_exts, which expresses the fact that it models all extents not just dynamic extents. It also shortens the name to make it consistent with _ExtentsStorage. libstdc++-v3/ChangeLog: * include/std/mdspan(extents): Change name of private member from _M_dynamic_extents

[PATCH v3 0/9] Implement layouts from mdspan.

Follows up on: https://gcc.gnu.org/pipermail/libstdc++/2025-May/061535.html To improve naming conventions, this series includes three new commits: * Two commits to rename _ExtentsStorage::_M_dynamic_extents, and extents::_M_dynamic_extents. * One commit to cleanup whitespace errors in ext

[PATCH v3 1/9] libstdc++: Rename _ExtentsStorage::_M_dynamic_extents.

The new name is _M_dyn_exts and makes space for a method _M_dynamic_extens, which returns a view of the requested dynamic extents. libstdc++-v3/ChangeLog: * include/std/mdspan(__mdspan::_ExtentsStorage): Change name of private member _M_dynamic_extens to _M_dyn_exts. Signed-off-b

[PATCH v3 4/9] libstdc++: Implement layout_left from mdspan.

Implements the parts of layout_left that don't depend on any of the other layouts. libstdc++-v3/ChangeLog: * include/std/mdspan (layout_left): New class. Signed-off-by: Luc Grosheintz --- libstdc++-v3/include/std/mdspan | 307 +++- 1 file changed, 306 insert

[PATCH v3 3/9] libstdc++: Cleanup formatting in mdspan.

libstdc++-v3/ChangeLog: * include/std/mdspan: Fix two instances of whitespace errors: `for(` -> `for (`. Signed-off-by: Luc Grosheintz --- libstdc++-v3/include/std/mdspan | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libstdc++-v3/include/std/mdspan b/li

[PATCH v3 8/9] libstdc++: Implement layout_stride from mdspan.

Implements the remaining parts of layout_left and layout_right; and all of layout_stride. libstdc++-v3/ChangeLog: * include/std/mdspan(layout_stride): New class. Signed-off-by: Luc Grosheintz --- libstdc++-v3/include/std/mdspan | 216 +++- 1 file changed, 21

[PATCH v3 9/9] libstdc++: Add tests for layout_stride.

Implements the tests for layout_stride and for the features of the other two layouts that depend on layout_stride. libstdc++-v3/ChangeLog: * testsuite/23_containers/mdspan/layouts/class_mandate_neg.cc: Add tests for layout_stride. * testsuite/23_containers/mdspan/layouts/c

[PATCH v3 6/9] libstdc++: Implement layout_right from mdspan.

Implement the parts of layout_left that depend on layout_right; and the parts of layout_right that don't depend on layout_stride. libstdc++-v3/ChangeLog: * include/std/mdspan (layout_right): New class. Signed-off-by: Luc Grosheintz --- libstdc++-v3/include/std/mdspan | 153

[PATCH v3 5/9] libstdc++: Add tests for layout_left.

Implements a suite of tests for the currently implemented parts of layout_left. The individual tests are templated over the layout type, to allow reuse as more layouts are added. libstdc++-v3/ChangeLog: * testsuite/23_containers/mdspan/layouts/class_mandate_neg.cc: New test. * tes

[PATCH v3 7/9] libstdc++: Add tests for layout_right.

Adds tests for layout_right and for the parts of layout_left that depend on layout_right. libstdc++-v3/ChangeLog: * testsuite/23_containers/mdspan/layouts/class_mandate_neg.cc: Add tests for layout_stride. * testsuite/23_containers/mdspan/layouts/ctors.cc: Add tests for

Re: [PATCH] i386: Extend *cmp_minus_1 optimizations also to plus with CONST_INT [PR120360]

On Wed, May 21, 2025 at 9:44 AM Jakub Jelinek wrote: > > Hi! > > As mentioned by Linus, we can't optimize comparison of otherwise unused > result of plus with CONST_INT second operand, compared against zero. > This can be done using just cmp instruction with negated constant and say > js/jns/je/jn

Re: [RFC PATCH 0/3] _BitInt(N) support for LoongArch

On Wed, May 21, 2025 at 05:38:27PM +0800, Yang Yujie wrote: > The current master branch does not seem to have _BitInt support for s390x, > is the patch on this list? > > Also, I cannot find the relevant psABI definition or discussions at > https://github.com/IBM/s390x-abi They were mailed to me p

Re: Fix PR 118541, do not generate unordered fp cmoves for IEEE compares

s Hi! On Thu, May 08, 2025 at 07:44:26PM -0400, Michael Meissner wrote: > In bug PR target/118541 on power9, power10, and power11 systems, for the > function: > > extern double __ieee754_acos (double); > > double > __acospi (double x) > { > double ret =

[PATCH] i386: Extend *cmp_minus_1 optimizations also to plus with CONST_INT [PR120360]

Hi! As mentioned by Linus, we can't optimize comparison of otherwise unused result of plus with CONST_INT second operand, compared against zero. This can be done using just cmp instruction with negated constant and say js/jns/je/jne etc. conditional jumps (or setcc). We already have *cmp_minus_1 i

Re: [PATCH v1 0/3] RISC-V: Combine vec_duplicate + vand.vv to vand.vx on GR2VR cost

This patch would like to introduce the combine of vec_dup + vand.vv into vand.vx on the cost value of GR2VR. The late-combine will take place if the cost of GR2VR is zero, or reject the combine if non-zero like 1, 15 in test. There will be two cases for the combine: OK, thanks. -- Regards Rob

Re: [RFC 2/2] libstdc++: Avoid double indirection when cosntructing function_ref owning wrappers [PR119126]

s/cosntructing/constructing/ -- Andreas Schwab, SUSE Labs, sch...@suse.de GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7 "And now for something completely different."

Re: [RFC PATCH 0/3] _BitInt(N) support for LoongArch

On Wed, May 21, 2025 at 09:21:40AM +0200, Jakub Jelinek wrote: > On Wed, May 21, 2025 at 10:13:27AM +0800, Yang Yujie wrote: > > On Tue, May 20, 2025 at 03:44:09PM GMT, Jakub Jelinek wrote: > > > I'd suggest working on it incrementally rather than with a full patch set. > > > In one or multiple pat

Re: [PATCH] [aarch64] [vxworks] mark x18 as fixed, adjust tests

Alexandre Oliva writes: > VxWorks uses x18 as the TCB, so STATIC_CHAIN_REGNUM has long been set > (in gcc/config/aarch64/aarch64-vxworks.h) to use x9 instead. > > This patch marks x18 as fixed on TARGET_VXWORKS, so that it is not > chosen by the register allocator, and adjusts tests that depend on

Re: [PATCH] testsuite: aarch64: arm: Fix -mcpu=unset support in shared effective targets

Christophe Lyon writes: > Many tests became unsupported on aarch64 when -mcpu=unset was added to > several arm_* effective targets, because this flag is only supported > on arm. > > Since these effective targets are used on arm and aarch64, the patch > adds -mcpu=unset on arm only, and restores ""

Re: [PATCH v23 0/3] c: Add _Countof and

On Wed, May 21, 2025 at 02:17:58AM +0200, Alejandro Colomar wrote: > Hi! > > Here's another revision of this patch set. > > v23 changes: > > - More specific change logs. > - #define assert() instead of #include'ing . > > `make check` says all's good. I haven't diffed against master this > ti

Re: [PATCH] aarch64: Carry over zeroness in aarch64_evpc_reencode

Pengxuan Zheng writes: > There was a bug in aarch64_evpc_reencode which could leave zero_op0_p and > zero_op1_p of the struct "newd" uninitialized. r16-701-gd77c3bc1c35e303 fixed > the issue by zero initializing "newd." This patch provides an alternative fix > as suggested by Richard Sandiford b

Re: [PATCH] fortran: add constant input support for trig functions with half-revolutions

Hi Yuao, first comments, I still need to look again at some changes, especially at simplify.cc. Yuao Ma wrote: This patch introduces constant input support for trigonometric functions, including those involving half-revolutions. Both valid and invalid inputs have been thoroughly tested, as

Re: [PATCH] [testsuite] [x86] memcpy-6 needs -msse2

On May 20, 2025, Alexandre Oliva wrote: > * memcpy-6.c: Bump to -msse2. I'd missed gcc.dg/ in the ChangeLog, and the checker was adamant that I ought to fix it ;-) -- Alexandre Oliva, happy hackerhttps://blog.lx.oliva.nom.br/ Free Software Activist FSFLA co-founder GN

Re: [PATCH] [testsuite] tolerate missing std::stold

On May 20, 2025, Jonathan Wakely wrote: > On Tue, 20 May 2025, 05:00 Alexandre Oliva, wrote: > OK Thanks > Maybe we should just define it in terms of std::stod, so it always exists > but might not support the full accuracy of long double. That sounds desirable to me, FWIW, but from past exper

Re: [PATCH] [testsuite] [x86] double copysign requires -msse2

On May 20, 2025, Alexandre Oliva wrote: > (This patch, as posted, applies on top of this: > https://gcc.gnu.org/pipermail/gcc-patches/2025-May/683066.html > plus the missing bit in the followup I've just posted) Since the ppc bits are not approved (yet?), I've rebased the x86 bits approved by Ur

[PATCH] fortran: add constant input support for trig functions with half-revolutions

Hi Tobias, Thanks for the thorough code review! I'm pretty swamped for the next couple of days, and I'll get the patch updated as you requested this weekend. > I don't understand this change. First, I don't see any reason why this > should get modified. And by modifying it, a simple "git blame" w

Re: [PATCH] [testsuite] [aarch64] match alt cache clear names in sme nonlocal_goto tests

On May 20, 2025, Richard Sandiford wrote: > Alexandre Oliva writes: >> -** bl __clear_cache >> +** bl .*ache.* > .* matches newlines, so how about: > bl [^\n]*[cC]ache[^\n]* > instead? OK if that works. Sure, thanks! Here's what I've installed: [testsuite] [aarch64

[PATCH] bitintlower: Ensure extension of the most significant limb on info->extended targets

On Wed, May 21, 2025 at 11:48:08AM +0200, Jakub Jelinek wrote: > With the following patch instead the test finally FAILs on s390x with -O1 > and higher, which shows that left shifts really need special casing for > info->extended. > I don't have proof of anything else though. Note, the shifts are

[PATCH v3 1/2] tree-simplify: unify simple_comparison ops in vec_cond for bit and/or/xor [PR119196]

Merge simple_comparison patterns under a single vec_cond_expr for bit_and, bit_ior, and bit_xor in the simplify pass. Ensure that when both operands of a bit_and, bit_or, or bit_xor are simple_comparison results, they reside within the same vec_cond_expr rather than separate ones. This prepares t

[PATCH v3 0/2] tree-optimization: extend scalar comparison folding to vectors [PR119196]

New in V3: Added XOR comparison optimization with the appropriate tests. Any further optimizations involving scalars are left for a future, separate patch, as these may be considered outside the scope of Bug 119196, whose focus was on missed folding of vector comparisons. -

Re: [PATCH] fortran: add constant input support for trig functions with half-revolutions

Hi, Yuao Ma wrote: I'm pretty swamped for the next couple of days Same issue here - hence, I haven't completed the review ... You're absolutely right that the best way to keep changes minimal is to just rename the `*resolve*` function. I missed the -gfc_resolve_trigd, +gfc_resolve_trig, c

[PATCH v3 2/2] gimple-fold: extend vector simplification to match scalar bitwise optimizations [PR119196]

Generalize existing scalar gimple_fold rules to apply the same bitwise comparison simplifications to vector types. Previously, an expression like (x < y) && (x > y) would fold to `false` if x and y are scalars, but equivalent vector comparisons were left untouched. T

Re: [PATCH 3/3] genemit: Use a byte encoding to generate insns

Jeff Law writes: > Given you know the RTL gen* related thingies better than anyone, I'd say > go forward and if there's any fallout, we can certainly cope with it. Thanks. I've now pushed the series and the earlier genemit tweaks, with the discussed change to mark the operandN arguments as cons

[to-be-committed][RISC-V] Improve (x << C1) + C2 split code

I wrote this a couple months ago to fix an instruction count regression in 505.mcf on risc-v, but I don't have a trivial little testcase to add to the suite. There were two problems with the pattern. First, the code was generating a shift followed by an add after reload. Naturally combine doe

Re: [PATCH v24 2/3] c: Add

On Wed, May 21, 2025 at 11:01:35PM +0200, Alejandro Colomar wrote: > gcc/ChangeLog: > > * Makefile.in (USER_H): Add . > * ginclude/stdcountof.h: Add countof macro. This one is actually : New file. If the header existed before and you've just added countof macro definition, it would be

Re: [PATCH v24 1/3] c: Add _Countof operator

On Wed, May 21, 2025 at 11:01:31PM +0200, Alejandro Colomar wrote: > This operator is similar to sizeof but can only be applied to an array, > and returns its number of elements. > > FUTURE DIRECTIONS: > > - We should make it work with array parameters to functions, >and somehow magically re

Re: [PATCH v24 3/3] c: Add -Wpedantic diagnostic for _Countof

On Wed, May 21, 2025 at 11:01:38PM +0200, Alejandro Colomar wrote: > It has been standardized in C2y. > > gcc/c/ChangeLog: > > * c-parser.cc (c_parser_sizeof_or_countof_expression): > Add -Wpedantic diagnostic for _Countof in <= C23 mode. > > gcc/testsuite/ChangeLog: > > * gcc

Re: [PATCH] configure: Always add pre-installed header directories to search path

On 9/25/24 9:22 PM, Stephanos Ioannidis wrote: configure script was adding the target directory flags, including the '-B' flags for the executable prefix and the '-isystem' flags for the pre-installed header directories, to the target flags only for non-Canadian builds under the premise that t

Re: [AUTOFDO] Merge profiles of clones before annotating

Ping? Thanks, Kugan > On 9 May 2025, at 11:54 am, Kugan Vivekanandarajah > wrote: > > External email: Use caution opening links or attachments > > > This patch add support for merging profiles from multiple clones. > That is, when optimized binaries have clones such as IPA-CP clone or SRA > c

Re: [AUTOFDO] Fix annotated profile for de-duplicated call

Ping? Thanks, Kugan > On 9 May 2025, at 11:51 am, Kugan Vivekanandarajah > wrote: > > External email: Use caution opening links or attachments > > > This patch fixes wrong annotation of profiles when call statement is > de-duplicated. i.e., when we may have same stmt executing from > more tha

Re: [AUTOFDO] Enable ipa-split for auto-profile

Ping? Thanks, Kugan > On 9 May 2025, at 11:55 am, Kugan Vivekanandarajah > wrote: > > ipa-split is not now run for auto-profile. IMO this was an oversight. > This patch enables it similar to PGO runs. > > gcc/ChangeLog: > >* ipa-split.cc pass_feedback_split_functions::clone (): New. >

Re: [PATCH 1/2] expand: Use rtx_cost directly instead of gen_move_insn for canonicalize_comparison.

On 5/20/25 9:12 PM, Andrew Pinski wrote: This is the first part in fixing PR target/120372. The current code for canonicalize_comparison, uses gen_move_insn and rtx_cost to find out the cost of generating a constant. This is ok in most cases except sometimes the comparison instruction can han

[PATCH v2] libstdc++: implement Philox Engine [PR119794]

Implements Philox Engine (P2075R6) and associated tests. v2 corrects a multiline comment left in error in serialize.cc, and additionally corrects a bug hidden by said comment, where the stream was given the output of 'y()' instead of 'y', causing state to be incorrectly passed. Lastly, it fixes

RE: [PATCH] aarch64: Carry over zeroness in aarch64_evpc_reencode

> Pengxuan Zheng writes: > > There was a bug in aarch64_evpc_reencode which could leave zero_op0_p > > and zero_op1_p of the struct "newd" uninitialized. > > r16-701-gd77c3bc1c35e303 fixed the issue by zero initializing "newd." > > This patch provides an alternative fix as suggested by Richard > >

[PATCH 1/2] Support picolibc targets

Match *-picolibc-* and select picolibc as the default C library, plus continuing to use the newlib-based logic for other configuration items. Add custom spec file fragments for use with picolibc: * '--oslib='. Allows targets to insert an OS library after the C library in the LIB_PATH spec fil

Re: [RFC PATCH 0/3] _BitInt(N) support for LoongArch

On Wed, May 21, 2025 at 11:48:08AM GMT, Jakub Jelinek wrote: > In gimple-lower-bitint.cc I'd strongly prefer to differentiate between > changes required to get info->extended working correctly (that is what > should be committed first, and right now should include the LSHIFT_EXPR in > lower_shift_s

[PATCH 0/4] c++: Support modules streaming some internal structures with no DECL_CONTEXT

This patch series adds support for streaming some internal declarations in C++20 modules that we previously would ICE on. The series has been successfully bootstrapped and regtested on x86_64-pc-linux-gnu. Additionally, modules.exp now passes with '--target_board=unix/-fsanitize=undefined'. Na

[PATCH 1/4] c++: Add flag to detect underlying representative of bitfield decls

This patch isn't currently necessary with how I've currently done the follow-up patches, but is needed for avoiding any potential issues in the future with DECL_CONTEXT'ful types getting created in the compiler with no names on the fields. (For instance, this change would make much of r15-7342-gd3

[PATCH 2/4] c++/modules: Implement streaming of uncontexted TYPE_DECLs [PR98735]

Another approach would be to fix 'write_class_def' to handle these declarations better, but that ended up being more work and felt fragile. It also meant streaming a lot more information that we don't need. Long term I had been playing around with reworking ubsan.cc entirely to have a fixed set of

[PATCH 4/4] c++/modules: Avoid name clashes when streaming internal labels [PR98375,PR118904]

I'm not sure if there might be a better way to retrieve the prefix back off an IDENTIFIER_NODE? I'm also not sure if IDENTIFIER_INTERNAL_P could ever clash with IDENTIFIER_TRANSPARENT_ALIAS; I'm pretty sure not (and it looks like nothing ever sets that flag anyway, that I could find?) but would ap

[PATCH 3/4] c++/modules: Support streaming new size cookie for constexpr [PR120040]

This type currently has a DECL_NAME of an IDENTIFIER_DECL. Although the documentation indicates this is legal, this confuses modules streaming which expects all RECORD_TYPEs to have a TYPE_DECL, which is used to determine the context and merge key, etc. PR c++/120040 gcc/cp/ChangeLog:

Re: [PATCH 2/4] c++/modules: Implement streaming of uncontexted TYPE_DECLs [PR98735]

On Thu, May 22, 2025 at 12:15:02PM +1000, Nathaniel Shead wrote: > Another approach would be to fix 'write_class_def' to handle these > declarations better, but that ended up being more work and felt fragile. > It also meant streaming a lot more information that we don't need. > > Long term I had

Re: [PATCH v24 1/3] c: Add _Countof operator

Hi Jakub, On Wed, May 21, 2025 at 11:12:07PM +0200, Jakub Jelinek wrote: > > * c-common.h: Add RID_COUNTOF. > > (enum rid): Add RID_COUNTOF. Okay. > > > (c_countof_type): New function prototype. > > * c-common.def (COUNTOF_EXPR): New tree. > > * c-common.cc > > (c_common_re

[PATCH 0/2] Add picolibc support

The first patch in this series selects picolibc as the default C library when the target is *-picolibc-*. This configures the default compiler specs for picolibc usage, including the addition of three picolic-specific options. The section patch in this series allows the default C library to be sel

[PATCH 2/2] Allow default libc (either newlib or picolibc) to be specified to configure

The default C library is normally computed based on the target triplet. However, for embedded systems, it can be useful to leave the triplet alone while changing which C library is used by default. Other C libraries may still be available on the system so the compiler and can be used by specifying

Re: [PATCH][RISC-V][PR target/70557] Improve storing 0 to memory on rv32

On 5/21/25 12:20 PM, Shreya Munnangi wrote: Patch is originally from Siarhei Volkau >. RISC-V has a zero register (x0) which we can use to store zero into memory without loading the constant into a distinct register. Adjust the constraints of the 32-bit movdi_32bit

[PATCH v25 0/3] c: Add _Countof and

Hi! Here's v25. Changes compared to v24 (see range-diff below): - Small fixes to the change logs. - Rewrap and remove parentheses in chains of ?: . - Implement c_parser_{sizeof,countof}_expression() as static inline. Tests still pass: $ grep countof ./gcc/testsuite/gcc/gcc.sum

[PATCH v25 2/3] c: Add

gcc/ChangeLog: * Makefile.in (USER_H): Add . * ginclude/stdcountof.h: New file. gcc/testsuite/ChangeLog: * gcc.dg/countof-stdcountof.c: New test. Signed-off-by: Alejandro Colomar --- gcc/Makefile.in | 1 + gcc/ginclude/stdcountof.h

[PATCH v25 3/3] c: Add -Wpedantic diagnostic for _Countof

It has been standardized in C2y. gcc/c/ChangeLog: * c-parser.cc (c_parser_sizeof_or_countof_expression): Add -Wpedantic diagnostic for _Countof in <= C23 mode. gcc/testsuite/ChangeLog: * gcc.dg/countof-compat.c: New test. * gcc.dg/countof-no-compat.c: New test.

[PATCH v25 1/3] c: Add _Countof operator

This operator is similar to sizeof but can only be applied to an array, and returns its number of elements. FUTURE DIRECTIONS: - We should make it work with array parameters to functions, and somehow magically return the number of elements of the array, regardless of it being really a poin

[PATCH] testsuite: RISC-V: Update the cset-sext-sfb/zba-slliuw test optimization level.

Failed testcases occurred in the regression test of gcc: cset-sext-sfb.c failed the -Oz test, and zba-slliuw.c failed the -Og test. This patch solves the problem by skipping the optimization. gcc/testsuite/ChangeLog: * gcc.target/riscv/cset-sext-sfb.c: Skip for -Oz. * gcc.target/r

Re: [PATCH] RISC-V: Default-initialize variable.

LGTM On Wed, May 21, 2025 at 9:49 PM Robin Dapp wrote: > > Hi, > > this patch initializes saved_vxrm_mode to VXRM_MODE_NONE. This is a > warning (but no error) when building the compiler so better fix it. > > Regtested on rv64gcv_zvl512b. Going to commit as obvious if the CI > is happy. > > Reg

Re: [PATCH] RISC-V: Support CPUs in -march.

I could imagine that is a simpler way to set the march since the march string becomes terribly long - we have an arch string more than 300 char...so I support this, although I think this should be discuss with LLVM community, but I think it's fine to accept as a GCC extension. So LGTM, go ahead to

[PATCH v4 1/1] Add warnings of potentially-uninitialized padding bits

Commit 0547dbb725b reduced the number of cases in which union padding bits are zeroed when the relevant language standard does not strictly require it, unless gcc was invoked with -fzero-init-padding-bits=unions or -fzero-init-padding-bits=all in order to explicitly request

[PATCH] libstdc++: Fix vector(from_range_t, R&&) for exceptions [PR120367]

Because this constructor delegates to vector(a) the object has been fully constructed and the destructor will run if an exception happens. That means we need to set _M_finish == _M_start so that the destructor doesn't try to destroy any elements. libstdc++-v3/ChangeLog: PR libstdc++/12036

Re: [PATCH 2/2] RISC-V:Add testcases for signed .SAT_ADD IMM form 1 with IMM = -1.

On 5/20/25 8:39 PM, Li, Pan2 wrote: Thanks Jeff. So for the tests, why are we forcing matching of the assembly code for the entire function? That must makes for a fragile test as we may change various aspects of code generation over time. If the point of the patch is to detect SAT_ADD in

Re: [PATCH V4] RISC-V: Prevent speculative vsetvl insn scheduling

On 5/20/25 4:05 PM, Edwin Lu wrote: The instruction scheduler appears to be speculatively hoisting vsetvl insns outside of their basic block without checking for data dependencies. This resulted in a situation where the following occurs vsetvli a5,a1,e32,m1,tu,ma vle32.v v2,

Re: [PATCH V4] RISC-V: Prevent speculative vsetvl insn scheduling

On 5/20/25 4:05 PM, Edwin Lu wrote: The instruction scheduler appears to be speculatively hoisting vsetvl insns outside of their basic block without checking for data dependencies. This resulted in a situation where the following occurs vsetvli a5,a1,e32,m1,tu,ma vle32.v v2,

Re: [PATCH 0/3] Redirect to specific target based on TARGET_VERSION_COMPATIBLE

On 4/14/25 5:34 AM, Yangyu Chen wrote: On 14 Apr 2025, at 19:06, Alfie Richards wrote: Hi Yangyu, This looks great with what we discussed previously. I have a very similar patch that implements a slightly stronger optimisation that I was about to send. It makes use of information if th

Re: Fix PR 118541, do not generate unordered fp cmoves for IEEE compares

I have posted a new version of the patch at: https://gcc.gnu.org/pipermail/gcc-patches/2025-May/684473.html -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss...@linux.ibm.com

Re: [PATCH 2/2] aarch64: Fold lsl+lsr+orr to rev for half-width shifts

On 20/05/25 16:35, Richard Sandiford wrote: External email: Use caution opening links or attachments Dhruv Chawla writes: On 06/05/25 21:57, Richard Sandiford wrote: External email: Use caution opening links or attachments Dhruv Chawla writes: This patch modifies the intrinsic expanders

[PATCH v4 1/2] aarch64: Match unpredicated shift patterns for ADR, SRA and ADDHNB instructions

From: Dhruv Chawla This patch modifies the shift expander to immediately lower constant shifts without unspec. It also modifies the ADR, SRA and ADDHNB patterns to match the lowered forms of the shifts, as the predicate register is not required for these instructions. Bootstrapped and regtested

Re: [PATCH] testsuite: RISC-V: Update the cset-sext-sfb/zba-slliuw test optimization level.

Thanks. I will pay attention to this. Dongyan Chen 在 2025/5/22 11:49, Jeff Law 写道: On 5/21/25 9:16 PM, Dongyan Chen wrote: Failed testcases occurred in the regression test of gcc: cset-sext-sfb.c failed the -Oz test, and zba-slliuw.c failed the -Og test. This patch solves the problem by ski

[PATCH v4 2/2] aarch64: Fold lsl+lsr+orr to rev for half-width shifts

From: Dhruv Chawla This patch folds the following pattern: lsl , , lsr , , orr , , to: revb/h/w , when the shift amount is equal to half the bitwidth of the register. Bootstrapped and regtested on aarch64-linux-gnu. Signed-off-by: Dhruv Chawla Co-authored-by: Richard Sandiford

Fix PR 118541 (V3), do not generate unordered fp cmoves for IEEE compares

Fix PR 118541, do not generate unordered fp cmoves for IEEE compares. This is version 3 of patch. I re-implemented the patch to just focus on the generation of the XSCMP{EQ,GT,GE}{DP,QP} instructions. In bug PR target/118541 on power9, power10, and power11 systems, for the function: ext

Re: Fix PR 118541 (V6 not V3), do not generate unordered fp cmoves for IEEE compares

I got the version number of the patch wrong. This patch is something like V6 of the patch, not V3. -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss...@linux.ibm.com

[PATCH][RISC-V][PR target/70557] Improve storing 0 to memory on rv32

Patch is originally from Siarhei Volkau . RISC-V has a zero register (x0) which we can use to store zero into memory without loading the constant into a distinct register. Adjust the constraints of the 32-bit movdi_32bit pattern to recognize that we can store 0.0 into memory using x0 as the source

Re: [PATCH] testsuite: RISC-V: Update the cset-sext-sfb/zba-slliuw test optimization level.

On 5/21/25 9:16 PM, Dongyan Chen wrote: Failed testcases occurred in the regression test of gcc: cset-sext-sfb.c failed the -Oz test, and zba-slliuw.c failed the -Og test. This patch solves the problem by skipping the optimization. gcc/testsuite/ChangeLog: * gcc.target/riscv/cset-sex

Re: [PATCH v2 1/6] libstdc++: Implement layout_left from mdspan.

On Wed, May 21, 2025 at 10:20 AM Luc Grosheintz wrote: > > > On 5/21/25 08:29, Tomasz Kaminski wrote: > > On Tue, May 20, 2025 at 3:16 PM Luc Grosheintz > > > wrote: > > > >> Implements the parts of layout_left that don't depend on any of the > >> other layouts. > >> > >> libstdc++-v3/ChangeLog:

Re: [PATCH] libstdc++: Fix vector(from_range_t, R&&) for exceptions [PR120367]

On Wed, May 21, 2025 at 5:41 PM Jonathan Wakely wrote: > Because this constructor delegates to vector(a) the object has been > fully constructed and the destructor will run if an exception happens. > That means we need to set _M_finish == _M_start so that the destructor > doesn't try to destroy a

[PATCH] RISC-V: Add minimal support of double trap extension 1.0

Add support of double trap extension [1], enabling GCC to recognize the following extensions at compile time. New extensions: - ssdbltrp - smdbltrp [1] https://github.com/riscv/riscv-double-trap/releases/download/v1.0/riscv-double-trap.pdf gcc/ChangeLog: * config/riscv/riscv-ext.def

Re: [PATCH v24 1/3] c: Add _Countof operator

Hi Jakub, On Wed, May 21, 2025 at 11:12:07PM +0200, Jakub Jelinek wrote: > > warning_at (loc, OPT_Wc___compat, > > "defining type in %qs expression is invalid in C++", > > (in_sizeof > > ? "sizeof" > > -: (in_typeof ? "typeof" : "alignof"))); >

Re: [PATCH v24 1/3] c: Add _Countof operator

On Wed, May 21, 2025 at 11:36:56PM +0200, Alejandro Colomar wrote: > Hi Jakub, > > On Wed, May 21, 2025 at 11:12:07PM +0200, Jakub Jelinek wrote: > > > warning_at (loc, OPT_Wc___compat, > > > "defining type in %qs expression is invalid in C++", > > > (in_sizeof > > >

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