Patch is originally from Siarhei Volkau <[email protected]>.
RISC-V has a zero register (x0) which we can use to store zero into memory
without loading the constant into a distinct register. Adjust the
constraints
of the 32-bit movdi_32bit pattern to recognize that we can store 0.0 into
memory using x0 as the source register.
This patch only affects RISC-V. It has been regression tested on
riscv64-elf.
Jeff has also tested this in his tester (riscv64-elf and riscv32-elf) with
no
regressions.
PR target/70557
gcc/
* config/riscv/riscv.md (movdi_32bit): Add "J" constraint to allow
storing 0
directly to memory.
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 0a5899a0f72..ef13a1c7e26 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2573,8 +2573,8 @@
})
(define_insn "*movdi_32bit"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,m,
*f,*f,*r,*f,*m,r")
- (match_operand:DI 1 "move_operand" "
r,i,m,r,*J*r,*m,*f,*f,*f,vp"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r, m,
*f,*f,*r,*f,*m,r")
+ (match_operand:DI 1 "move_operand" "
r,i,m,rJ,*J*r,*m,*f,*f,*f,vp"))]
"!TARGET_64BIT
&& (register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))"
