Hi,

This patch allows an -march string like

 -march=sifive-p670

in order to allow overriding a previous -march in a simple way.

Suppose we have a Makefile that specifies -march=rv64gc by default.
A user-specified -mcpu=sifive-p670 would be after the -march in the
options string and thus only set -mtune=sifive-p670 (as -mcpu does not
override a previously specified -march or -mtune).

So if we wanted to override we would need to specify the full, lengthy
-march=rv64gcv_... string instead of a simple -mcpu=...

Therefore this patch always first tries to interpret -march= as CPU
string.  If it is a supported CPU we use its march properties and let it
override previously specified options.  Otherwise the behavior is as
before.  This enables the "last-specified option wins" behavior GCC
normally employs.

Note that -march does not imply -mtune like on x86 or other targets.
So an -march=CPU won't override a previously specified -mtune=other-CPU.

I haven't spent a lot of time on this (basically stopped once it looked
like it's working) and was hoping somebody who touched these riscv parts
will notice glaring holes :)

Regtested on rv64gcv_zvl512b.

Regards
Robin

gcc/ChangeLog:

        * common/config/riscv/riscv-common.cc 
(riscv_subset_list::parse_base_ext):
        Adjust error message.
        (riscv_handle_option): Parse as CPU string first.
        (riscv_expand_arch): Ditto.
        * doc/invoke.texi: Document.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/arch-56.c: New test.
---
gcc/common/config/riscv/riscv-common.cc  | 19 ++++++++++++-------
gcc/doc/invoke.texi                      |  2 +-
gcc/testsuite/gcc.target/riscv/arch-56.c | 13 +++++++++++++
3 files changed, 26 insertions(+), 8 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-56.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index c843393998c..a6d8763f032 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -980,8 +980,9 @@ riscv_subset_list::parse_base_ext (const char *p)
    }
  else
    {
-      error_at (m_loc, "%<-march=%s%>: ISA string must begin with rv32, rv64 "
-               "or Profiles", m_arch);
+      error_at (m_loc, "%<-march=%s%>: ISA string must begin with rv32, rv64,"
+               " a supported RVA profile or refer to a supported CPU",
+               m_arch);
      return NULL;
    }

@@ -1708,7 +1709,8 @@ riscv_handle_option (struct gcc_options *opts,
  switch (decoded->opt_index)
    {
    case OPT_march_:
-      riscv_parse_arch_string (decoded->arg, opts, loc);
+      if (riscv_find_cpu (decoded->arg) == NULL)
+       riscv_parse_arch_string (decoded->arg, opts, loc);
      return true;

    case OPT_mcpu_:
@@ -1725,15 +1727,18 @@ riscv_handle_option (struct gcc_options *opts,
/* Expand arch string with implied extensions.  */

const char *
-riscv_expand_arch (int argc ATTRIBUTE_UNUSED,
+riscv_expand_arch (int argc,
                   const char **argv)
{
  gcc_assert (argc == 1);
  location_t loc = UNKNOWN_LOCATION;
-  riscv_parse_arch_string (argv[0], NULL, loc);
+  /* Try to interpret the arch as CPU first.  */
+  const char *arch_str = riscv_expand_arch_from_cpu (argc, argv);
+  if (!strlen (arch_str))
+    riscv_parse_arch_string (argv[0], NULL, loc);
  const std::string arch = riscv_arch_str (false);
-  if (arch.length())
-    return xasprintf ("-march=%s", arch.c_str());
+  if (arch.length ())
+    return xasprintf ("-march=%s", arch.c_str ());
  else
    return "";
}
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 52cfdb99871..2368509034f 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1268,7 +1268,7 @@ See RS/6000 and PowerPC Options.
-mfence-tso  -mno-fence-tso
-mdiv  -mno-div
-misa-spec=@var{ISA-spec-string}
--march=@var{ISA-string|Profiles|Profiles_ISA-string}
+-march=@var{ISA-string|Profiles|Profiles_ISA-string|CPU/processor string}
-mtune=@var{processor-string}
-mpreferred-stack-boundary=@var{num}
-msmall-data-limit=@var{N-bytes}
diff --git a/gcc/testsuite/gcc.target/riscv/arch-56.c 
b/gcc/testsuite/gcc.target/riscv/arch-56.c
new file mode 100644
index 00000000000..c0b43b74a49
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-56.c
@@ -0,0 +1,13 @@
+/* Check whether the second -march overrides the first.  */
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=rv64gc -march=sifive-p670" } */
+
+void
+foo (char *a, char *b, int n)
+{
+  for (int i = 0; i < n; i++)
+    a[i] = b[i] + 1;
+}
+
+/* { dg-final { scan-assembler "vset" } } */
+/* { dg-final { scan-assembler "zvl128b" } } */
--
2.49.0


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