On 5/20/25 4:05 PM, Edwin Lu wrote:
The instruction scheduler appears to be speculatively hoisting vsetvl
insns outside of their basic block without checking for data
dependencies. This resulted in a situation where the following occurs
vsetvli a5,a1,e32,m1,tu,ma
vle32.v v2,0(a0)
sub a1,a1,a5 <-- a1 potentially set to 0
sh2add a0,a5,a0
vfmacc.vv v1,v2,v2
vsetvli a5,a1,e32,m1,tu,ma <-- incompatible vinfo. update vl to 0
beq a1,zero,.L12 <-- check if avl is 0
This patch would essentially delay the vsetvl update to after the branch
to prevent unnecessarily updating the vinfo at the end of a basic block.
PR 117974
gcc/ChangeLog:
* config/riscv/riscv.cc (struct riscv_tune_param): Add tune
param.
(riscv_sched_can_speculate_insn): Implement.
(TARGET_SCHED_CAN_SPECULATE_INSN): Implement.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/pr117974.c: New test.
Though note it failed CI on the new test:
FAIL: gcc.target/riscv/rvv/vsetvl/pr117974.c -O3 -fomit-frame-pointer
-funroll-loops -fpeel-loops -ftracer -finline-functions scan-assembler-times
beq\\s+[a-x0-9]+,zero,.L12\\s+vsetvli 3
So something probably needs a minor adjustment.
Jeff
