[gcc r15-5012] Check LOOP_VINFO_PEELING_FOR_GAPS on epilog is supported

https://gcc.gnu.org/g:76048bd0693e30a5abc67aa6dcce9f4973ea208e commit r15-5012-g76048bd0693e30a5abc67aa6dcce9f4973ea208e Author: Richard Biener Date: Mon Nov 4 13:03:33 2024 +0100 Check LOOP_VINFO_PEELING_FOR_GAPS on epilog is supported We need to check that an epilogue doesn't re

[gcc r15-5020] VN: Factor out inserting predicates for conditional

https://gcc.gnu.org/g:b38f8294e4f29132c8cf4c5d3f3beb64bb0c499d commit r15-5020-gb38f8294e4f29132c8cf4c5d3f3beb64bb0c499d Author: Andrew Pinski Date: Fri Nov 1 19:28:19 2024 -0700 VN: Factor out inserting predicates for conditional To make it easier to add more predicates in some c

[gcc r15-5014] Add LOOP_VINFO_MAIN_LOOP_INFO

https://gcc.gnu.org/g:42d99f63cfccabe1d19177993abf4f1219d6f967 commit r15-5014-g42d99f63cfccabe1d19177993abf4f1219d6f967 Author: Richard Biener Date: Mon Nov 4 12:58:41 2024 +0100 Add LOOP_VINFO_MAIN_LOOP_INFO The following introduces LOOP_VINFO_MAIN_LOOP_INFO alongside LOOP_V

[gcc r15-5025] btf: check hash maps are non-null before emptying

https://gcc.gnu.org/g:6571e8f863736b7705f59c9ab0f17b7c4fdbcf92 commit r15-5025-g6571e8f863736b7705f59c9ab0f17b7c4fdbcf92 Author: David Faust Date: Thu Nov 7 09:19:51 2024 -0800 btf: check hash maps are non-null before emptying These maps will always be non-null in btf_finalize und

[gcc r15-5024] ifcombine: For short circuit case, allow 2 convert defining statements [PR85605]

https://gcc.gnu.org/g:2a2e6784074e1f7b679bc09b1a66982bf60645a5 commit r15-5024-g2a2e6784074e1f7b679bc09b1a66982bf60645a5 Author: Andrew Pinski Date: Mon Oct 28 16:40:34 2024 -0700 ifcombine: For short circuit case, allow 2 convert defining statements [PR85605] r0-126134-g5d2a9da9

[gcc r15-5021] VN: Handle `(a | b) !=/== 0` for predicates [PR117414]

https://gcc.gnu.org/g:578002846620ed04192a4832e9f20b5c32816153 commit r15-5021-g578002846620ed04192a4832e9f20b5c32816153 Author: Andrew Pinski Date: Fri Nov 1 20:06:30 2024 -0700 VN: Handle `(a | b) !=/== 0` for predicates [PR117414] For `(a | b) == 0`, we can "assert" on the true

[gcc r15-5022] VN: Handle `(A CMP B) !=/== 0` for predicates [PR117414]

https://gcc.gnu.org/g:add4bb94459d6cecae11de279b49f9c1acb14394 commit r15-5022-gadd4bb94459d6cecae11de279b49f9c1acb14394 Author: Andrew Pinski Date: Fri Nov 1 23:12:52 2024 -0700 VN: Handle `(A CMP B) !=/== 0` for predicates [PR117414] After the last patch, we also want to record

[gcc r15-5023] VN: Lookup `val != 0` if we got back val when looking up the predicate for GIMPLE_COND [PR117414]

https://gcc.gnu.org/g:684e5ae90b64c3481f8a5cb7b9517daf79c78ab4 commit r15-5023-g684e5ae90b64c3481f8a5cb7b9517daf79c78ab4 Author: Andrew Pinski Date: Fri Nov 1 23:20:22 2024 -0700 VN: Lookup `val != 0` if we got back val when looking up the predicate for GIMPLE_COND [PR117414] Som

[gcc r15-5013] Add LOOP_VINFO_DRS_ADVANCED_BY

https://gcc.gnu.org/g:2c25af0e52a631e46a1731594301e5e63bc28992 commit r15-5013-g2c25af0e52a631e46a1731594301e5e63bc28992 Author: Richard Biener Date: Mon Nov 4 13:09:21 2024 +0100 Add LOOP_VINFO_DRS_ADVANCED_BY The following remembers how we advanced DRs when vectorizing an ep

[gcc r15-5017] libgomp.texi: Document OpenMP's Interoperability Routines

https://gcc.gnu.org/g:e52cfd4bc23de14f1e1795bdf7ec161d94b8c087 commit r15-5017-ge52cfd4bc23de14f1e1795bdf7ec161d94b8c087 Author: Tobias Burnus Date: Thu Nov 7 16:13:06 2024 +0100 libgomp.texi: Document OpenMP's Interoperability Routines libgomp/ChangeLog: * libgom

[gcc r15-5026] bpf: avoid possible null deref in btf_ext_output [PR target/117447]

https://gcc.gnu.org/g:0e1382034246a594f1da8dbaee97c4a06743f31a commit r15-5026-g0e1382034246a594f1da8dbaee97c4a06743f31a Author: David Faust Date: Thu Nov 7 09:27:07 2024 -0800 bpf: avoid possible null deref in btf_ext_output [PR target/117447] The BPF-specific .BTF.ext section is

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement vector SAT_TRUNC for signed integer

https://gcc.gnu.org/g:e88115c93dc7b3cb2a805db3612bdcc3a66b5dcd commit e88115c93dc7b3cb2a805db3612bdcc3a66b5dcd Author: Pan Li Date: Mon Oct 14 10:14:31 2024 +0800 RISC-V: Implement vector SAT_TRUNC for signed integer This patch would like to implement the sstrunc for vector signed

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 2 of vector signed SAT_SUB

https://gcc.gnu.org/g:4ab025e6a1d8c4ed10d364c5563b5f3e440388ec commit 4ab025e6a1d8c4ed10d364c5563b5f3e440388ec Author: Pan Li Date: Sat Oct 12 09:13:54 2024 +0800 RISC-V: Add testcases for form 2 of vector signed SAT_SUB Form 2: #define DEF_VEC_SAT_S_SUB_FMT_2(T, UT, MIN, MA

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH] RISC-V: override alignment of function/jump/loop

https://gcc.gnu.org/g:d51adfe84ba03e9206479518b03f01246db39505 commit d51adfe84ba03e9206479518b03f01246db39505 Author: Wang Pengcheng Date: Wed Oct 23 23:11:53 2024 -0600 [PATCH] RISC-V: override alignment of function/jump/loop Just like what AArch64 has done. Signed-off-

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 4 of signed vector SAT_ADD

https://gcc.gnu.org/g:8cd0ebf8e1f184ccae8110ac274e5c893e84cfa4 commit 8cd0ebf8e1f184ccae8110ac274e5c893e84cfa4 Author: Pan Li Date: Mon Sep 23 13:43:50 2024 +0800 RISC-V: Add testcases for form 4 of signed vector SAT_ADD Form 4: #define DEF_VEC_SAT_S_ADD_FMT_4(T, UT, MIN, MA

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB form 1 with IMM = 1.

https://gcc.gnu.org/g:61532fbcc1679df99727353e9e0f40366ff43644 commit 61532fbcc1679df99727353e9e0f40366ff43644 Author: xuli Date: Mon Oct 21 04:10:14 2024 + RISC-V: Add testcases for unsigned .SAT_SUB form 1 with IMM = 1. form 1: T __attribute__((noinline)) \

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Adjust the gather-scatter testcases due to middle-end change

https://gcc.gnu.org/g:b5fe5d04d22ab11186542e2bbc86642eda87937f commit b5fe5d04d22ab11186542e2bbc86642eda87937f Author: Pan Li Date: Wed Oct 23 16:43:37 2024 +0800 RISC-V: Adjust the gather-scatter testcases due to middle-end change After we have MASK_LEN_STRIDED_LOAD{STORE} in the

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB form 1 with IMM = max -1.

https://gcc.gnu.org/g:023d03a21501da0621083c5487cb2aa7b503f627 commit 023d03a21501da0621083c5487cb2aa7b503f627 Author: xuli Date: Mon Oct 21 04:01:01 2024 + RISC-V: Add testcases for unsigned .SAT_SUB form 1 with IMM = max -1. form 1: T __attribute__((noinline))

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V:Bugfix for vlmul_ext and vlmul_trunc with NULL return value[pr117286]

https://gcc.gnu.org/g:43601fa23e1f4ea30469a25b75628655eb1cdac6 commit 43601fa23e1f4ea30469a25b75628655eb1cdac6 Author: xuli Date: Mon Oct 28 04:41:09 2024 + RISC-V:Bugfix for vlmul_ext and vlmul_trunc with NULL return value[pr117286] This patch fixes following ICE: te

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 1 of MASK_LEN_STRIDED_LOAD{STORE}

https://gcc.gnu.org/g:d8edb5cd745ffd9435d1651a6a5ae302c49fe633 commit d8edb5cd745ffd9435d1651a6a5ae302c49fe633 Author: Pan Li Date: Wed Oct 23 16:52:01 2024 +0800 RISC-V: Add testcases for form 1 of MASK_LEN_STRIDED_LOAD{STORE} Form 1: void __attribute__((noinline))

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [target/117316] Fix initializer for riscv code alignment handling

https://gcc.gnu.org/g:b07b227ad0ceade439f702356abe0a59a89b48d5 commit b07b227ad0ceade439f702356abe0a59a89b48d5 Author: Jeff Law Date: Mon Oct 28 05:39:24 2024 -0600 [target/117316] Fix initializer for riscv code alignment handling The construct used for initializing the code align

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH 1/2] RISC-V:Add intrinsic support for the CMOs extensions

https://gcc.gnu.org/g:eecb5e6ca11b2929bee236bcaeb561f3e232c47b commit eecb5e6ca11b2929bee236bcaeb561f3e232c47b Author: yulong Date: Tue Oct 29 08:43:42 2024 -0600 [PATCH 1/2] RISC-V:Add intrinsic support for the CMOs extensions gcc/ChangeLog: * config.gcc: Add ris

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: allow -fno-plt to disable PLT

https://gcc.gnu.org/g:f8cab2ae987facf17539e3b4e8a9e26bad49130e commit f8cab2ae987facf17539e3b4e8a9e26bad49130e Author: Yangyu Chen Date: Thu Oct 31 16:31:24 2024 +0800 RISC-V: allow -fno-plt to disable PLT Currently, the RISC-V target uses the target specific mplt option to co

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement the MASK_LEN_STRIDED_LOAD{STORE}

https://gcc.gnu.org/g:ecb0d1b860e15371248a055ae4b2d8058bb8dd1a commit ecb0d1b860e15371248a055ae4b2d8058bb8dd1a Author: Pan Li Date: Wed Oct 23 16:46:53 2024 +0800 RISC-V: Implement the MASK_LEN_STRIDED_LOAD{STORE} This patch would like to implment the MASK_LEN_STRIDED_LOAD{STORE}

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V] RISC-V: Add implication for M extension.

https://gcc.gnu.org/g:273865dac950d3f1c3be88bc9d79ac05701c1bc3 commit 273865dac950d3f1c3be88bc9d79ac05701c1bc3 Author: Tsung Chun Lin Date: Tue Oct 29 09:47:57 2024 -0600 [RISC-V] RISC-V: Add implication for M extension. That M implies Zmmul. gcc/ChangeLog:

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB form 2 with IMM = 1.

https://gcc.gnu.org/g:7c313c4bbea75040a5c7b8c06b5a79b36374633b commit 7c313c4bbea75040a5c7b8c06b5a79b36374633b Author: xuli Date: Wed Oct 23 01:57:51 2024 + RISC-V: Add testcases for unsigned .SAT_SUB form 2 with IMM = 1. form2: T __attribute__((noinline)) \

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: fix const interleaved stepped vector with a scalar pattern

https://gcc.gnu.org/g:b68a80eed8f0763f610ae67a07e12119bda3a7d7 commit b68a80eed8f0763f610ae67a07e12119bda3a7d7 Author: Vineet Gupta Date: Thu Oct 24 15:15:40 2024 -0700 RISC-V: fix const interleaved stepped vector with a scalar pattern When bisecting for ICE in PR/117353, commit 7

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH 2/2] RISC-V:Add intrinsic cases for the CMOs extensions

https://gcc.gnu.org/g:4dd46cea79099f885fb00ca4c3a8ec7b88358728 commit 4dd46cea79099f885fb00ca4c3a8ec7b88358728 Author: yulong Date: Tue Oct 29 08:44:45 2024 -0600 [PATCH 2/2] RISC-V:Add intrinsic cases for the CMOs extensions gcc/testsuite/ChangeLog: * gcc.target/

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Do not inline when callee is versioned but caller is not

https://gcc.gnu.org/g:3a533e006d9c81b0b26a95729647911f3c0c2113 commit 3a533e006d9c81b0b26a95729647911f3c0c2113 Author: Yangyu Chen Date: Thu Oct 24 15:12:45 2024 +0800 RISC-V: Do not inline when callee is versioned but caller is not When the callee is versioned but the caller is n

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH v2 1/2] RISC-V: Make vectorized memset handle more cases

https://gcc.gnu.org/g:7e5d9abbc0d4692df374c7aa46a5b13ea8826f30 commit 7e5d9abbc0d4692df374c7aa46a5b13ea8826f30 Author: Craig Blackmore Date: Mon Nov 4 13:55:19 2024 -0700 [PATCH v2 1/2] RISC-V: Make vectorized memset handle more cases `expand_vec_setmem` only generated vectorized

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH v2 2/2] RISC-V: Disable by pieces for vector setmem length > UNITS_PER_WORD

https://gcc.gnu.org/g:b4207141e5e1125f0d57d2a5d9e4fd8ae971b6a4 commit b4207141e5e1125f0d57d2a5d9e4fd8ae971b6a4 Author: Craig Blackmore Date: Mon Nov 4 13:57:20 2024 -0700 [PATCH v2 2/2] RISC-V: Disable by pieces for vector setmem length > UNITS_PER_WORD For fast unaligned access

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH v2] RISC-V: Fix gcc.target/riscv/rvv/base/cpymem-1.c f3

https://gcc.gnu.org/g:dda02bf87ee9770ee6c12f0bcc0bc9b70a664bb0 commit dda02bf87ee9770ee6c12f0bcc0bc9b70a664bb0 Author: Craig Blackmore Date: Thu Oct 31 09:12:10 2024 -0600 [PATCH v2] RISC-V: Fix gcc.target/riscv/rvv/base/cpymem-1.c f3 The function body checks for f3 only ran with

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Split riscv_process_target_attr with const char *args argument

https://gcc.gnu.org/g:6af6c65c19ea1801adbee1089c6f7af7730406c8 commit 6af6c65c19ea1801adbee1089c6f7af7730406c8 Author: Yangyu Chen Date: Thu Oct 24 15:10:57 2024 +0800 RISC-V: Split riscv_process_target_attr with const char *args argument This patch splits static bool riscv_proces

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V] Aggressively hoist VXRM assignments

https://gcc.gnu.org/g:e2274cdb525545acc30055e7a420ab0b3308d34c commit e2274cdb525545acc30055e7a420ab0b3308d34c Author: Jeff Law Date: Wed Oct 30 07:43:22 2024 -0600 [RISC-V] Aggressively hoist VXRM assignments So a while back I was looking at pixel_avg for RISC-V where we try to

[gcc r15-5030] libstdc++: Fix grammar in comment, again

https://gcc.gnu.org/g:c26e83918b58040ff735a61de5acb6b3b96c5ea3 commit r15-5030-gc26e83918b58040ff735a61de5acb6b3b96c5ea3 Author: Jonathan Wakely Date: Thu Nov 7 21:57:52 2024 + libstdc++: Fix grammar in comment, again libstdc++-v3/ChangeLog: * include/bits/has

[gcc r15-5031] libstdc++: Define __is_pair variable template for C++11

https://gcc.gnu.org/g:dd08cdccc36d084eda0e2748c772f6bf9a7f412f commit r15-5031-gdd08cdccc36d084eda0e2748c772f6bf9a7f412f Author: Jonathan Wakely Date: Fri Nov 1 10:09:55 2024 + libstdc++: Define __is_pair variable template for C++11 libstdc++-v3/ChangeLog: * i

[gcc r15-5032] libstdc++: Fix conversions to key/value types for hash table insertion [PR115285]

https://gcc.gnu.org/g:90c578654a2c96032aa6621449859243df5f641b commit r15-5032-g90c578654a2c96032aa6621449859243df5f641b Author: Jonathan Wakely Date: Tue Nov 5 17:19:06 2024 + libstdc++: Fix conversions to key/value types for hash table insertion [PR115285] The conversions t

[gcc r15-5033] libstdc++: Improve comment for _Hashtable::_M_insert_unique_node

https://gcc.gnu.org/g:e97179bacd067ccd3ee765632e0c034df152ccb6 commit r15-5033-ge97179bacd067ccd3ee765632e0c034df152ccb6 Author: Jonathan Wakely Date: Thu Nov 7 16:51:58 2024 + libstdc++: Improve comment for _Hashtable::_M_insert_unique_node Clarify the effects if rehashing is

[gcc r14-10897] aarch64: Add support for FUJITSU-MONAKA (-mcpu=fujitsu-monaka) CPU

https://gcc.gnu.org/g:6bcd3935f05056f1ed777882a70c247dc637cf6d commit r14-10897-g6bcd3935f05056f1ed777882a70c247dc637cf6d Author: Yuta Mukai Date: Thu Nov 7 22:09:39 2024 + aarch64: Add support for FUJITSU-MONAKA (-mcpu=fujitsu-monaka) CPU This patch adds initial support for F

[gcc r15-5016] Unify registered_pp_pragmas and registered_pragmas

https://gcc.gnu.org/g:06a725a6f77da0ac28d4ddf20bfb7f191363aa5f commit r15-5016-g06a725a6f77da0ac28d4ddf20bfb7f191363aa5f Author: Paul Iannetta Date: Wed Oct 30 11:21:09 2024 +0100 Unify registered_pp_pragmas and registered_pragmas Until now, the structures that keep pragma informa

[gcc r15-5028] aarch64: Make PSEL dependent on SME rather than SME2

https://gcc.gnu.org/g:afd3887262edbdd5d7be5f34658432fd3046a168 commit r15-5028-gafd3887262edbdd5d7be5f34658432fd3046a168 Author: Richard Sandiford Date: Thu Nov 7 20:34:49 2024 + aarch64: Make PSEL dependent on SME rather than SME2 The svpsel_lane intrinsics were wrongly class

[gcc r15-5027] aarch64: Restrict FCLAMP to SME2

https://gcc.gnu.org/g:f5962839d6e0c3115931e68d938d9a0cd7a383b1 commit r15-5027-gf5962839d6e0c3115931e68d938d9a0cd7a383b1 Author: Richard Sandiford Date: Thu Nov 7 20:34:48 2024 + aarch64: Restrict FCLAMP to SME2 There are two sets of patterns for FCLAMP: one set for single reg

[gcc r15-5029] aarch64: Fix gcc.target/aarch64/sme2/acle-asm/bfmlslb_f32.c

https://gcc.gnu.org/g:156f536d54b2f6f41de4719f9b3a8a33273a51a9 commit r15-5029-g156f536d54b2f6f41de4719f9b3a8a33273a51a9 Author: Richard Sandiford Date: Thu Nov 7 20:34:50 2024 + aarch64: Fix gcc.target/aarch64/sme2/acle-asm/bfmlslb_f32.c I missed a search-and-replace on this

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement scalar SAT_SUB for signed integer

https://gcc.gnu.org/g:15690407e1aadbdf8303a854c2f56e84e122c22e commit 15690407e1aadbdf8303a854c2f56e84e122c22e Author: Pan Li Date: Wed Sep 25 09:36:05 2024 +0800 RISC-V: Implement scalar SAT_SUB for signed integer This patch would like to implement the sssub form 1. Aka:

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V] Add splitters to restore condops generation after recent phiopt changes

https://gcc.gnu.org/g:0e45f9a77a54860cf026e2d41838fff66fe83d50 commit 0e45f9a77a54860cf026e2d41838fff66fe83d50 Author: Jeff Law Date: Mon Oct 7 11:49:21 2024 -0600 [RISC-V] Add splitters to restore condops generation after recent phiopt changes V2: Fix typo in ChangeLog.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 2 of scalar signed SAT_SUB

https://gcc.gnu.org/g:599aacb21f10585fe5d6c9101e02238fc648c426 commit 599aacb21f10585fe5d6c9101e02238fc648c426 Author: Pan Li Date: Thu Sep 26 20:21:10 2024 +0800 RISC-V: Add testcases for form 2 of scalar signed SAT_SUB Form 2: #define DEF_SAT_S_SUB_FMT_2(T, UT, MIN, MAX) \

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 1 of scalar signed SAT_SUB

https://gcc.gnu.org/g:9ef5ea5baba5d85a41fd5c272289936055cbf877 commit 9ef5ea5baba5d85a41fd5c272289936055cbf877 Author: Pan Li Date: Wed Sep 25 09:42:31 2024 +0800 RISC-V: Add testcases for form 1 of scalar signed SAT_SUB Form 1: #define DEF_SAT_S_SUB_FMT_1(T, UT, MIN, MAX) \

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 3 of scalar signed SAT_SUB

https://gcc.gnu.org/g:4598ef98bd41b9141e195e14ad3ce7e8063933cf commit 4598ef98bd41b9141e195e14ad3ce7e8063933cf Author: Pan Li Date: Thu Oct 3 16:15:56 2024 +0800 RISC-V: Add testcases for form 3 of scalar signed SAT_SUB Form 3: #define DEF_SAT_S_SUB_FMT_3(T, UT, MIN, MAX)

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add an implicit dependency for Zawrs

https://gcc.gnu.org/g:f3b7430f8db19df7acba09eb736b10de3291c283 commit f3b7430f8db19df7acba09eb736b10de3291c283 Author: Xiao Zeng Date: Fri Sep 27 17:30:36 2024 +0800 RISC-V: Add an implicit dependency for Zawrs There is a description in

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH] RISC-V/libgcc: Fix incorrect and missing .cfi_offset for __riscv_save_[0-3] on RV32.

https://gcc.gnu.org/g:3303b857418214599c0b47ed4413721bb822398b commit 3303b857418214599c0b47ed4413721bb822398b Author: Tsung Chun Lin Date: Tue Oct 1 09:10:29 2024 -0600 [PATCH] RISC-V/libgcc: Fix incorrect and missing .cfi_offset for __riscv_save_[0-3] on RV32. 0001-RISC-V-libgc

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH] RISC-V/libgcc: Fix incorrect .cfi_offset for saving ra in __riscv_save_[0-3] on ilp32e.

https://gcc.gnu.org/g:a04990658b179392b600a5a3798492a6f2e3875f commit a04990658b179392b600a5a3798492a6f2e3875f Author: Tsung Chun Lin Date: Fri Oct 4 08:02:07 2024 -0600 [PATCH] RISC-V/libgcc: Fix incorrect .cfi_offset for saving ra in __riscv_save_[0-3] on ilp32e. From 8b3c5ebe8

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add implication for M extension.

https://gcc.gnu.org/g:86e241cb8bdbc49ab348e7094b34320635b2b80d commit 86e241cb8bdbc49ab348e7094b34320635b2b80d Author: Tsung Chun Lin Date: Tue Oct 8 17:40:59 2024 -0600 RISC-V: Add implication for M extension. That M implies Zmmul. gcc/ChangeLog: * commo

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement TARGET_CAN_INLINE_P

https://gcc.gnu.org/g:6de223d810eac940c6375edd082d2c636d078e01 commit 6de223d810eac940c6375edd082d2c636d078e01 Author: Yangyu Chen Date: Tue Oct 8 11:08:44 2024 -0600 RISC-V: Implement TARGET_CAN_INLINE_P Currently, we lack support for TARGET_CAN_INLINE_P on the RISC-V ISA. As

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 4 of scalar signed SAT_SUB

https://gcc.gnu.org/g:b59748c176c0bb6fad863ff65d9ab54bddadc20b commit b59748c176c0bb6fad863ff65d9ab54bddadc20b Author: Pan Li Date: Thu Oct 3 16:47:52 2024 +0800 RISC-V: Add testcases for form 4 of scalar signed SAT_SUB Form 4: #define DEF_SAT_S_SUB_FMT_4(T, UT, MIN, MAX)

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Revert "RISC-V: Add implication for M extension."

https://gcc.gnu.org/g:a67ec8f344c43a807ccd0fb1d8d74a579942700c commit a67ec8f344c43a807ccd0fb1d8d74a579942700c Author: Jeff Law Date: Wed Oct 9 16:22:06 2024 -0600 Revert "RISC-V: Add implication for M extension." This reverts commit 0a193466f2e87acef9b86e0d086bc6f6017518b0.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 1 of scalar signed SAT_TRUNC

https://gcc.gnu.org/g:c268c7121cf51f5991a5900cee4aabc555e2440f commit c268c7121cf51f5991a5900cee4aabc555e2440f Author: Pan Li Date: Tue Oct 8 11:28:44 2024 +0800 RISC-V: Add testcases for form 1 of scalar signed SAT_TRUNC Form 1: #define DEF_SAT_S_TRUNC_FMT_1(WT, NT, NT_MIN,

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement scalar SAT_TRUNC for signed integer

https://gcc.gnu.org/g:cedd41718bb3c254fbdacfa0623840df3917b40d commit cedd41718bb3c254fbdacfa0623840df3917b40d Author: Pan Li Date: Tue Oct 8 11:22:21 2024 +0800 RISC-V: Implement scalar SAT_TRUNC for signed integer This patch would like to implement the sstrunc for scalar signed

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Optimize branches with shifted immediate operands

https://gcc.gnu.org/g:8c2010a09a3a63f908fcf999b3248343369185b9 commit 8c2010a09a3a63f908fcf999b3248343369185b9 Author: Jovan Vukic Date: Wed Oct 9 16:53:38 2024 -0600 RISC-V: Optimize branches with shifted immediate operands After the valuable feedback I received, it’s clear to me

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V][PR target/116615] RISC-V: Use default LOGICAL_OP_NON_SHORT_CIRCUIT

https://gcc.gnu.org/g:5f91c4a2e4dfdf5ded4655a2bbcc41b99780fe23 commit 5f91c4a2e4dfdf5ded4655a2bbcc41b99780fe23 Author: Palmer Dabbelt Date: Tue Oct 8 07:28:32 2024 -0600 [RISC-V][PR target/116615] RISC-V: Use default LOGICAL_OP_NON_SHORT_CIRCUIT > We have cheap logical ops, so let

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Enable builtin __riscv_mul with Zmmul extension.

https://gcc.gnu.org/g:771a4038fa5f57b37b8931bb739fe167dae2d7fb commit 771a4038fa5f57b37b8931bb739fe167dae2d7fb Author: Tsung Chun Lin Date: Tue Oct 8 17:44:38 2024 -0600 RISC-V: Enable builtin __riscv_mul with Zmmul extension. From d5b254e19d1f37fe27c7e98a0160e5c22446cfea Mon Sep

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Revert "RISC-V: Enable builtin __riscv_mul with Zmmul extension."

https://gcc.gnu.org/g:0d753781b949522fa740d8307d30b0f8795d867c commit 0d753781b949522fa740d8307d30b0f8795d867c Author: Jeff Law Date: Wed Oct 9 16:21:56 2024 -0600 Revert "RISC-V: Enable builtin __riscv_mul with Zmmul extension." This reverts commit 2990f5802a727cbd717587c3a345fa9

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 1 of vector signed SAT_SUB

https://gcc.gnu.org/g:86a667a882c82b97781673ceb8815e9c700fe56c commit 86a667a882c82b97781673ceb8815e9c700fe56c Author: Pan Li Date: Fri Oct 11 12:12:03 2024 +0800 RISC-V: Add testcases for form 1 of vector signed SAT_SUB Form 1: #define DEF_VEC_SAT_S_SUB_FMT_1(T, UT, MIN, MA

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 8 of scalar signed SAT_TRUNC

https://gcc.gnu.org/g:cbfde0fde6cdbd4c4dbf646873adad5a9ad3b45c commit cbfde0fde6cdbd4c4dbf646873adad5a9ad3b45c Author: Pan Li Date: Thu Oct 10 16:24:08 2024 +0800 RISC-V: Add testcases for form 8 of scalar signed SAT_TRUNC Form 8: #define DEF_SAT_S_TRUNC_FMT_8(NT, WT, NT_MIN

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V:Bugfix for C++ code compilation failure with rv32imafc_zve32f[pr116883]

https://gcc.gnu.org/g:39bd5c9d0383801bb7c5371b54e07a9e7196fc4d commit 39bd5c9d0383801bb7c5371b54e07a9e7196fc4d Author: Li Xu Date: Thu Oct 10 08:51:19 2024 -0600 RISC-V:Bugfix for C++ code compilation failure with rv32imafc_zve32f[pr116883] From: xuli Example as follows

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 2 of scalar signed SAT_TRUNC

https://gcc.gnu.org/g:95cd2154d39d6dc2134a00033e0ac553a1c99dd3 commit 95cd2154d39d6dc2134a00033e0ac553a1c99dd3 Author: Pan Li Date: Wed Oct 9 10:33:31 2024 +0800 RISC-V: Add testcases for form 2 of scalar signed SAT_TRUNC Form 2: #define DEF_SAT_S_TRUNC_FMT_2(NT, WT, NT_MIN,

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 3 of scalar signed SAT_TRUNC

https://gcc.gnu.org/g:f16d3f5e692668903b7e2e66a3046e043fb7 commit f16d3f5e692668903b7e2e66a3046e043fb7 Author: Pan Li Date: Wed Oct 9 22:37:00 2024 +0800 RISC-V: Add testcases for form 3 of scalar signed SAT_TRUNC Form 3: #define DEF_SAT_S_TRUNC_FMT_3(NT, WT, NT_MIN,

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 7 of scalar signed SAT_TRUNC

https://gcc.gnu.org/g:e459ef25692afcddd50fdabaa48949c267f44cb5 commit e459ef25692afcddd50fdabaa48949c267f44cb5 Author: Pan Li Date: Thu Oct 10 16:08:40 2024 +0800 RISC-V: Add testcases for form 7 of scalar signed SAT_TRUNC Form 7: #define DEF_SAT_S_TRUNC_FMT_7(NT, WT, NT_MIN

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 5 of scalar signed SAT_TRUNC

https://gcc.gnu.org/g:bda7ba63e0e170b201ab9d5539ce5b78e8854872 commit bda7ba63e0e170b201ab9d5539ce5b78e8854872 Author: Pan Li Date: Thu Oct 10 15:35:33 2024 +0800 RISC-V: Add testcases for form 5 of scalar signed SAT_TRUNC Form 5: #define DEF_SAT_S_TRUNC_FMT_5(NT, WT, NT_MIN

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 6 of scalar signed SAT_TRUNC

https://gcc.gnu.org/g:5a254091002952304a731a830932487eeaebd684 commit 5a254091002952304a731a830932487eeaebd684 Author: Pan Li Date: Thu Oct 10 15:53:45 2024 +0800 RISC-V: Add testcases for form 6 of scalar signed SAT_TRUNC Form 6: #define DEF_SAT_S_TRUNC_FMT_6(NT, WT, NT_MIN

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 4 of scalar signed SAT_TRUNC

https://gcc.gnu.org/g:b5d3b4d45b106110cc184748c3fba01f2a463d71 commit b5d3b4d45b106110cc184748c3fba01f2a463d71 Author: Pan Li Date: Thu Oct 10 14:52:04 2024 +0800 RISC-V: Add testcases for form 4 of scalar signed SAT_TRUNC Form 4: #define DEF_SAT_S_TRUNC_FMT_4(NT, WT, NT_MIN

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V] Slightly improve broadcasting small constants into vectors

https://gcc.gnu.org/g:4b3f2e950eb7f71b8445d2d268a2b73428be2ed5 commit 4b3f2e950eb7f71b8445d2d268a2b73428be2ed5 Author: Jeff Law Date: Sat Oct 12 07:12:53 2024 -0600 RISC-V] Slightly improve broadcasting small constants into vectors I probably spent way more time on this than it's

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add detailed comments on processing implied extensions. [NFC]

https://gcc.gnu.org/g:d273fb1fff879b75b9534c1d51a2c0d9897a9825 commit d273fb1fff879b75b9534c1d51a2c0d9897a9825 Author: Yangyu Chen Date: Mon Oct 14 18:31:06 2024 +0800 RISC-V: Add detailed comments on processing implied extensions. [NFC] In some cases, we don't need to handle impl

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix UNRESOLVED testcases for SAT alu vector mode

https://gcc.gnu.org/g:8bae04250642e76adb4c69fac5ca52263c189984 commit 8bae04250642e76adb4c69fac5ca52263c189984 Author: Pan Li Date: Tue Oct 15 09:19:44 2024 +0800 RISC-V: Fix UNRESOLVED testcases for SAT alu vector mode Some saturation related alu testcases missed additional optio

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 3 of vector signed SAT_SUB

https://gcc.gnu.org/g:d92cec88f320dfc954d9c78497c214f62ad1e25d commit d92cec88f320dfc954d9c78497c214f62ad1e25d Author: Pan Li Date: Sat Oct 12 10:40:30 2024 +0800 RISC-V: Add testcases for form 3 of vector signed SAT_SUB Form 3: #define DEF_VEC_SAT_S_SUB_FMT_3(T, UT, MIN, MA

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement __init_riscv_feature_bits, __riscv_feature_bits, and __riscv_vendor_feature_bits

https://gcc.gnu.org/g:b24a3bda663750278e690f5e3f2d50d31ca16ba4 commit b24a3bda663750278e690f5e3f2d50d31ca16ba4 Author: Kito Cheng Date: Mon Oct 14 16:07:16 2024 +0800 RISC-V: Implement __init_riscv_feature_bits, __riscv_feature_bits, and __riscv_vendor_feature_bits This provides

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Use biggest_mode as mode for constants.

https://gcc.gnu.org/g:8e28c8822d2985445de528b0f134a92239210fc4 commit 8e28c8822d2985445de528b0f134a92239210fc4 Author: Robin Dapp Date: Tue Oct 15 12:10:48 2024 +0200 RISC-V: Use biggest_mode as mode for constants. In compute_nregs_for_mode we expect that the current variable's mo

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V] Avoid unnecessary extensions when value is already extended

https://gcc.gnu.org/g:ed2e094882fe423f929053e362fcb9485427d34c commit ed2e094882fe423f929053e362fcb9485427d34c Author: Jivan Hakobyan Date: Sat Oct 12 19:10:50 2024 -0600 [RISC-V] Avoid unnecessary extensions when value is already extended This is a minor patch from Jivan from rou

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 4 of vector signed SAT_SUB

https://gcc.gnu.org/g:ea35428b52483a61ced69af27bb3e49a657cf8e2 commit ea35428b52483a61ced69af27bb3e49a657cf8e2 Author: Pan Li Date: Sat Oct 12 11:08:21 2024 +0800 RISC-V: Add testcases for form 4 of vector signed SAT_SUB Form 4: #define DEF_VEC_SAT_S_SUB_FMT_4(T, UT, MIN, MA

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH 2/7] RISC-V: Fix uninitialized reg in memcpy

https://gcc.gnu.org/g:e348a878cb7b60e13c06ed526aa32265f8fdd978 commit e348a878cb7b60e13c06ed526aa32265f8fdd978 Author: Craig Blackmore Date: Fri Oct 18 09:06:58 2024 -0600 [PATCH 2/7] RISC-V: Fix uninitialized reg in memcpy gcc/ChangeLog: * config/riscv/riscv-stri

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH 1/7] RISC-V: Fix indentation in riscv_vector::expand_block_move [NFC]

https://gcc.gnu.org/g:ee4d8b5e9ccfc3363ce769f9c2b51dbe927de50f commit ee4d8b5e9ccfc3363ce769f9c2b51dbe927de50f Author: Craig Blackmore Date: Fri Oct 18 09:01:35 2024 -0600 [PATCH 1/7] RISC-V: Fix indentation in riscv_vector::expand_block_move [NFC] gcc/ChangeLog:

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement vector SAT_SUB for signed integer

https://gcc.gnu.org/g:eb052e6234e110b857d895f1c004baa924bb9cc4 commit eb052e6234e110b857d895f1c004baa924bb9cc4 Author: Pan Li Date: Fri Oct 11 12:05:10 2024 +0800 RISC-V: Implement vector SAT_SUB for signed integer This patch would like to implement the sssub for vector signed int

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 1 of vector signed SAT_TRUNC

https://gcc.gnu.org/g:2c2eb88266adde345ccc7efe51481e03f0a0046c commit 2c2eb88266adde345ccc7efe51481e03f0a0046c Author: Pan Li Date: Mon Oct 14 10:21:39 2024 +0800 RISC-V: Add testcases for form 1 of vector signed SAT_TRUNC Form 1: #define DEF_VEC_SAT_S_TRUNC_FMT_1(NT, WT, NT

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 4 of vector signed SAT_TRUNC

https://gcc.gnu.org/g:e6f47b02d26e982e5b47105432106c151f46 commit e6f47b02d26e982e5b47105432106c151f46 Author: Pan Li Date: Mon Oct 14 11:41:02 2024 +0800 RISC-V: Add testcases for form 4 of vector signed SAT_TRUNC Form 4: #define DEF_VEC_SAT_S_TRUNC_FMT_4(NT, WT, NT

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH 4/7] RISC-V: Honour -mrvv-max-lmul in riscv_vector::expand_block_move

https://gcc.gnu.org/g:09eddbb34a38357aab6d3186c830ec7babdf6750 commit 09eddbb34a38357aab6d3186c830ec7babdf6750 Author: Craig Blackmore Date: Sat Oct 19 06:57:06 2024 -0600 [PATCH 4/7] RISC-V: Honour -mrvv-max-lmul in riscv_vector::expand_block_move Unlike the other vector string o

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH 5/7] RISC-V: Move vector memcpy decision making to separate function [NFC]

https://gcc.gnu.org/g:95dd943483b5f42071e12ddf8c3385f196dfb899 commit 95dd943483b5f42071e12ddf8c3385f196dfb899 Author: Craig Blackmore Date: Sat Oct 19 07:00:47 2024 -0600 [PATCH 5/7] RISC-V: Move vector memcpy decision making to separate function [NFC] This moves the code for de

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH][v5] RISC-V: add option -m(no-)autovec-segment

https://gcc.gnu.org/g:a514689ebcb85872987e407f253b373335bc0148 commit a514689ebcb85872987e407f253b373335bc0148 Author: Greg McGary Date: Sat Oct 19 08:21:56 2024 -0600 [PATCH][v5] RISC-V: add option -m(no-)autovec-segment Add option -m(no-)autovec-segment to enable/disable autovec

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH 7/7] RISC-V: Disable by pieces for vector setmem length > UNITS_PER_WORD

https://gcc.gnu.org/g:f2009b5cb0d0c18e19c0e2badfea5777fb7cbcae commit f2009b5cb0d0c18e19c0e2badfea5777fb7cbcae Author: Craig Blackmore Date: Sat Oct 19 07:08:31 2024 -0600 [PATCH 7/7] RISC-V: Disable by pieces for vector setmem length > UNITS_PER_WORD For fast unaligned access ta

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 2 of vector signed SAT_TRUNC

https://gcc.gnu.org/g:591f45227fd6ecb6c6401bb6da9ff25921934ea9 commit 591f45227fd6ecb6c6401bb6da9ff25921934ea9 Author: Pan Li Date: Mon Oct 14 11:09:55 2024 +0800 RISC-V: Add testcases for form 2 of vector signed SAT_TRUNC Form 2: #define DEF_VEC_SAT_S_TRUNC_FMT_2(NT, WT, NT

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 3 of vector signed SAT_TRUNC

https://gcc.gnu.org/g:db978aea92ebddbcb21ae28d2b86c003e45eeff4 commit db978aea92ebddbcb21ae28d2b86c003e45eeff4 Author: Pan Li Date: Mon Oct 14 11:26:06 2024 +0800 RISC-V: Add testcases for form 3 of vector signed SAT_TRUNC Form 3: #define DEF_VEC_SAT_S_TRUNC_FMT_3(NT, WT, NT

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH 3/7] RISC-V: Fix vector memcpy smaller LMUL generation

https://gcc.gnu.org/g:b0158d651af43932755e4c5799df58771d6e5c06 commit b0158d651af43932755e4c5799df58771d6e5c06 Author: Craig Blackmore Date: Fri Oct 18 09:17:21 2024 -0600 [PATCH 3/7] RISC-V: Fix vector memcpy smaller LMUL generation If riscv_vector::expand_block_move is generatin

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Revert "[PATCH 7/7] RISC-V: Disable by pieces for vector setmem length > UNITS_PER_WORD"

https://gcc.gnu.org/g:44ae4bc2958543c5bc14e1d9157550c8255832da commit 44ae4bc2958543c5bc14e1d9157550c8255832da Author: Jeff Law Date: Sun Oct 20 10:35:18 2024 -0600 Revert "[PATCH 7/7] RISC-V: Disable by pieces for vector setmem length > UNITS_PER_WORD" This reverts commit 72cedd

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed][PR rtl-optimization/116488] Fix SIGN_EXTEND source handling in ext-dce

https://gcc.gnu.org/g:7841513ff437829304619a750a550a41d6918cc4 commit 7841513ff437829304619a750a550a41d6918cc4 Author: Jeff Law Date: Mon Oct 21 13:37:21 2024 -0600 [committed][PR rtl-optimization/116488] Fix SIGN_EXTEND source handling in ext-dce A while back I noticed that the

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 7 of vector signed SAT_TRUNC

https://gcc.gnu.org/g:efc3b1248f054bd3d3326598561991b66371a25f commit efc3b1248f054bd3d3326598561991b66371a25f Author: Pan Li Date: Mon Oct 14 15:10:46 2024 +0800 RISC-V: Add testcases for form 7 of vector signed SAT_TRUNC Form 7: #define DEF_VEC_SAT_S_TRUNC_FMT_7(NT, WT, NT

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 8 of vector signed SAT_TRUNC

https://gcc.gnu.org/g:8a28d75bf29166a2d73490242c3bb75ed5522548 commit 8a28d75bf29166a2d73490242c3bb75ed5522548 Author: Pan Li Date: Mon Oct 14 15:23:57 2024 +0800 RISC-V: Add testcases for form 8 of vector signed SAT_TRUNC Form 8: #define DEF_VEC_SAT_S_TRUNC_FMT_8(NT, WT, NT

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 5 of vector signed SAT_TRUNC

https://gcc.gnu.org/g:cbadd73662a924befd0ff614f09d0bf75d8c3bac commit cbadd73662a924befd0ff614f09d0bf75d8c3bac Author: Pan Li Date: Mon Oct 14 14:41:22 2024 +0800 RISC-V: Add testcases for form 5 of vector signed SAT_TRUNC Form 5: #define DEF_VEC_SAT_S_TRUNC_FMT_5(NT, WT, NT

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 6 of vector signed SAT_TRUNC

https://gcc.gnu.org/g:85a44e56370ad5bfe742e3ae5b406c81b5d02fb6 commit 85a44e56370ad5bfe742e3ae5b406c81b5d02fb6 Author: Pan Li Date: Mon Oct 14 14:55:56 2024 +0800 RISC-V: Add testcases for form 6 of vector signed SAT_TRUNC Form 6: #define DEF_VEC_SAT_S_TRUNC_FMT_6(NT, WT, NT

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Partial cherry-pick (just risc-v bits) of:

https://gcc.gnu.org/g:2bd87a408fbf6c2d04db3d228c07cdc1cfbfc1f1 commit 2bd87a408fbf6c2d04db3d228c07cdc1cfbfc1f1 Author: Jakub Jelinek Date: Thu Nov 7 13:49:10 2024 -0700 Partial cherry-pick (just risc-v bits) of: commit e48a65d3b3fcbcf6059df247d9c87a9a19b35861 Author: Jakub Jel

[gcc r15-5008] rtl-optimization/117467 - 33% compile-time in rest of compilation

https://gcc.gnu.org/g:7a07de2c60b3c513b6aef206e9b55b3ffefe8b39 commit r15-5008-g7a07de2c60b3c513b6aef206e9b55b3ffefe8b39 Author: Richard Biener Date: Thu Nov 7 09:23:03 2024 +0100 rtl-optimization/117467 - 33% compile-time in rest of compilation ext-dce uses TV_NONE, that's not OK

[gcc r15-5011] testsuite: Fix up pr116725.c test [PR116725]

https://gcc.gnu.org/g:0dadf022de293c202ab21b0aeed7c9a4511f57d5 commit r15-5011-g0dadf022de293c202ab21b0aeed7c9a4511f57d5 Author: Jakub Jelinek Date: Thu Nov 7 13:20:20 2024 +0100 testsuite: Fix up pr116725.c test [PR116725] On Fri, Oct 18, 2024 at 02:05:59PM -0400, Antoni Boucher

[gcc r15-5018] libstdc++: Fix typo in comment in hashtable.h

https://gcc.gnu.org/g:bcf40c70f8b0fbc54ec14adea31f274e1791b1ed commit r15-5018-gbcf40c70f8b0fbc54ec14adea31f274e1791b1ed Author: Jonathan Wakely Date: Tue Nov 5 23:55:08 2024 + libstdc++: Fix typo in comment in hashtable.h And tweak grammar in a couple of comments. li

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