[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add an implicit dependency for Zawrs

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:f3b7430f8db19df7acba09eb736b10de3291c283

commit f3b7430f8db19df7acba09eb736b10de3291c283
Author: Xiao Zeng <zengx...@eswincomputing.com>
Date:   Fri Sep 27 17:30:36 2024 +0800

    RISC-V: Add an implicit dependency for Zawrs
    
    There is a description in 
<https://github.com/riscv/riscv-isa-manual/blob/main/src/zawrs.adoc>:
    
    "The instructions in the Zawrs extension are only useful in conjunction
    with the LR instruction, which is provided by the Zalrsc component
    of the A extension."
    
    It can be concluded that: zawrs -> zalrsc.
    
    gcc/ChangeLog:
    
            * common/config/riscv/riscv-common.cc: zawrs -> zalrsc.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/predef-38.c: New test.
            * gcc.target/riscv/predef-39.c: New test.
    
    Signed-off-by: Xiao Zeng <zengx...@eswincomputing.com>
    (cherry picked from commit c01e3aaae79ecd439ad35063db3dee9775f3aefa)

Diff:
---
 gcc/common/config/riscv/riscv-common.cc    |  1 +
 gcc/testsuite/gcc.target/riscv/predef-38.c | 31 ++++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/predef-39.c | 31 ++++++++++++++++++++++++++++++
 3 files changed, 63 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index bd42fd01532b..a6abd903b98f 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -96,6 +96,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
 
   {"zabha", "zaamo"},
   {"zacas", "zaamo"},
+  {"zawrs", "zalrsc"},
 
   {"zcmop", "zca"},
 
diff --git a/gcc/testsuite/gcc.target/riscv/predef-38.c 
b/gcc/testsuite/gcc.target/riscv/predef-38.c
new file mode 100644
index 000000000000..986c02b451a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-38.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32i_zawrs -mabi=ilp32 -mcmodel=medlow 
-misa-spec=20191213" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 32
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i)
+#error "__riscv_i"
+#endif
+
+#if !defined(__riscv_zawrs)
+#error "__riscv_zawrs"
+#endif
+
+#if !defined(__riscv_zalrsc)
+#error "__riscv_zalrsc"
+#endif
+
+#if defined(__riscv_a)
+#error "__riscv_a"
+#endif
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-39.c 
b/gcc/testsuite/gcc.target/riscv/predef-39.c
new file mode 100644
index 000000000000..558164de8c44
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-39.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64i_zawrs -mabi=lp64 -mcmodel=medlow 
-misa-spec=20191213" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i)
+#error "__riscv_i"
+#endif
+
+#if !defined(__riscv_zawrs)
+#error "__riscv_zawrs"
+#endif
+
+#if !defined(__riscv_zalrsc)
+#error "__riscv_zalrsc"
+#endif
+
+#if defined(__riscv_a)
+#error "__riscv_a"
+#endif
+
+  return 0;
+}