[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Partial cherry-pick (just risc-v bits) of:

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:2bd87a408fbf6c2d04db3d228c07cdc1cfbfc1f1

commit 2bd87a408fbf6c2d04db3d228c07cdc1cfbfc1f1
Author: Jakub Jelinek <ja...@redhat.com>
Date:   Thu Nov 7 13:49:10 2024 -0700

    Partial cherry-pick (just risc-v bits) of:
    
    commit e48a65d3b3fcbcf6059df247d9c87a9a19b35861
    Author: Jakub Jelinek <ja...@redhat.com>
    Date:   Wed Oct 16 14:44:32 2024 +0200
    
        Ternary operator formatting fixes

Diff:
---
 gcc/config/riscv/riscv.cc | 4 ++--
 gcc/config/riscv/zc.md    | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 2f7250a0cf60..5b9d9b6b64be 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -6621,8 +6621,8 @@ riscv_union_memmodels (enum memmodel model1, enum 
memmodel model2)
   model1 = memmodel_base (model1);
   model2 = memmodel_base (model2);
 
-  enum memmodel weaker = model1 <= model2 ? model1: model2;
-  enum memmodel stronger = model1 > model2 ? model1: model2;
+  enum memmodel weaker = model1 <= model2 ? model1 : model2;
+  enum memmodel stronger = model1 > model2 ? model1 : model2;
 
   switch (stronger)
     {
diff --git a/gcc/config/riscv/zc.md b/gcc/config/riscv/zc.md
index 5b948b41586f..6dc47da3acc9 100644
--- a/gcc/config/riscv/zc.md
+++ b/gcc/config/riscv/zc.md
@@ -1442,7 +1442,7 @@
         (match_operand:X 3 "zcmp_mv_sreg_operand" "r"))]
   "TARGET_ZCMP
    && (REGNO (operands[2]) != REGNO (operands[0]))"
-  { return (REGNO (operands[0]) == 
A0_REGNUM)?"cm.mva01s\t%1,%3":"cm.mva01s\t%3,%1"; }
+  { return (REGNO (operands[0]) == A0_REGNUM) ? "cm.mva01s\t%1,%3" : 
"cm.mva01s\t%3,%1"; }
   [(set_attr "mode" "<X:MODE>")
    (set_attr "type" "mvpair")])
 
@@ -1454,6 +1454,6 @@
   "TARGET_ZCMP
    && (REGNO (operands[0]) != REGNO (operands[2]))
    && (REGNO (operands[1]) != REGNO (operands[3]))"
-  { return (REGNO (operands[1]) == 
A0_REGNUM)?"cm.mvsa01\t%0,%2":"cm.mvsa01\t%2,%0"; }
+  { return (REGNO (operands[1]) == A0_REGNUM) ? "cm.mvsa01\t%0,%2" : 
"cm.mvsa01\t%2,%0"; }
   [(set_attr "mode" "<X:MODE>")
    (set_attr "type" "mvpair")])