gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB form 2 with IMM = 1.

Jeff Law via Gcc-cvs Thu, 07 Nov 2024 13:07:00 -0800

https://gcc.gnu.org/g:7c313c4bbea75040a5c7b8c06b5a79b36374633b


commit 7c313c4bbea75040a5c7b8c06b5a79b36374633b
Author: xuli <xu...@eswincomputing.com>
Date:   Wed Oct 23 01:57:51 2024 +0000

    RISC-V: Add testcases for unsigned .SAT_SUB form 2 with IMM = 1.
    
    form2:
    T __attribute__((noinline))             \
    sat_u_sub_imm##IMM##_##T##_fmt_2 (T x)  \
    {                                       \
      return x >= (T)IMM ? x - (T)IMM : 0;  \
    }
    
    Passed the rv64gcv regression test.
    
    Signed-off-by: Li Xu <xu...@eswincomputing.com>
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/sat_u_sub_imm-run-5.c: add run case for imm=1.
            * gcc.target/riscv/sat_u_sub_imm-run-6.c: Ditto.
            * gcc.target/riscv/sat_u_sub_imm-run-7.c: Ditto.
            * gcc.target/riscv/sat_u_sub_imm-run-8.c: Ditto.
            * gcc.target/riscv/sat_u_sub_imm-5_3.c: New test.
            * gcc.target/riscv/sat_u_sub_imm-6_3.c: New test.
            * gcc.target/riscv/sat_u_sub_imm-7_3.c: New test.
            * gcc.target/riscv/sat_u_sub_imm-8_1.c: New test.
    
    (cherry picked from commit 179a682d047500604c6612afb425acf481e1a6b2)

Diff:
---
 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-5_3.c   | 18 ++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-6_3.c   | 19 +++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7_3.c   | 17 +++++++++++++++++
 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-8_1.c   | 17 +++++++++++++++++
 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-5.c |  1 +
 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-6.c |  1 +
 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-7.c |  1 +
 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-8.c |  1 +
 8 files changed, 75 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-5_3.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-5_3.c
new file mode 100644
index 000000000000..42edfc59f8aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-5_3.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-skip-if  "" { *-*-* } { "-flto" } } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm1_uint8_t_fmt_2:
+** snez\s+[atx][0-9]+,\s*a0
+** subw\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 1)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_SUB" "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-6_3.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-6_3.c
new file mode 100644
index 000000000000..5250b90418aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-6_3.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-skip-if  "" { *-*-* } { "-flto" } } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm1_uint16_t_fmt_2:
+** snez\s+[atx][0-9]+,\s*a0
+** subw\s+a0,\s*a0,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 1)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_SUB" "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7_3.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7_3.c
new file mode 100644
index 000000000000..99df0e4b683b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7_3.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-skip-if  "" { *-*-* } { "-flto" } } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm1_uint32_t_fmt_2:
+** snez\s+[atx][0-9]+,\s*a0
+** subw\s+a0,\s*a0,\s*[atx][0-9]+
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 1)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_SUB" "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-8_1.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-8_1.c
new file mode 100644
index 000000000000..cbbc08339f4d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-8_1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-skip-if  "" { *-*-* } { "-flto" } } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm1_uint64_t_fmt_2:
+** snez\s+[atx][0-9]+,\s*a0
+** sub\s+a0,\s*a0,\s*[atx][0-9]+
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 1)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_SUB" "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-5.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-5.c
index 627e81bca4bd..fc3809590dee 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-5.c
@@ -4,6 +4,7 @@
 #include "sat_arith.h"
 
 DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 0)
+DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 1)
 DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 2)
 DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 6)
 DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 129)
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-6.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-6.c
index 8deed2bf28f6..0f4f9e40f1f4 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-6.c
@@ -4,6 +4,7 @@
 #include "sat_arith.h"
 
 DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 0)
+DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 1)
 DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 2)
 DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 6)
 DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 32767)
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-7.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-7.c
index 7a3d7b0176fb..ea15d85782d2 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-7.c
@@ -4,6 +4,7 @@
 #include "sat_arith.h"
 
 DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 0)
+DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 1)
 DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 2)
 DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 6)
 DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 2147483647)
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-8.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-8.c
index 3ed1c90f78f7..612da9212cd4 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-8.c
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-8.c
@@ -4,6 +4,7 @@
 #include "sat_arith.h"
 
 DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 0)
+DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 1)
 DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 2)
 DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 6)
 DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 18446744073709551614u)

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB form 2 with IMM = 1.

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