https://gcc.gnu.org/g:4ab025e6a1d8c4ed10d364c5563b5f3e440388ec
commit 4ab025e6a1d8c4ed10d364c5563b5f3e440388ec
Author: Pan Li <pan2...@intel.com>
Date: Sat Oct 12 09:13:54 2024 +0800
RISC-V: Add testcases for form 2 of vector signed SAT_SUB
Form 2:
#define DEF_VEC_SAT_S_SUB_FMT_2(T, UT, MIN, MAX) \
void __attribute__((noinline)) \
vec_sat_s_sub_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
T minus = (UT)x - (UT)y; \
out[i] = (x ^ y) >= 0 || (minus ^ x) >= 0 \
? minus : x < 0 ? MIN : MAX; \
} \
}
DEF_VEC_SAT_S_SUB_FMT_2(int8_t, uint8_t, INT8_MIN, INT8_MAX)
The below test are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper
macros.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i16.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i32.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i64.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i8.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-2-i16.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-2-i32.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-2-i64.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-2-i8.c: New
test.
Signed-off-by: Pan Li <pan2...@intel.com>
(cherry picked from commit 72d24d2a130a54fbe1479cb85e5639a7eab6c971)
Diff:
---
.../riscv/rvv/autovec/binop/vec_sat_s_sub-2-i16.c | 9 +++++++++
.../riscv/rvv/autovec/binop/vec_sat_s_sub-2-i32.c | 9 +++++++++
.../riscv/rvv/autovec/binop/vec_sat_s_sub-2-i64.c | 9 +++++++++
.../riscv/rvv/autovec/binop/vec_sat_s_sub-2-i8.c | 9 +++++++++
.../rvv/autovec/binop/vec_sat_s_sub-run-2-i16.c | 17 +++++++++++++++++
.../rvv/autovec/binop/vec_sat_s_sub-run-2-i32.c | 17 +++++++++++++++++
.../rvv/autovec/binop/vec_sat_s_sub-run-2-i64.c | 17 +++++++++++++++++
.../rvv/autovec/binop/vec_sat_s_sub-run-2-i8.c | 17 +++++++++++++++++
.../gcc.target/riscv/rvv/autovec/vec_sat_arith.h | 22 ++++++++++++++++++++++
9 files changed, 126 insertions(+)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i16.c
new file mode 100644
index 000000000000..dec0359c5ed9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i16.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_SUB_FMT_2(int16_t, uint16_t, INT16_MIN, INT16_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i32.c
new file mode 100644
index 000000000000..72b2d6778cca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i32.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_SUB_FMT_2(int32_t, uint32_t, INT32_MIN, INT32_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i64.c
new file mode 100644
index 000000000000..3ca44589e427
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i64.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_SUB_FMT_2(int64_t, uint64_t, INT64_MIN, INT64_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i8.c
new file mode 100644
index 000000000000..e3a7bfcf161c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-2-i8.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_SUB_FMT_2(int8_t, uint8_t, INT8_MIN, INT8_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-2-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-2-i16.c
new file mode 100644
index 000000000000..89cd45036d1a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-2-i16.c
@@ -0,0 +1,17 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T int16_t
+#define T1 int16_t
+#define T2 uint16_t
+
+DEF_VEC_SAT_S_SUB_FMT_2_WRAP (T1, T2, INT16_MIN, INT16_MAX)
+
+#define test_data TEST_BINARY_DATA_NAME_WRAP(T, T, sssub)
+#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \
+ RUN_VEC_SAT_S_SUB_FMT_2_WRAP(T, out, op_1, op_2, N)
+
+#include "vec_sat_binary_vvv_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-2-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-2-i32.c
new file mode 100644
index 000000000000..aa91300111a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-2-i32.c
@@ -0,0 +1,17 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T int32_t
+#define T1 int32_t
+#define T2 uint32_t
+
+DEF_VEC_SAT_S_SUB_FMT_2_WRAP (T1, T2, INT32_MIN, INT32_MAX)
+
+#define test_data TEST_BINARY_DATA_NAME_WRAP(T, T, sssub)
+#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \
+ RUN_VEC_SAT_S_SUB_FMT_2_WRAP(T, out, op_1, op_2, N)
+
+#include "vec_sat_binary_vvv_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-2-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-2-i64.c
new file mode 100644
index 000000000000..061070302323
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-2-i64.c
@@ -0,0 +1,17 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T int64_t
+#define T1 int64_t
+#define T2 uint64_t
+
+DEF_VEC_SAT_S_SUB_FMT_2_WRAP (T1, T2, INT64_MIN, INT64_MAX)
+
+#define test_data TEST_BINARY_DATA_NAME_WRAP(T, T, sssub)
+#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \
+ RUN_VEC_SAT_S_SUB_FMT_2_WRAP(T, out, op_1, op_2, N)
+
+#include "vec_sat_binary_vvv_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-2-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-2-i8.c
new file mode 100644
index 000000000000..3b2a24d321e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_sub-run-2-i8.c
@@ -0,0 +1,17 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T int8_t
+#define T1 int8_t
+#define T2 uint8_t
+
+DEF_VEC_SAT_S_SUB_FMT_2_WRAP (T1, T2, INT8_MIN, INT8_MAX)
+
+#define test_data TEST_BINARY_DATA_NAME_WRAP(T, T, sssub)
+#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \
+ RUN_VEC_SAT_S_SUB_FMT_2_WRAP(T, out, op_1, op_2, N)
+
+#include "vec_sat_binary_vvv_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
index a2caf335c0b2..93deceec1a24 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
@@ -466,6 +466,23 @@ vec_sat_s_sub_##T##_fmt_1 (T *out, T *op_1, T *op_2,
unsigned limit) \
#define DEF_VEC_SAT_S_SUB_FMT_1_WRAP(T, UT, MIN, MAX) \
DEF_VEC_SAT_S_SUB_FMT_1(T, UT, MIN, MAX)
+#define DEF_VEC_SAT_S_SUB_FMT_2(T, UT, MIN, MAX) \
+void __attribute__((noinline)) \
+vec_sat_s_sub_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \
+{ \
+ unsigned i; \
+ for (i = 0; i < limit; i++) \
+ { \
+ T x = op_1[i]; \
+ T y = op_2[i]; \
+ T minus = (UT)x - (UT)y; \
+ out[i] = (x ^ y) >= 0 || (minus ^ x) >= 0 \
+ ? minus : x < 0 ? MIN : MAX; \
+ } \
+}
+#define DEF_VEC_SAT_S_SUB_FMT_2_WRAP(T, UT, MIN, MAX) \
+ DEF_VEC_SAT_S_SUB_FMT_2(T, UT, MIN, MAX)
+
#define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \
vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N)
@@ -506,6 +523,11 @@ vec_sat_s_sub_##T##_fmt_1 (T *out, T *op_1, T *op_2,
unsigned limit) \
#define RUN_VEC_SAT_S_SUB_FMT_1_WRAP(T, out, op_1, op_2, N) \
RUN_VEC_SAT_S_SUB_FMT_1(T, out, op_1, op_2, N)
+#define RUN_VEC_SAT_S_SUB_FMT_2(T, out, op_1, op_2, N) \
+ vec_sat_s_sub_##T##_fmt_2(out, op_1, op_2, N)
+#define RUN_VEC_SAT_S_SUB_FMT_2_WRAP(T, out, op_1, op_2, N) \
+ RUN_VEC_SAT_S_SUB_FMT_2(T, out, op_1, op_2, N)
+
/******************************************************************************/
/* Saturation Sub Truncated (Unsigned and Signed)
*/
/******************************************************************************/
