https://gcc.gnu.org/g:85a44e56370ad5bfe742e3ae5b406c81b5d02fb6
commit 85a44e56370ad5bfe742e3ae5b406c81b5d02fb6
Author: Pan Li <pan2...@intel.com>
Date: Mon Oct 14 14:55:56 2024 +0800
RISC-V: Add testcases for form 6 of vector signed SAT_TRUNC
Form 6:
#define DEF_VEC_SAT_S_TRUNC_FMT_6(NT, WT, NT_MIN, NT_MAX) \
void __attribute__((noinline)) \
vec_sat_s_trunc_##NT##_##WT##_fmt_6 (NT *out, WT *in, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
WT x = in[i]; \
NT trunc = (NT)x; \
out[i] = (WT)NT_MIN >= x || x > (WT)NT_MAX \
? x < 0 ? NT_MIN : NT_MAX \
j: trunc; \
} \
}
The below test are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper
macros.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i16-to-i8.c:
New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i32-to-i16.c:
New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i32-to-i8.c:
New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i16.c:
New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i32.c:
New test.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i8.c:
New test.
*
gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i16-to-i8.c: New test.
*
gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i32-to-i16.c: New test.
*
gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i32-to-i8.c: New test.
*
gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i16.c: New test.
*
gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i32.c: New test.
*
gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i8.c: New test.
Signed-off-by: Pan Li <pan2...@intel.com>
(cherry picked from commit f411abe7935e01b7e61f966d12a7a0850ca8f1c0)
Diff:
---
.../rvv/autovec/unop/vec_sat_s_trunc-6-i16-to-i8.c | 9 +++++++++
.../autovec/unop/vec_sat_s_trunc-6-i32-to-i16.c | 9 +++++++++
.../rvv/autovec/unop/vec_sat_s_trunc-6-i32-to-i8.c | 9 +++++++++
.../autovec/unop/vec_sat_s_trunc-6-i64-to-i16.c | 9 +++++++++
.../autovec/unop/vec_sat_s_trunc-6-i64-to-i32.c | 9 +++++++++
.../rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i8.c | 9 +++++++++
.../autovec/unop/vec_sat_s_trunc-run-6-i16-to-i8.c | 16 ++++++++++++++++
.../unop/vec_sat_s_trunc-run-6-i32-to-i16.c | 16 ++++++++++++++++
.../autovec/unop/vec_sat_s_trunc-run-6-i32-to-i8.c | 16 ++++++++++++++++
.../unop/vec_sat_s_trunc-run-6-i64-to-i16.c | 16 ++++++++++++++++
.../unop/vec_sat_s_trunc-run-6-i64-to-i32.c | 16 ++++++++++++++++
.../autovec/unop/vec_sat_s_trunc-run-6-i64-to-i8.c | 16 ++++++++++++++++
.../gcc.target/riscv/rvv/autovec/vec_sat_arith.h | 22 ++++++++++++++++++++++
13 files changed, 172 insertions(+)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i16-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i16-to-i8.c
new file mode 100644
index 000000000000..c97057355c40
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i16-to-i8.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_TRUNC_FMT_6(int8_t, int16_t, INT8_MIN, INT8_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i32-to-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i32-to-i16.c
new file mode 100644
index 000000000000..629c07347bb9
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i32-to-i16.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_TRUNC_FMT_6(int16_t, int32_t, INT16_MIN, INT16_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i32-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i32-to-i8.c
new file mode 100644
index 000000000000..c70c8321c068
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i32-to-i8.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_TRUNC_FMT_6(int8_t, int32_t, INT8_MIN, INT8_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i16.c
new file mode 100644
index 000000000000..d1967baf901d
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i16.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_TRUNC_FMT_6(int16_t, int64_t, INT16_MIN, INT16_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i32.c
new file mode 100644
index 000000000000..8e2625fbed16
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i32.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_TRUNC_FMT_6(int32_t, int64_t, INT32_MIN, INT32_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i8.c
new file mode 100644
index 000000000000..b75a82e342cf
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-6-i64-to-i8.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_TRUNC_FMT_6(int8_t, int64_t, INT8_MIN, INT8_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i16-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i16-to-i8.c
new file mode 100644
index 000000000000..457abd6ee078
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i16-to-i8.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T1 int8_t
+#define T2 int16_t
+
+DEF_VEC_SAT_S_TRUNC_FMT_6_WRAP(T1, T2, INT8_MIN, INT8_MAX)
+
+#define T TEST_UNARY_STRUCT_DECL(T1, T2)
+#define DATA TEST_UNARY_DATA_WRAP(T1, T2)
+#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_6_WRAP(T1, T2, out, in,
N)
+
+#include "vec_sat_unary_vv_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i32-to-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i32-to-i16.c
new file mode 100644
index 000000000000..694a771689c3
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i32-to-i16.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T1 int16_t
+#define T2 int32_t
+
+DEF_VEC_SAT_S_TRUNC_FMT_6_WRAP(T1, T2, INT16_MIN, INT16_MAX)
+
+#define T TEST_UNARY_STRUCT_DECL(T1, T2)
+#define DATA TEST_UNARY_DATA_WRAP(T1, T2)
+#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_6_WRAP(T1, T2, out, in,
N)
+
+#include "vec_sat_unary_vv_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i32-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i32-to-i8.c
new file mode 100644
index 000000000000..457abd6ee078
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i32-to-i8.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T1 int8_t
+#define T2 int16_t
+
+DEF_VEC_SAT_S_TRUNC_FMT_6_WRAP(T1, T2, INT8_MIN, INT8_MAX)
+
+#define T TEST_UNARY_STRUCT_DECL(T1, T2)
+#define DATA TEST_UNARY_DATA_WRAP(T1, T2)
+#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_6_WRAP(T1, T2, out, in,
N)
+
+#include "vec_sat_unary_vv_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i16.c
new file mode 100644
index 000000000000..6fb64a3e5ffd
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i16.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T1 int16_t
+#define T2 int64_t
+
+DEF_VEC_SAT_S_TRUNC_FMT_6_WRAP(T1, T2, INT16_MIN, INT16_MAX)
+
+#define T TEST_UNARY_STRUCT_DECL(T1, T2)
+#define DATA TEST_UNARY_DATA_WRAP(T1, T2)
+#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_6_WRAP(T1, T2, out, in,
N)
+
+#include "vec_sat_unary_vv_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i32.c
new file mode 100644
index 000000000000..0c8bc7458ae3
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i32.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T1 int32_t
+#define T2 int64_t
+
+DEF_VEC_SAT_S_TRUNC_FMT_6_WRAP(T1, T2, INT32_MIN, INT32_MAX)
+
+#define T TEST_UNARY_STRUCT_DECL(T1, T2)
+#define DATA TEST_UNARY_DATA_WRAP(T1, T2)
+#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_6_WRAP(T1, T2, out, in,
N)
+
+#include "vec_sat_unary_vv_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i8.c
new file mode 100644
index 000000000000..3c4513cad758
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_s_trunc-run-6-i64-to-i8.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T1 int8_t
+#define T2 int64_t
+
+DEF_VEC_SAT_S_TRUNC_FMT_6_WRAP(T1, T2, INT8_MIN, INT8_MAX)
+
+#define T TEST_UNARY_STRUCT_DECL(T1, T2)
+#define DATA TEST_UNARY_DATA_WRAP(T1, T2)
+#define RUN_UNARY(out, in, N) RUN_VEC_SAT_S_TRUNC_FMT_6_WRAP(T1, T2, out, in,
N)
+
+#include "vec_sat_unary_vv_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
index 30996e14a3b4..1586a99603fc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
@@ -732,6 +732,23 @@ vec_sat_s_trunc_##NT##_##WT##_fmt_5 (NT *out, WT *in,
unsigned limit) \
#define DEF_VEC_SAT_S_TRUNC_FMT_5_WRAP(NT, WT, NT_MIN, NT_MAX) \
DEF_VEC_SAT_S_TRUNC_FMT_5(NT, WT, NT_MIN, NT_MAX)
+#define DEF_VEC_SAT_S_TRUNC_FMT_6(NT, WT, NT_MIN, NT_MAX) \
+void __attribute__((noinline)) \
+vec_sat_s_trunc_##NT##_##WT##_fmt_6 (NT *out, WT *in, unsigned limit) \
+{ \
+ unsigned i; \
+ for (i = 0; i < limit; i++) \
+ { \
+ WT x = in[i]; \
+ NT trunc = (NT)x; \
+ out[i] = (WT)NT_MIN >= x || x > (WT)NT_MAX \
+ ? x < 0 ? NT_MIN : NT_MAX \
+ : trunc; \
+ } \
+}
+#define DEF_VEC_SAT_S_TRUNC_FMT_6_WRAP(NT, WT, NT_MIN, NT_MAX) \
+ DEF_VEC_SAT_S_TRUNC_FMT_6(NT, WT, NT_MIN, NT_MAX)
+
#define RUN_VEC_SAT_U_TRUNC_FMT_1(NT, WT, out, in, N) \
vec_sat_u_trunc_##NT##_##WT##_fmt_1 (out, in, N)
#define RUN_VEC_SAT_U_TRUNC_FMT_1_WRAP(NT, WT, out, in, N) \
@@ -777,4 +794,9 @@ vec_sat_s_trunc_##NT##_##WT##_fmt_5 (NT *out, WT *in,
unsigned limit) \
#define RUN_VEC_SAT_S_TRUNC_FMT_5_WRAP(NT, WT, out, in, N) \
RUN_VEC_SAT_S_TRUNC_FMT_5(NT, WT, out, in, N)
+#define RUN_VEC_SAT_S_TRUNC_FMT_6(NT, WT, out, in, N) \
+ vec_sat_s_trunc_##NT##_##WT##_fmt_6 (out, in, N)
+#define RUN_VEC_SAT_S_TRUNC_FMT_6_WRAP(NT, WT, out, in, N) \
+ RUN_VEC_SAT_S_TRUNC_FMT_6(NT, WT, out, in, N)
+
#endif
