Commit 33729a5fc0ca ("iommu/io-pgtable-arm: Remove split on unmap
behavior") did away with the treatment of partial unmaps of huge IOPTEs.
In the case of Panthor, that means an attempt to run a VM_BIND unmap
operation on a memory region whose start address and size aren't 2MiB
aligned, in the even
On Wed, 2025-10-08 at 11:48 +1000, Dave Airlie wrote:
> I think that is getting a bit complicated for distros though. There is
> no reason to ever want 535 only. We don't want to give people options
> we don't actually support.
My Ubuntu 25.04 system ships with kernel 6.14 but only the r535 firmwa
panfrost_job_* prefixed functions in panfrost_job.c deal with both
panfrost_job objects and also the more general JM (Job Manager) side of
the device itself. This is confusing.
Reprefix functions that program the JM to panfrosot_jm_* instead.
Signed-off-by: Adrián Larumbe
---
drivers/gpu/drm/pa
The RXSETR_CRCEN(n) and RXSETR_ECCEN(n) macros both take parameter (n),
add the missing macro parameter. Neither of those macros is used by the
driver, so for now the bug is harmless.
Fixes: 685e8dae19df ("drm/rcar-du: dsi: Implement DSI command support")
Reviewed-by: Laurent Pinchart
Signed-off-
This should allow amdkfd_fences to outlive the amdgpu module.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 6
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c | 36 +++
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 7 ++--
drivers/gpu/d
Hi Marek,
On Thu, 16 Oct 2025 at 16:13, Marek Vasut wrote:
> On 10/16/25 12:14 PM, Geert Uytterhoeven wrote:
> >> which are also never disabled, do we want to disable the GPU by default
> >> and enable per-board ?
> >
> > Yes please. We do the same with renesas,*-mali GPU nodes.
> > The board may
On Sun, 5 Oct 2025 at 19:49, Ayushi Makhija wrote:
>
> On 9/26/2025 3:32 AM, Dmitry Baryshkov wrote:
> > On Thu, Sep 25, 2025 at 11:06:01AM +0530, Ayushi Makhija wrote:
> >> Add device tree nodes for the DSI0 controller with their corresponding
> >> PHY found on Qualcomm QCS8300 SoC.
> >>
> >> Sig
From: Nagaraju Siddineni
- Add core buffer‑control module (mfc_core_buf_ctrl.c)
with set/get/recover/restore ops.
- Add context‑control layer (mfc_ctx_ctrl.c) defining
V4L2 decoder controls and per‑buffer handling.
- Export mfc_bufs_ops and mfc_ctrls_ops for integration
with existing MFC core
Pr
On 10/11/2025 9:38 PM, Michał Winiarski wrote:
> An upcoming change will use GuC buffer cache as a place where GuC
> migration data will be stored, and the memory requirement for that is
> larger than indirect data.
> Allow the caller to pass the size based on the intended usecase.
>
> Signed-o
On 09/10/2025 23:13, Krzysztof Kozlowski wrote:
> On 09/10/2025 17:02, Pet Weng wrote:
>> + The HDMI transmitter side supports up to 4Kx2K@30Hz resolutions, and is
>> + compliant with HDMI 1.4b and HDCP 1.4.
>> +
>> + For audio, the IT61620 supports up to 8-channel LPCM via I2S (multi-line
>> o
On 10/7/2025 10:11 AM, Youssef Samir wrote:
From: Youssef Samir
If msg_xfer() is called and the channel ring does not have enough room
to accommodate the whole message, the function sleeps and tries again.
It uses retry_count to keep track of the number of retrials done. This
variable is not us
On Sun, 28 Sep 2025 17:50:18 +0300
Leon Romanovsky wrote:
> From: Leon Romanovsky
>
> Make sure that all VFIO PCI devices have peer-to-peer capabilities
> enables, so we would be able to export their MMIO memory through DMABUF,
>
> Signed-off-by: Leon Romanovsky
> ---
> drivers/vfio/pci/vfio
On 08/10/2025 09:53, Tvrtko Ursulin wrote:
> Remove member no longer used by the scheduler core.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Frank Binns
> Cc: Matt Coster
> Cc: [email protected]
Reviewed-by: Matt Coster
> ---
> drivers/gpu/drm/imagination/pvr_queue.c | 1 -
> 1 fi
On Fri, Sep 19, 2025 at 12:29:29PM +0900, Ryosuke Yasuoka wrote:
> Add drm_panic support for stdu in vmwgfx. This patch was tested in a VM
> with VMSVGA on Virtual Box.
>
> Based on the feedback for v2 patch, I've made the following updates in
> my v3 patch.
> - Use MEMREMAP_WB | MEMREMAP_DEC flag
Free the client memory in the client free callback. Also move the
debugging output into the free callback: drm_client_release() puts
the reference on the DRM device, so pointers to the device should
be considered dangling afterwards.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/clients/d
Sorry, my previous description may not have been accurate enough.
When|radeon_audio_detect|is triggered, the disconnected state of the
connector has not yet been uploaded to DRM.
This prevents other components (functions not included
in|radeon_dvi_detect|/|radeon_dp_detect|) from retrieving the
Add support for X403 format.
Reviewed-by: Laurent Pinchart
Reviewed-by: Vishal Sagar
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/xlnx/zynqmp_disp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c
b/drivers/gpu/drm/xlnx/zynqmp_disp.c
index fe11
Hi Dmitry,
On 9/23/2025 9:12 AM, Dmitry Baryshkov wrote:
On Mon, Sep 22, 2025 at 09:20:34AM +0800, Chaoyi Chen wrote:
From: Chaoyi Chen
The RK3399 SoC integrates two USB/DP combo PHYs, each of which
supports software-configurable pin mapping and DisplayPort lane
assignment. These capabilities
This series aims to reduce the page tables overhead of DRM drivers for
builds with CONFIG_TRANSPARENT_HUGEPAGE enabled and either the sysfs
knob '/sys/kernel/mm/transparent_hugepage/shmem_enabled' appropriately
set or drivers using a dedicated huge tmpfs mount point.
It starts by implementing a ma
Two patches to implement a generic framework for dma-buf to support
local private interconnects.
The interconnect support is negotiated as part of an attachment and is
not a property of the dma-buf itself. Just like pcie p2p support.
The first patch adds members to the dma_buf_attach_ops and to th
Adreno 840 present in Kaanapali SoC is the second generation GPU in
A8x family. It comes in 2 variants with either 2 or 3 Slices. This is
in addition to the SKUs supported based on the GPU FMAX.
Add the necessary register configurations to the catalog and enable
support for it.
Signed-off-by: Akh
This is a note to let you know that I've just added the patch titled
minmax: deduplicate __unconst_integer_typeof()
to the 5.15-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
minmax-
Call intel_casf_enable and intel_casf_disable
in atomic commit path to enable and disable casf.
Call intel_casf_update_strength to only update
the desired strength value.
v2: Introduce casf_enable here.[Ankit]
v3: Use is_disabling in casf_disabling.[Ankit]
v4: Swap old_state and new_state param.[A
These loops in drm_bridge.c iterate over the encoder chain using
list_for_each_entry_reverse), which does not prevent changes to the bridge
chain while iterating over it.
Take the encoder chain mutex while iterating to avoid chain changes while
iterating.
All the "simple" loops are converted. drm
On 9/22/25 17:44, Alexandr Sapozhnkiov wrote:
> From: Alexandr Sapozhnikov
>
> Return value of function drm_crtc_init_with_planes(),
> called at virtgpu_display.c:276, is not checked,
> but it is usually checked for this function
>
> Found by Linux Verification Center (linuxtesting.org) with S
Hi
Am 23.09.25 um 08:34 schrieb Thomas Zimmermann:
cc Ruben
Am 22.09.25 um 19:43 schrieb Mehdi Ben Hadj Khelifa:
Replace kmalloc with kmalloc array in drm/gud/gud_pipe.c since the
calculation inside kmalloc is dynamic "width * height" and added
u_char as the size of each element.
Signed-off-b
On Fri, Sep 26, 2025 at 11:30:26AM +0100, Srinivas Kandagatla wrote:
>
>
> On 9/25/25 5:28 AM, Dmitry Baryshkov wrote:
> > On Thu, Sep 25, 2025 at 12:05:09PM +0800, Jianfeng Liu wrote:
> >> After reusing drm_hdmi_audio_* helpers and drm_bridge_connector
> >> integration in drm/msm/dp, we have dro
On 9/30/25 6:16 AM, Alistair Popple wrote:
> Changes since v2:
>
> The main change since v2 has been to make all firmware bindings
> completely opaque. It has been made clear this is a pre-requisite for
Any hints about where to see this aspect would be welcome.
...
> A full tree including the
On 10/14/25 1:52 PM, Matt Coster wrote:
Hello Matt,
+++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi
@@ -2565,6 +2565,18 @@ gic: interrupt-controller@f101 {
resets = <&cpg 408>;
};
+ gpu: gpu@fd00 {
+ compatible = "renesa
It's not uncommon for the particular device to support only a subset of
HDMI InfoFrames. Currently it's mostly ignored by the framework: it
calls write_infoframe() / clear_infoframe() callbacks for all frames and
expects them to return success even if the InfoFrame is not supported.
Sort that out,
From: Xiangxu Yin
Describe the DisplayPort controller for Qualcomm SM6150 SoC.
Signed-off-by: Xiangxu Yin
---
.../devicetree/bindings/display/msm/qcom,sm6150-mdss.yaml | 11 +++
1 file changed, 11 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sm615
On 10/14/2025 12:01 PM, Lizhi Hou wrote:
Add new parameter DRM_AMDXDNA_HW_LAST_ASYNC_ERR to get array IOCTL. When
hardware reports an error, the driver save the error information and
timestamp. This new get array parameter retrieves the last error.
Signed-off-by: Lizhi Hou
---
drivers/acce
On 09.10.25 12:25, Balbir Singh wrote:
On 10/9/25 17:12, David Hildenbrand wrote:
On 09.10.25 06:21, Balbir Singh wrote:
On 8/22/25 06:06, David Hildenbrand wrote:
Let's reject them early, which in turn makes folio_alloc_gigantic() reject
them properly.
To avoid converting from order to nr_pa
On Mon, Sep 22, 2025 at 07:28:17PM +0800, Xiangxu Yin wrote:
>
> On 9/22/2025 5:45 PM, Dmitry Baryshkov wrote:
> > On Mon, Sep 22, 2025 at 02:58:17PM +0800, Xiangxu Yin wrote:
> >> On 9/20/2025 2:41 AM, Dmitry Baryshkov wrote:
> >>> On Fri, Sep 19, 2025 at 10:24:29PM +0800, Xiangxu Yin wrote:
> >>
This is a note to let you know that I've just added the patch titled
minmax.h: move all the clamp() definitions after the min/max() ones
to the 6.1-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the pa
On Wed, 1 Oct 2025 14:04:18 +0200
Boris Brezillon wrote:
> On Wed, 1 Oct 2025 13:45:36 +0200
> Alice Ryhl wrote:
>
> > On Wed, Oct 1, 2025 at 1:27 PM Boris Brezillon
> > wrote:
> > >
> > > On Wed, 01 Oct 2025 10:41:36 +
> > > Alice Ryhl wrote:
> > >
> > > > When using GPUVM in immed
On Fri, Sep 19, 2025 at 10:24:22PM +0800, Xiangxu Yin wrote:
> Move resets to qmp_phy_cfg for per-PHY customization. Keep legacy DT
> path on the old hardcoded list; non-legacy path uses cfg->reset_list.
>
> Signed-off-by: Xiangxu Yin
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 18 +++
On Monday, 6 October 2025 12:58:55 Central European Summer Time Nicolas
Frattaroli wrote:
> On Friday, 3 October 2025 23:41:16 Central European Summer Time Chia-I Wu
> wrote:
> > On Fri, Oct 3, 2025 at 1:16 PM Nicolas Frattaroli
> > wrote:
> > >
> > > Various MediaTek SoCs use GPU integration si
On Wed, 03 Sep 2025 21:50:58 +0300, Cristian Ciocaltea wrote:
> The first patch in the series implements the CEC capability of the
> Synopsys DesignWare HDMI QP TX controller found in RK3588 & RK3576 Socs.
> This is based on the downstream code, but rewritten on top of the CEC
> helpers added rec
On 15/10/2025 14:00, Boris Brezillon wrote:
> Will be needed if we want to skip CPU cache maintenance operations when
> the GPU can snoop CPU caches.
>
> v2:
> - New commit
>
> v3:
> - Fix the coherency values (enum instead of bitmask)
>
> Signed-off-by: Boris Brezillon
> ---
> drivers/gpu/drm
Hi,
On 2025-09-24 20:17 UTC, Dmitry Baryshkov wrote:
>> msm_dp_audio_prepare is not called because hdmi-codec driver only checks
>> and runs hw_params. This commit will add hw_params callback function
>> same as drm_connector_hdmi_audio_prepare, so that hdmi-codec driver can
>> work with userspace
From: Chaoyi Chen
This patch add support for Type-C Port Controller Manager. Each PHY
will register typec_mux and typec_switch when external Type-C
controller is present. Type-C events are handled by TCPM without
extcon.
The extcon device should still be supported.
Signed-off-by: Chaoyi Chen
-
On 09/10/2025 12:43, Adrián Larumbe wrote:
> Drawing from commit d2624d90a0b7 ("drm/panthor: assign unique names to
> queues"), give scheduler queues proper names that reflect the function
> of their JM slot, so that this will be shown when gathering DRM
> scheduler tracepoints.
>
> Signed-off-by:
An upcoming change will use GuC buffer cache as a place where GuC
migration data will be stored, and the memory requirement for that is
larger than indirect data.
Allow the caller to pass the size based on the intended usecase.
Signed-off-by: Michał Winiarski
---
drivers/gpu/drm/xe/tests/xe_guc_
Handle the DSC pixel throughput quirk, limiting the compressed link-bpp
value for Synaptics Panamera branch devices, working around a
blank/unstable output issue observed on docking stations containing
these branch devices, when using a mode with a high pixel clock and a
high compressed link-bpp va
From: David Heidelberg
Follow the device-tree change for OnePlus 6/6T and invert the reset
polarity in the driver.
Fixes: 5933baa36e26 ("drm/panel/samsung-sofef00: Add panel for OnePlus 6/T
devices")
Signed-off-by: David Heidelberg
---
drivers/gpu/drm/panel/panel-samsung-sofef00.c | 10 +-
On Sun, Sep 28, 2025 at 05:52:35PM +0800, Chaoyi Chen wrote:
> On 9/23/2025 9:50 AM, Dmitry Baryshkov wrote:
>
> [...]
>
>
> > > + /* One endpoint may correspond to one HPD bridge. */
> > > + for_each_of_graph_port_endpoint(port, dp_ep) {
> > > + /* Try to get "port" node of correspond P
In the pursuit of making UI/VI layer code independent of DE version,
change meaning of UI index to index of the plane within mixer. DE33 can
split amount of VI and UI planes between multiple mixer in whatever way
it deems acceptable, so simple calculation VI num + UI index won't be
meaningful anymo
Hi Marek,
On Thu, 16 Oct 2025 at 11:48, Marek Vasut wrote:
> On 10/16/25 10:22 AM, Geert Uytterhoeven wrote:
> >> --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi
> >> +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi
> >> @@ -2575,6 +2575,22 @@ gic: interrupt-controller@f101 {
> >>
The LD070WX3 is a Color Active Matrix Liquid Crystal Display with an
integral Light Emitting Diode (LED) backlight system. The matrix employs
a-Si Thin Film Transistor as the active element. It is a transmissive type
display operating in the normally Black mode. This TFT-LCD has 7.0 inches
diagonal
After reusing drm_hdmi_audio_* helpers and drm_bridge_connector
integration in drm/msm/dp, we have dropped msm_dp_audio_hw_params and
use msm_dp_audio_prepare instead. While userspace is still calling
hw_params to do audio initialization, and we get the following errors:
q6apm-lpass-dais 370.r
On 9/25/25 20:01, David Hildenbrand wrote:
> On 16.09.25 14:21, Balbir Singh wrote:
>> Add support for splitting device-private THP folios, enabling fallback
>> to smaller page sizes when large page allocation or migration fails.
>>
>> Key changes:
>> - split_huge_pmd(): Handle device-private PMD e
Reduce coupling to implementation details of the formatting machinery by
avoiding direct use for `core`'s formatting traits and macros.
This backslid in commit 9def0d0a2a1c ("rust: alloc: add
Vec::push_within_capacity").
Reviewed-by: Alice Ryhl
Acked-by: Danilo Krummrich
Signed-off-by: Tamir Du
The mediatek atomic_check implementation uses the deprecated
drm_atomic_get_existing_crtc_state() helper.
This hook is called as part of the global atomic_check, thus before the
states are swapped. The existing state thus points to the new state, and
we can use drm_atomic_get_new_crtc_state() inst
On 13/10/2025 10:17, Tvrtko Ursulin wrote:
On 13/10/2025 09:48, Thomas Hellström wrote:
Hi, Tvrtko,
On Sat, 2025-10-11 at 09:00 +0100, Tvrtko Ursulin wrote:
On 10/10/2025 15:11, Thomas Hellström wrote:
On Thu, 2025-10-09 at 09:53 +0100, Tvrtko Ursulin wrote:
On 08/10/2025 15:39, Thomas
From dmesg we see this:
[ 35.845199] ast 0008:04:00.0: [drm] Using ASPEED DisplayPort transmitter
From: Thomas Zimmermann
Date: Tuesday, September 23, 2025 at 10:35 AM
To: Carol Soto , Nirmoy Das , KuoHsiang
Chou
Cc: [email protected] , Matt
Ochs
Subject: Re: ast "WARN_ON(!_
Le 03/10/2025 à 10:59, Luca Ceresoli a écrit :
DRM bridges must be added before they are attached. Add a warning to catch
violations.
The warning is based on the bridge not being part of any list, so it will
trigger if the bridge is being attached without ever having been added.
It won't cat
From: Nagaraju Siddineni
Add a V4L2‑based decoder for Exynos MFC.
- Implement full decoder V4L2 ioctl, control, buffer, and stream handling.
- Provide ioctl getter and default format helper.
Move the decoder to the standard V4L2 framework,
to enable proper media‑device registration and user‑spac
Applied to drm-misc-next
On 10/1/2025 9:50 AM, Karol Wachowski wrote:
> Reviewed-by: Karol Wachowski
>
> On 9/25/2025 4:51 PM, Maciej Falkowski wrote:
>> From: Andrzej Kacprowski
>>
>> Fix doc description of job structure as it is
>> improperly formatted. Align order of job structure's
>> fields
When keepalive vote is set to false IFPC will be re-enabled even if the
perfcounter oob vote is set.
Workaround this by not setting keepalive vote when sysprof is active.
---
I have little confidence that this is the proper solution hence why
this is an RFC.
Hopefully something better can be fou
Brevity is good.
Signed-off-by: Daniel Stone
---
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 24
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
index e2bf2dbd882b.
On 10/3/25 16:41, Francesco Valla wrote:
Hi Jocelyn,
On Friday, 3 October 2025 at 14:48:03 Jocelyn Falempe
wrote:
On 10/3/25 12:33, Francesco Valla wrote:
The color parameter passed to drm_draw_fill24() was truncated to 16
bits, leading to an incorrect color drawn to the target iosys_map.
Fi
On 09/10/2025 14:54, Konrad Dybcio wrote:
On 10/8/25 4:05 PM, David Heidelberg via B4 Relay wrote:
From: David Heidelberg
Describe panel Tearing Effect (TE) GPIO line.
Reviewed-by: Konrad Dybcio
Signed-off-by: David Heidelberg
---
arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 1 +
Set the correct DMA mask. Without this DMA will fail on some setups.
Signed-off-by: Alistair Popple
---
Changes for v2:
- Update DMA mask to correct value for Ampere/Turing (47 bits)
---
drivers/gpu/nova-core/driver.rs | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git
On 15.09.25 12:01, Michel Dänzer wrote:
> On 12.09.25 15:45, Derek Foreman wrote:
>> On 9/12/25 2:33 AM, Chuanyu Tseng wrote:
>>>
>>> This is done through 2 new CRTC properties, along with a client
>>> cap. See the docstrings in patch for details.
>
> Not sure why a client cap would be needed for
Reviewed-by: Karol Wachowski
On 9/25/2025 4:51 PM, Maciej Falkowski wrote:
> From: Jacek Lawrynowicz
>
> Add additional warnings related to allocation and
> deallocation of buffer objects to better track possible
> memory leaks and generally the BO's lifecycle.
>
> Introduce checks for handle_co
commit aad0214f3026 ("dyndbg: add DECLARE_DYNDBG_CLASSMAP macro")
DECLARE_DYNDBG_CLASSMAP() has a design error; its usage fails a
basic K&R rule: "define once, refer many times".
When DRM_USE_DYNAMIC_DEBUG=y, it is used across DRM core & drivers;
each invocation allocates/inits the classmap under
gud_probe() currently is a quite large function that does a lot of
different things, including USB detection, plane init, and several other
things.
This patch moves the plane and crtc init into gud_plane_init() in
gud_pipe.c, which is a more appropriate file for this. Associated
variables and stru
чт, 9 жовт. 2025 р. о 00:14 Conor Dooley пише:
>
> On Wed, Oct 08, 2025 at 10:30:33AM +0300, Svyatoslav Ryhel wrote:
> > Document MIPI calibration device found in Tegra132.
>
> Could you explain why a fallback is not suitable? The patchset is really
> too big for me to trivially check that the cha
Hi Dmitry,
On 9/12/2025 7:09 PM, Dmitry Baryshkov wrote:
On Fri, Sep 12, 2025 at 04:58:44PM +0800, Damon Ding wrote:
The &drm_panel_funcs.enable() and &drm_panel_funcs.disable() mainly
help turn on/off the backlight to make the image visible, and the
backlight operations are even needless if dr
On Fri, 10 Oct 2025 17:37:50 +0800, Langyan Ye wrote:
> Add device tree bindings for the Tianma TL121BVMS07-00 12.1-inch
> MIPI-DSI TFT LCD panel. The panel is based on the Ilitek IL79900A
> controller.
>
> Signed-off-by: Langyan Ye
> ---
> .../display/panel/ilitek,il79900a.yaml| 64 ++
On 23.09.25 13:14, Dan Carpenter wrote:
> Call dma_fence_put(fence) if dma_fence_add_callback() fails.
Well that change is obviously incorrect.
When dma_fence_add_callback() fails we already call dma_fence_put() and drop
the reference.
When the dma_fence_add_callback() call succeeds the callbac
On Mon Oct 13, 2025 at 3:20 PM JST, Alistair Popple wrote:
> Initialise the GSP resource manager arguments (rmargs) which provide
> initialisation parameters to the GSP firmware during boot. The rmargs
> structure contains arguments to configure the GSP message/command queue
> location.
>
> These a
Hi guys,
trying to not let the mail thread branch to much, I'm just replying on the
newest mail.
Please let me know if I missed some question.
On 23.09.25 08:44, Matthew Brost wrote:
> On Mon, Sep 22, 2025 at 11:25:47PM -0700, Matthew Brost wrote:
>> On Mon, Sep 22, 2025 at 11:53:06PM -0600, Ka
On Thu, Oct 16, 2025 at 11:52:24AM +0200, Boris Brezillon wrote:
> On Thu, 16 Oct 2025 10:42:21 +0200
> Marcin Ślusarz wrote:
>
> > On Wed, Oct 15, 2025 at 06:03:23PM +0200, Boris Brezillon wrote:
> > > +static int panfrost_ioctl_sync_bo(struct drm_device *ddev, void *data,
> > > +
Replace kmalloc with kmalloc array in drm/gud/gud_pipe.c since the
calculation inside kmalloc is dynamic 'width * height'
Signed-off-by: Mehdi Ben Hadj Khelifa
---
Changelog:
Changes since v2:
-Reversed width and height in parameter order.
Link:https://lore.kernel.org/all/20250923085144.22582-1-
On 9/30/2025 2:11 PM, Connor Abbott wrote:
On Tue, Sep 30, 2025 at 10:08 AM Rob Clark wrote:
On Tue, Sep 30, 2025 at 12:43 AM Dmitry Baryshkov
wrote:
On Tue, Sep 30, 2025 at 11:18:17AM +0530, Akhil P Oommen wrote:
A8x is the next generation of Adreno GPUs, featuring a significant
hardware
This is to make LLVM syntactic analysers happy.
Reviewed-by: Boris Brezillon
Signed-off-by: Adrián Larumbe
---
drivers/gpu/drm/panfrost/panfrost_mmu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.h
b/drivers/gpu/drm/panfrost/panfrost_mmu.h
index e6e
On 10/6/25 2:09 PM, Joel Fernandes wrote:
> Add initial structures and helpers for page table management. Will
> expand and build on this in later patches. Uses bitstruct for clean
> code.
>
> Signed-off-by: Joel Fernandes
> ---
> Rebased on rust-drm-next + bitfield patches [1].
>
> [1]
> https
Le 09/10/2025 à 12:27, David Hildenbrand a écrit :
On 09.10.25 12:01, Christophe Leroy wrote:
Le 09/10/2025 à 11:20, David Hildenbrand a écrit :
On 09.10.25 11:16, Christophe Leroy wrote:
Le 09/10/2025 à 10:14, David Hildenbrand a écrit :
On 09.10.25 10:04, Christophe Leroy wrote:
L
Hi Prabhakar,
On Thu, 2 Oct 2025 at 18:17, Prabhakar wrote:
> From: Lad Prabhakar
>
> Add MIPI DSI support for the Renesas RZ/V2H(P) SoC. Compared to the
> RZ/G2L family, the RZ/V2H(P) requires dedicated D-PHY PLL programming,
> different clock configuration, and additional timing parameter hand
If we reach the beginning of the LRU AS list, then return an error.
Reviewed-by: Boris Brezillon
Signed-off-by: Adrián Larumbe
---
drivers/gpu/drm/panfrost/panfrost_job.c | 6 +-
drivers/gpu/drm/panfrost/panfrost_mmu.c | 5 +++--
drivers/gpu/drm/panfrost/panfrost_mmu.h | 2 +-
d
It's unnecessary to set initial ExtDst source selection because KMS
driver would do that when doing atomic commits. Drop the selection.
This is needed as a preparation for reading ExtDst source selection
when trying to disable CRTC at boot in an upcoming commit.
Reviewed-by: Frank Li
Signed-off-
From: Joel Fernandes
Add definition for RISCV_CPUCTL register and use it in a new falcon API
to check if the RISC-V core of a Falcon is active. It is required by
the sequencer to know if the GSP's RISCV processor is active.
Signed-off-by: Joel Fernandes
---
drivers/gpu/nova-core/falcon.rs | 9
On 10/13/2025 10:11 AM, Dmitry Baryshkov wrote:
On Mon, Oct 13, 2025 at 09:26:06AM +0800, Chaoyi Chen wrote:
On 10/12/2025 2:52 AM, Dmitry Baryshkov wrote:
On Sat, Oct 11, 2025 at 11:32:31AM +0800, Chaoyi Chen wrote:
From: Chaoyi Chen
The RK3399 has two USB/DP combo PHY and one CDN-DP cont
Blank the display by disabling sync pulses with VGACR17<7>. Unblank
by reenabling them. This VGA setting should be supported by all Aspeed
hardware.
Ast currently blanks via sync-off bits in VGACRB6. Not all BMCs handle
VGACRB6 correctly. After disabling sync during a reboot, some BMCs do
not reen
Derive the Zeroable trait for existing bindgen generated bindings. This
is safe because all bindgen generated types are simple integer types for
which any bit pattern, including all zeros, is valid.
Signed-off-by: Alistair Popple
---
Changes for v5:
- New for v5
---
drivers/gpu/nova-core/gsp/
AQE (Applicaton Qrisc Engine) is a dedicated core inside CP which aides
in Raytracing related workloads. Add support for loading the AQE firmware
and initialize the necessary registers.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 24
drive
This is an associated type that may be used in order to specify a data-type
to pass to gem objects when construction them, allowing for drivers to more
easily initialize their private-data for gem objects.
Signed-off-by: Lyude Paul
---
V3:
* s/BaseDriverObject/DriverObject/
V4:
* Fix leftover re
On 26.09.25 16:19, Xaver Hugl wrote:
>> 2) Kernel does LFC/ramping
>
> I don't think that would be a good idea. The kernel doing ramping
> would mean the user can't (easily) configure it, and it would
> complicate the compositor doing ramping with a different strategy
> (like reducing the allowed
Document the DisplayPort controller found in the Qualcomm Glymur SoC.
There are 4 controllers and their new core revision is different when
compared to all previous platforms, therefore being incompatible.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Abel Vesa
---
Documentation/devicetree/bi
On 09.10.25 10:04, Christophe Leroy wrote:
Le 09/10/2025 à 09:22, David Hildenbrand a écrit :
On 09.10.25 09:14, Christophe Leroy wrote:
Hi David,
Le 01/09/2025 à 17:03, David Hildenbrand a écrit :
diff --git a/mm/hugetlb.c b/mm/hugetlb.c
index 1e777cc51ad04..d3542e92a712e 100644
--- a/mm/h
From: Sebastian Reichel
I planned to set the polarity of horizontal and vertical sync, but
accidentally described vertical sync twice with different polarity
instead.
Note, that there is no functional change, because the driver only
makes use of DRM_MODE_FLAG_P[HV]SYNC to divert from the default
v7:
- Delete the three preceding function definitions
- delete Delete the redundant code and comments
v6:
- simplify to return drm_atomic_helper_check_plane_state()
- remove empty line
- remove call drm_probe_ddc and smidebug
- replace drm_err with drm_dbg_kms
- add callback .disable
(http
Remove member no longer used by the scheduler core.
Signed-off-by: Tvrtko Ursulin
Cc: Lucas De Marchi
Cc: "Thomas Hellström"
Cc: Rodrigo Vivi
Cc: [email protected]
---
drivers/gpu/drm/xe/xe_dep_scheduler.c | 1 -
drivers/gpu/drm/xe/xe_execlist.c | 1 -
drivers/gpu/drm/xe/xe_
On 03/10/2025 17:47, Joel Fernandes wrote:
Out of broad need for the register and bitfield macros in Rust, move
them out of nova into the kernel crate. Several usecases need them (Nova
is already using these and Tyr developers said they need them).
bitfield moved into kernel crate - defines bitf
On Fri, Oct 03, 2025 at 03:22:23PM +0200, Maxime Ripard wrote:
> On Tue, Sep 30, 2025 at 10:02:28AM +0300, Dmitry Baryshkov wrote:
> > On Mon, Sep 29, 2025 at 03:00:04PM +0200, Maxime Ripard wrote:
> > > On Thu, Sep 25, 2025 at 05:16:07PM +0300, Dmitry Baryshkov wrote:
> > > > On Thu, Sep 25, 2025
This series avoids a race between DRM bridge removal and usage of the
bridge private_obj during DRM_MODESET_LOCK_ALL_BEGIN/END() and other
locking operations.
This is part of the work towards removal of bridges from a still existing
DRM pipeline without use-after-free. The grand plan was discussed
Hi everyone,
dma_fences have ever lived under the tyranny dictated by the module
lifetime of their issuer, leading to crashes should anybody still holding
a reference to a dma_fence when the module of the issuer was unloaded.
But those days are over! The patch set following this mail finally
impl
On Mon Sep 29, 2025 at 1:18 PM JST, Alexandre Courbot wrote:
> On Fri Sep 26, 2025 at 10:05 PM JST, Danilo Krummrich wrote:
>> Meanwhile nova-core depends on CONFIG_64BIT and a raw DmaAddress is
>> always a u64, hence remove the now actually useless conversion.
>>
>> Signed-off-by: Danilo Krummrich
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