On Mon, Sep 22, 2025 at 07:28:17PM +0800, Xiangxu Yin wrote: > > On 9/22/2025 5:45 PM, Dmitry Baryshkov wrote: > > On Mon, Sep 22, 2025 at 02:58:17PM +0800, Xiangxu Yin wrote: > >> On 9/20/2025 2:41 AM, Dmitry Baryshkov wrote: > >>> On Fri, Sep 19, 2025 at 10:24:29PM +0800, Xiangxu Yin wrote: > >>>> Add QCS615-specific configuration for USB/DP PHY, including DP init > >>>> routines, voltage swing tables, and platform data. Add compatible > >>>> "qcs615-qmp-usb3-dp-phy". > >>>> > >>>> Signed-off-by: Xiangxu Yin <[email protected]> > >>>> --- > >>>> drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 395 > >>>> +++++++++++++++++++++++++++++++ > >>>> 1 file changed, 395 insertions(+) > >>>> > >>>> + > >>>> + writel(0x3f, qmp->dp_tx + QSERDES_V2_TX_TRANSCEIVER_BIAS_EN); > >>>> + writel(0x10, qmp->dp_tx + QSERDES_V2_TX_HIGHZ_DRVR_EN); > >>>> + writel(0x0a, qmp->dp_tx + QSERDES_V2_TX_TX_POL_INV); > >>>> + writel(0x3f, qmp->dp_tx2 + QSERDES_V2_TX_TRANSCEIVER_BIAS_EN); > >>>> + writel(0x10, qmp->dp_tx2 + QSERDES_V2_TX_HIGHZ_DRVR_EN); > >>>> + writel(0x0a, qmp->dp_tx2 + QSERDES_V2_TX_TX_POL_INV); > >>> Are you sure that these don't need to be adjusted based on > >>> qmp->orientation or selected lanes count? > >>> > >>> In fact... I don't see orientation handling for DP at all. Don't we need > >>> it? > >> > >> Thanks for the review. > >> > >> I agree with your reasoning and compared talos 14nm HPG with hana/kona > >> 7nm PHY HPG; the 7nm COMBO PHY series has orientation/lane-count dependent > >> configs, but the 14nm PHY series does not. On QCS615 (talos), the TX_* > >> registers you pointed to are programmed with constant values regardless > >> of orientation or lane count. This has been confirmed from both the HPG > >> and the downstream reference driver. > > Thanks for the confirmation. > > > >> For orientation, from reference the only difference is DP_PHY_MODE, which > >> is set by qmp_usbc_configure_dp_mode(). The DP PHY does have an > >> SW_PORTSELECT-related register, but due to talos lane mapping from the > >> DP controller to the PHY not being the standard <0 1 2 3> sequence, it > >> cannot reliably handle orientation flip. Also, QCS615 is a fixed- > >> orientation platform (not DP-over-TypeC), so there is no validated hardware > >> path for orientation flip on this platform. > > Wait... I thought that the the non-standard lane order is handled by the > > DP driver, then we should be able to handle the orientation inside PHY > > driver as usual. > > > Yes, I have confirmed this with our verification team. > > For the non-standard lane order, handling flip requires swapping mapped > lane 0 ↔ lane 3 and lane 1 ↔ lane 2 in the logical2physical mapping. > This is a hardware limitation, and with the current PHY driver we cannot > propagate orientation status to dp_ctrl for processing.
This might mean that we might need to make DP host receive mux messages... > > > > Anyway, please add a FIXME comment into the source file and a note to > > the commit message that SW_PORTSELECT should be handled, but it's not a > > part of this patch for the stated reasons. > > > OK, I will add a |FIXME| comment in |qmp_usbc_dp_power_on| and update the > related commit message. Thanks! -- With best wishes Dmitry
