[gcc r15-2429] recog: Disallow subregs in mode-punned value [PR115881]

[Richard Sandiford via Gcc-cvs]

https://gcc.gnu.org/g:d63b6d8b494483b0049370ff0dfeee0e1d10e54b

commit r15-2429-gd63b6d8b494483b0049370ff0dfeee0e1d10e54b
Author: Richard Sandiford 
Date:   Wed Jul 31 09:23:35 2024 +0100

recog: Disallow subregs in mode-punned value [PR115881]

In g:9d20529d94b23275885f380d155fe8671ab5353a, I'd extended
insn_propagation to handle simple cases of hard-reg mode punning.
The punned "to" value was created using simplify_subreg rather
than simplify_gen_subreg, on the basis that hard-coded subregs
aren't generally useful after RA (where hard-reg propagation is
expected to happen).

This PR is about a case where the subreg gets pushed into the
operands of a plus, but the subreg on one of the operands
cannot be simplified.  Specifically, we have to generate
(subreg:SI (reg:DI sp) 0) rather than (reg:SI sp), since all
references to the stack pointer must be via stack_pointer_rtx.

However, code in x86 (reasonably) expects no subregs of registers
to appear after RA, except for special cases like strict_low_part.
This leads to an awkward situation where we can't ban subregs of sp
(because of the strict_low_part use), can't allow direct references
to sp in other modes (because of the stack_pointer_rtx requirement),
and can't allow rvalue uses of the subreg (because of the "no subregs
after RA" assumption).  It all seems a bit of a mess...

I sat on this for a while in the hope that a clean solution might
become apparent, but in the end, I think we'll just have to check
manually for nested subregs and punt on them.

gcc/
PR rtl-optimization/115881
* recog.cc: Include rtl-iter.h.
(insn_propagation::apply_to_rvalue_1): Check that the result
of simplify_subreg does not include nested subregs.

gcc/testsuite/
PR rtl-optimization/115881
* gcc.c-torture/compile/pr115881.c: New test.

Diff:
---
 gcc/recog.cc   | 21 +
 gcc/testsuite/gcc.c-torture/compile/pr115881.c | 16 
 2 files changed, 37 insertions(+)

diff --git a/gcc/recog.cc b/gcc/recog.cc
index 54b317126c29..23e4820180f8 100644
--- a/gcc/recog.cc
+++ b/gcc/recog.cc
@@ -41,6 +41,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "reload.h"
 #include "tree-pass.h"
 #include "function-abi.h"
+#include "rtl-iter.h"
 
 #ifndef STACK_POP_CODE
 #if STACK_GROWS_DOWNWARD
@@ -1082,6 +1083,7 @@ insn_propagation::apply_to_rvalue_1 (rtx *loc)
  || !REG_CAN_CHANGE_MODE_P (REGNO (x), GET_MODE (from),
 GET_MODE (x)))
return false;
+
  /* If the reference is paradoxical and the replacement
 value contains registers, we would need to check that the
 simplification below does not increase REG_NREGS for those
@@ -1090,11 +1092,30 @@ insn_propagation::apply_to_rvalue_1 (rtx *loc)
  if (paradoxical_subreg_p (GET_MODE (x), GET_MODE (from))
  && !CONSTANT_P (to))
return false;
+
  newval = simplify_subreg (GET_MODE (x), to, GET_MODE (from),
subreg_lowpart_offset (GET_MODE (x),
   GET_MODE (from)));
  if (!newval)
return false;
+
+ /* Check that the simplification didn't just push an explicit
+subreg down into subexpressions.  In particular, for a register
+R that has a fixed mode, such as the stack pointer, a subreg of:
+
+  (plus:M (reg:M R) (const_int C))
+
+would be:
+
+  (plus:N (subreg:N (reg:M R) ...) (const_int C'))
+
+But targets can legitimately assume that subregs of hard registers
+will not be created after RA (except in special circumstances,
+such as strict_low_part).  */
+ subrtx_iterator::array_type array;
+ FOR_EACH_SUBRTX (iter, array, newval, NONCONST)
+   if (GET_CODE (*iter) == SUBREG)
+ return false;
}
 
   if (should_unshare)
diff --git a/gcc/testsuite/gcc.c-torture/compile/pr115881.c 
b/gcc/testsuite/gcc.c-torture/compile/pr115881.c
new file mode 100644
index ..8379704c4c8b
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/compile/pr115881.c
@@ -0,0 +1,16 @@
+typedef unsigned u32;
+int list_is_head();
+void tu102_acr_wpr_build_acr_0_0_0(int, long, u32);
+void tu102_acr_wpr_build() {
+  u32 offset = 0;
+  for (; list_is_head();) {
+int hdr;
+u32 _addr = offset, _size = sizeof(hdr), *_data = &hdr;
+while (_size--) {
+  tu102_acr_wpr_build_acr_0_0_0(0, _addr, *_data++);
+  _addr += 4;
+}
+offset += sizeof(hdr);
+  }
+  tu102_acr_wpr_build_acr_0_0_0(0, offset, 0);
+}

[gcc r15-2430] i386: Mark target option with optimization when enabled with opt level [PR116065]

[Hongyu Wang via Gcc-cvs]

https://gcc.gnu.org/g:a59c4e496fa916cb9a484a649aa1b4cebd6550f2

commit r15-2430-ga59c4e496fa916cb9a484a649aa1b4cebd6550f2
Author: Hongyu Wang 
Date:   Fri Jul 26 08:27:01 2024 +0800

i386: Mark target option with optimization when enabled with opt level 
[PR116065]

When introducing munroll-only-small-loops, the option was marked as
Target Save and added to -O2 default which makes attribute(optimize)
resets target option and causing error when cmdline has O1 and
funciton attribute has O2 and other target options. Mark this option
as Optimization to fix.

gcc/ChangeLog

PR target/116065
* config/i386/i386.opt (munroll-only-small-loops): Mark as
Optimization instead of Save.

gcc/testsuite/ChangeLog

PR target/116065
* gcc.target/i386/pr116065.c: New test.

Diff:
---
 gcc/config/i386/i386.opt |  2 +-
 gcc/testsuite/gcc.target/i386/pr116065.c | 24 
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index 353fffb23430..52054bc018ad 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -1259,7 +1259,7 @@ Target Mask(ISA2_RAOINT) Var(ix86_isa_flags2) Save
 Support RAOINT built-in functions and code generation.
 
 munroll-only-small-loops
-Target Var(ix86_unroll_only_small_loops) Init(0) Save
+Target Var(ix86_unroll_only_small_loops) Init(0) Optimization
 Enable conservative small loop unrolling.
 
 mlam=
diff --git a/gcc/testsuite/gcc.target/i386/pr116065.c 
b/gcc/testsuite/gcc.target/i386/pr116065.c
new file mode 100644
index ..083e70f2413f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr116065.c
@@ -0,0 +1,24 @@
+/* PR target/116065  */
+/* { dg-do compile } */
+/* { dg-options "-O1 -mno-avx" } */
+
+#ifndef __AVX__
+#pragma GCC push_options
+#pragma GCC target("avx")
+#define __DISABLE_AVX__
+#endif /* __AVX__ */
+
+extern inline double __attribute__((__gnu_inline__,__always_inline__))
+ foo (double x) { return x; }
+
+#ifdef __DISABLE_AVX__
+#undef __DISABLE_AVX__
+#pragma GCC pop_options
+#endif /* __DISABLE_AVX__ */
+
+void __attribute__((target ("avx"), optimize(3)))
+bar (double *p)
+{
+  *p = foo (*p);
+}
+

[gcc r15-2431] middle-end/101478 - ICE with degenerate address during gimplification

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:33ead6400ad59d4b38fa0527a9a7b53a28114ab7

commit r15-2431-g33ead6400ad59d4b38fa0527a9a7b53a28114ab7
Author: Richard Biener 
Date:   Wed Jul 31 10:07:45 2024 +0200

middle-end/101478 - ICE with degenerate address during gimplification

When we gimplify &MEM[0B + 4] we are re-folding the address in case
types are not canonical which ends up with a constant address that
recompute_tree_invariant_for_addr_expr ICEs on.  Properly guard
that call.

PR middle-end/101478
* gimplify.cc (gimplify_addr_expr): Check we still have an
ADDR_EXPR before calling recompute_tree_invariant_for_addr_expr.

* gcc.dg/pr101478.c: New testcase.

Diff:
---
 gcc/gimplify.cc |  3 ++-
 gcc/testsuite/gcc.dg/pr101478.c | 11 +++
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/gcc/gimplify.cc b/gcc/gimplify.cc
index ab323d764e8c..c77a53bdfcee 100644
--- a/gcc/gimplify.cc
+++ b/gcc/gimplify.cc
@@ -6980,7 +6980,8 @@ gimplify_addr_expr (tree *expr_p, gimple_seq *pre_p, 
gimple_seq *post_p)
*expr_p = build_fold_addr_expr (op0);
 
   /* Make sure TREE_CONSTANT and TREE_SIDE_EFFECTS are set properly.  */
-  recompute_tree_invariant_for_addr_expr (*expr_p);
+  if (TREE_CODE (*expr_p) == ADDR_EXPR)
+   recompute_tree_invariant_for_addr_expr (*expr_p);
 
   /* If we re-built the ADDR_EXPR add a conversion to the original type
  if required.  */
diff --git a/gcc/testsuite/gcc.dg/pr101478.c b/gcc/testsuite/gcc.dg/pr101478.c
new file mode 100644
index ..527620ea0f11
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr101478.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "" } */
+
+struct obj {
+  int n;
+  int l;
+};
+int main()
+{
+  (struct obj *)((char *)(__SIZE_TYPE__)({ 0; }) - (char *)&((struct obj 
*)0)->l);
+}

[gcc r15-2432] LoongArch: Relax ins_zero_bitmask_operand and remove and3_align

[Xi Ruoyao via Gcc-cvs]

https://gcc.gnu.org/g:70a4e79dc9ed73b056aa0362f61302e04227049f

commit r15-2432-g70a4e79dc9ed73b056aa0362f61302e04227049f
Author: Xi Ruoyao 
Date:   Sun Jul 28 17:02:49 2024 +0800

LoongArch: Relax ins_zero_bitmask_operand and remove and3_align

In r15-1207 I was too stupid to realize we just need to relax
ins_zero_bitmask_operand to allow using bstrins for aligning, instead of
adding a new split.  And, "> 12" in ins_zero_bitmask_operand also makes
no sense: it rejects bstrins for things like "x & ~4l" with no good
reason.

So fix my errors now.

gcc/ChangeLog:

* config/loongarch/predicates.md (ins_zero_bitmask_operand):
Cover more cases that bstrins can benefit.
(high_bitmask_operand): Remove.
* config/loongarch/constraints.md (Yy): Remove.
* config/loongarch/loongarch.md (and3_align): Remove.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/bstrins-4.c: New test.

Diff:
---
 gcc/config/loongarch/constraints.md|  4 
 gcc/config/loongarch/loongarch.md  | 17 -
 gcc/config/loongarch/predicates.md |  9 ++---
 gcc/testsuite/gcc.target/loongarch/bstrins-4.c |  9 +
 4 files changed, 11 insertions(+), 28 deletions(-)

diff --git a/gcc/config/loongarch/constraints.md 
b/gcc/config/loongarch/constraints.md
index 12cf5e2924a3..18da8b31f499 100644
--- a/gcc/config/loongarch/constraints.md
+++ b/gcc/config/loongarch/constraints.md
@@ -292,10 +292,6 @@
"@internal"
(match_operand 0 "low_bitmask_operand"))
 
-(define_constraint "Yy"
-   "@internal"
-   (match_operand 0 "high_bitmask_operand"))
-
 (define_constraint "YI"
   "@internal
A replicated vector const in which the replicated value is in the range
diff --git a/gcc/config/loongarch/loongarch.md 
b/gcc/config/loongarch/loongarch.md
index 9bad79bbf45e..280d1c403c46 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -1588,23 +1588,6 @@
   [(set_attr "move_type" "pick_ins")
(set_attr "mode" "")])
 
-(define_insn_and_split "and3_align"
-  [(set (match_operand:GPR 0 "register_operand" "=r")
-   (and:GPR (match_operand:GPR 1 "register_operand" "r")
-(match_operand:GPR 2 "high_bitmask_operand" "Yy")))]
-  ""
-  "#"
-  ""
-  [(set (match_dup 0) (match_dup 1))
-   (set (zero_extract:GPR (match_dup 0) (match_dup 2) (const_int 0))
-   (const_int 0))]
-{
-  int len;
-
-  len = low_bitmask_len (mode, ~INTVAL (operands[2]));
-  operands[2] = GEN_INT (len);
-})
-
 (define_insn_and_split "*bstrins__for_mask"
   [(set (match_operand:GPR 0 "register_operand" "=r")
(and:GPR (match_operand:GPR 1 "register_operand" "r")
diff --git a/gcc/config/loongarch/predicates.md 
b/gcc/config/loongarch/predicates.md
index 58e406ea522b..95c2544cc2f2 100644
--- a/gcc/config/loongarch/predicates.md
+++ b/gcc/config/loongarch/predicates.md
@@ -293,10 +293,6 @@
   (and (match_code "const_int")
(match_test "low_bitmask_len (mode, INTVAL (op)) > 12")))
 
-(define_predicate "high_bitmask_operand"
-  (and (match_code "const_int")
-   (match_test "low_bitmask_len (mode, ~INTVAL (op)) > 0")))
-
 (define_predicate "d_operand"
   (and (match_code "reg")
(match_test "GP_REG_P (REGNO (op))")))
@@ -406,11 +402,10 @@
 
 (define_predicate "ins_zero_bitmask_operand"
   (and (match_code "const_int")
-   (match_test "INTVAL (op) != -1")
-   (match_test "INTVAL (op) & 1")
(match_test "low_bitmask_len (mode, \
 ~UINTVAL (op) | (~UINTVAL(op) - 1)) \
-   > 12")))
+   > 0")
+   (not (match_operand 0 "const_uns_arith_operand"
 
 (define_predicate "const_call_insn_operand"
   (match_code "const,symbol_ref,label_ref")
diff --git a/gcc/testsuite/gcc.target/loongarch/bstrins-4.c 
b/gcc/testsuite/gcc.target/loongarch/bstrins-4.c
new file mode 100644
index ..0823cfc386e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/bstrins-4.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d" } */
+/* { dg-final { scan-assembler "bstrins\\.d\t\\\$r4,\\\$r0,2,2" } } */
+
+long
+x (long a)
+{
+  return a & ~4;
+}

[gcc r15-2433] LoongArch: Rework bswap{hi,si,di}2 definition

[Xi Ruoyao via Gcc-cvs]

https://gcc.gnu.org/g:996c2e2144c4a534b65424170c596dcbf44ba6db

commit r15-2433-g996c2e2144c4a534b65424170c596dcbf44ba6db
Author: Xi Ruoyao 
Date:   Sun Jul 28 19:57:02 2024 +0800

LoongArch: Rework bswap{hi,si,di}2 definition

Per a gcc-help thread we are generating sub-optimal code for
__builtin_bswap{32,64}.  To fix it:

- Use a single revb.d instruction for bswapdi2.
- Use a single revb.2w instruction for bswapsi2 for TARGET_64BIT,
  revb.2h + rotri.w for !TARGET_64BIT.
- Use a single revb.2h instruction for bswapsi2 (x) r>> 16, and a single
  revb.2w instruction for bswapdi2 (x) r>> 32.

Unfortunately I cannot figure out a way to make the compiler generate
revb.4h or revh.{2w,d} instructions.

gcc/ChangeLog:

* config/loongarch/loongarch.md (UNSPEC_REVB_2H, UNSPEC_REVB_4H,
UNSPEC_REVH_D): Remove UNSPECs.
(revb_4h, revh_d): Remove define_insn.
(revb_2h): Define as (rotatert:SI (bswap:SI x) 16) instead of
an UNSPEC.
(revb_2h_extend, revb_2w, *bswapsi2, bswapdi2): New define_insn.
(bswapsi2): Change to define_expand.  Only expand to revb.2h +
rotri.w if !TARGET_64BIT.
(bswapdi2): Change to define_insn of which the output is just a
revb.d instruction.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/revb.c: New test.

Diff:
---
 gcc/config/loongarch/loongarch.md | 79 +--
 gcc/testsuite/gcc.target/loongarch/revb.c | 61 
 2 files changed, 104 insertions(+), 36 deletions(-)

diff --git a/gcc/config/loongarch/loongarch.md 
b/gcc/config/loongarch/loongarch.md
index 280d1c403c46..ee0310f2bd60 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -20,11 +20,6 @@
 ;; .
 
 (define_c_enum "unspec" [
-  ;; Integer operations that are too cumbersome to describe directly.
-  UNSPEC_REVB_2H
-  UNSPEC_REVB_4H
-  UNSPEC_REVH_D
-
   ;; Floating-point moves.
   UNSPEC_LOAD_LOW
   UNSPEC_LOAD_HIGH
@@ -3151,55 +3146,67 @@
 
 ;; Reverse the order of bytes of operand 1 and store the result in operand 0.
 
-(define_insn "bswaphi2"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-   (bswap:HI (match_operand:HI 1 "register_operand" "r")))]
+(define_insn "revb_2h"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+   (rotatert:SI (bswap:SI (match_operand:SI 1 "register_operand" "r"))
+(const_int 16)))]
   ""
   "revb.2h\t%0,%1"
   [(set_attr "type" "shift")])
 
-(define_insn_and_split "bswapsi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-   (bswap:SI (match_operand:SI 1 "register_operand" "r")))]
-  ""
-  "#"
-  ""
-  [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_REVB_2H))
-   (set (match_dup 0) (rotatert:SI (match_dup 0) (const_int 16)))]
-  ""
-  [(set_attr "insn_count" "2")])
-
-(define_insn_and_split "bswapdi2"
+(define_insn "revb_2h_extend"
   [(set (match_operand:DI 0 "register_operand" "=r")
-   (bswap:DI (match_operand:DI 1 "register_operand" "r")))]
+   (sign_extend:DI
+ (rotatert:SI
+   (bswap:SI (match_operand:SI 1 "register_operand" "r"))
+   (const_int 16]
   "TARGET_64BIT"
-  "#"
-  ""
-  [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_REVB_4H))
-   (set (match_dup 0) (unspec:DI [(match_dup 0)] UNSPEC_REVH_D))]
-  ""
-  [(set_attr "insn_count" "2")])
+  "revb.2h\t%0,%1"
+  [(set_attr "type" "shift")])
 
-(define_insn "revb_2h"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-   (unspec:SI [(match_operand:SI 1 "register_operand" "r")] 
UNSPEC_REVB_2H))]
+(define_insn "bswaphi2"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+   (bswap:HI (match_operand:HI 1 "register_operand" "r")))]
   ""
   "revb.2h\t%0,%1"
   [(set_attr "type" "shift")])
 
-(define_insn "revb_4h"
+(define_insn "revb_2w"
   [(set (match_operand:DI 0 "register_operand" "=r")
-   (unspec:DI [(match_operand:DI 1 "register_operand" "r")] 
UNSPEC_REVB_4H))]
+   (rotatert:DI (bswap:DI (match_operand:DI 1 "register_operand" "r"))
+(const_int 32)))]
   "TARGET_64BIT"
-  "revb.4h\t%0,%1"
+  "revb.2w\t%0,%1"
   [(set_attr "type" "shift")])
 
-(define_insn "revh_d"
+(define_insn "*bswapsi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+   (bswap:SI (match_operand:SI 1 "register_operand" "r")))]
+  "TARGET_64BIT"
+  "revb.2w\t%0,%1"
+  [(set_attr "type" "shift")])
+
+(define_expand "bswapsi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+   (bswap:SI (match_operand:SI 1 "register_operand" "r")))]
+  ""
+{
+  if (!TARGET_64BIT)
+{
+  rtx t = gen_reg_rtx (SImode);
+  emit_insn (gen_revb_2h (t, operands[1]));
+  emit_insn (gen_rotrsi3 (operands[0], t, GEN_INT (16)));
+  DONE;
+}
+})
+
+(define_insn "bswapdi2"
   [(set (match_operand:DI 

[gcc] Created branch 'mikael/heads/inline_minmaxloc_without_dim_v08' in namespace 'refs/users'

[Mikael Morin via Gcc-cvs]

The branch 'mikael/heads/inline_minmaxloc_without_dim_v08' was created in 
namespace 'refs/users' pointing to:

 b8a4ddbd04b3... fortran: Continue MINLOC/MAXLOC second loop where the first

[gcc(refs/users/mikael/heads/inline_minmaxloc_without_dim_v08)] fortran: Add tests covering inline MINLOC/MAXLOC without DIM [PR90608]

[Mikael Morin via Gcc-cvs]

https://gcc.gnu.org/g:29c4b48d6b407d0eb410235169cf1ae9d63a0179

commit 29c4b48d6b407d0eb410235169cf1ae9d63a0179
Author: Mikael Morin 
Date:   Wed Jul 31 10:09:25 2024 +0200

fortran: Add tests covering inline MINLOC/MAXLOC without DIM [PR90608]

Tested on x86_64-pc-linux-gnu.
OK for master?

-- >8 --

Add the tests covering the various cases for which we are about to implement
inline expansion of MINLOC and MAXLOC.  Those are cases where the DIM
argument is not present.

PR fortran/90608

gcc/testsuite/ChangeLog:

* gfortran.dg/maxloc_7.f90: New test.
* gfortran.dg/maxloc_with_mask_1.f90: New test.
* gfortran.dg/minloc_8.f90: New test.
* gfortran.dg/minloc_with_mask_1.f90: New test.

Diff:
---
 gcc/testsuite/gfortran.dg/maxloc_7.f90   | 220 +
 gcc/testsuite/gfortran.dg/maxloc_with_mask_1.f90 | 393 +++
 gcc/testsuite/gfortran.dg/minloc_8.f90   | 220 +
 gcc/testsuite/gfortran.dg/minloc_with_mask_1.f90 | 392 ++
 4 files changed, 1225 insertions(+)

diff --git a/gcc/testsuite/gfortran.dg/maxloc_7.f90 
b/gcc/testsuite/gfortran.dg/maxloc_7.f90
new file mode 100644
index ..a875083052a9
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/maxloc_7.f90
@@ -0,0 +1,220 @@
+! { dg-do run }
+!
+! PR fortran/90608
+! Check the correct behaviour of the inline maxloc implementation,
+! when there is no optional argument.
+
+program p
+  implicit none
+  integer, parameter :: data5(*) = (/ 1, 7, 2, 7, 0 /)
+  integer, parameter :: data64(*) = (/ 2, 5, 4, 6, 0, 9, 3, 5,  &
+   4, 4, 1, 7, 3, 2, 1, 2,  &
+   5, 4, 6, 0, 9, 3, 5, 4,  &
+   4, 1, 7, 3, 2, 1, 2, 5,  &
+   4, 6, 0, 9, 3, 5, 4, 4,  &
+   1, 7, 3, 2, 1, 2, 5, 4,  &
+   6, 0, 9, 3, 5, 4, 4, 1,  &
+   7, 3, 2, 1, 2, 5, 4, 6  /)
+  call check_int_const_shape_rank_1
+  call check_int_const_shape_rank_3
+  call check_int_const_shape_empty_4
+  call check_int_alloc_rank_1
+  call check_int_alloc_rank_3
+  call check_int_alloc_empty_4
+  call check_real_const_shape_rank_1
+  call check_real_const_shape_rank_3
+  call check_real_const_shape_empty_4
+  call check_real_alloc_rank_1
+  call check_real_alloc_rank_3
+  call check_real_alloc_empty_4
+  call check_int_lower_bounds
+  call check_real_lower_bounds
+  call check_all_nans
+  call check_dependencies
+contains
+  subroutine check_int_const_shape_rank_1()
+integer :: a(5)
+integer, allocatable :: m(:)
+a = data5
+m = maxloc(a)
+if (size(m, dim=1) /= 1) stop 11
+if (any(m /= (/ 2 /))) stop 12
+  end subroutine
+  subroutine check_int_const_shape_rank_3()
+integer :: a(4,4,4)
+integer, allocatable :: m(:)
+a = reshape(data64, shape(a))
+m = maxloc(a)
+if (size(m, dim=1) /= 3) stop 21
+if (any(m /= (/ 2, 2, 1 /))) stop 22
+  end subroutine
+  subroutine check_int_const_shape_empty_4()
+integer :: a(9,3,0,7)
+integer, allocatable :: m(:)
+a = reshape((/ integer:: /), shape(a))
+m = maxloc(a)
+if (size(m, dim=1) /= 4) stop 31
+if (any(m /= (/ 0, 0, 0, 0 /))) stop 32
+  end subroutine
+  subroutine check_int_alloc_rank_1()
+integer, allocatable :: a(:)
+integer, allocatable :: m(:)
+allocate(a(5))
+a(:) = data5
+m = maxloc(a)
+if (size(m, dim=1) /= 1) stop 41
+if (any(m /= (/ 2 /))) stop 42
+  end subroutine
+  subroutine check_int_alloc_rank_3()
+integer, allocatable :: a(:,:,:)
+integer, allocatable :: m(:)
+allocate(a(4,4,4))
+a(:,:,:) = reshape(data64, shape(a))
+m = maxloc(a)
+if (size(m, dim=1) /= 3) stop 51
+if (any(m /= (/ 2, 2, 1 /))) stop 52
+  end subroutine
+  subroutine check_int_alloc_empty_4()
+integer, allocatable :: a(:,:,:,:)
+integer, allocatable :: m(:)
+allocate(a(9,3,0,7))
+a(:,:,:,:) = reshape((/ integer:: /), shape(a))
+m = maxloc(a)
+if (size(m, dim=1) /= 4) stop 61
+if (any(m /= (/ 0, 0, 0, 0 /))) stop 62
+  end subroutine
+  subroutine check_real_const_shape_rank_1()
+real :: a(5)
+integer, allocatable :: m(:)
+a = (/ real:: data5 /)
+m = maxloc(a)
+if (size(m, dim=1) /= 1) stop 71
+if (any(m /= (/ 2 /))) stop 72
+  end subroutine
+  subroutine check_real_const_shape_rank_3()
+real :: a(4,4,4)
+integer, allocatable :: m(:)
+a = reshape((/ real:: data64 /), shape(a))
+m = maxloc(a)
+if (size(m, dim=1) /= 3) stop 81
+if (any(m /= (/ 2, 2, 1 /))) stop 82
+  end subroutine
+  subroutine check_real_const_shape_empty_4()
+real :: a(9,3,0,7)
+integer, allocatable :: m(:)
+a = reshape((/ real:: /), shape(a))
+m = maxloc(a)
+if (size(m, dim=1)

[gcc(refs/users/mikael/heads/inline_minmaxloc_without_dim_v08)] fortran: Inline MINLOC/MAXLOC with no DIM and ARRAY of rank 1 [PR90608]

[Mikael Morin via Gcc-cvs]

https://gcc.gnu.org/g:c272e51bf329761491185835bf26f5a8a53c0247

commit c272e51bf329761491185835bf26f5a8a53c0247
Author: Mikael Morin 
Date:   Wed Jul 31 10:09:53 2024 +0200

fortran: Inline MINLOC/MAXLOC with no DIM and ARRAY of rank 1 [PR90608]

Regression-tested on x86_64-pc-linux-gnu.
OK for master?

-- >8 --

Enable inline code generation for the MINLOC and MAXLOC intrinsic, if the
DIM argument is not present and ARRAY has rank 1.  This case is similar to
the case where the result is scalar (DIM present and rank 1 ARRAY), which
already supports inline expansion of the intrinsic.  Both cases return
the same value, with the difference that the result is an array of size 1 if
DIM is absent, whereas it's a scalar if DIM  is present.  So all there is
to do for the new case to work is hook the inline expansion with the
scalarizer.

PR fortran/90608

gcc/fortran/ChangeLog:

* trans-array.cc (gfc_conv_ss_startstride): Set the scalarization
rank based on the MINLOC/MAXLOC rank if needed.  Call the inline
code generation and setup the scalarizer array descriptor info
in the MINLOC and MAXLOC cases.
* trans-intrinsic.cc (gfc_conv_intrinsic_minmaxloc): Return the
result array element if the scalarizer is setup and we are inside
the loops.  Restrict library function call dispatch to the case
where inline expansion is not supported.  Declare an array result
if the expression isn't scalar.  Initialize the array result single
element and return the result variable if the expression isn't
scalar.
(walk_inline_intrinsic_minmaxloc): New function.
(walk_inline_intrinsic_function): Add MINLOC and MAXLOC cases,
dispatching to walk_inline_intrinsic_minmaxloc.
(gfc_add_intrinsic_ss_code): Add MINLOC and MAXLOC cases.
(gfc_inline_intrinsic_function_p): Return true if ARRAY has rank 1,
regardless of DIM.

Diff:
---
 gcc/fortran/trans-array.cc |  25 ++
 gcc/fortran/trans-intrinsic.cc | 198 +++--
 2 files changed, 155 insertions(+), 68 deletions(-)

diff --git a/gcc/fortran/trans-array.cc b/gcc/fortran/trans-array.cc
index c93a5f1e7543..0c78e1fecd8f 100644
--- a/gcc/fortran/trans-array.cc
+++ b/gcc/fortran/trans-array.cc
@@ -4771,6 +4771,8 @@ gfc_conv_ss_startstride (gfc_loopinfo * loop)
case GFC_ISYM_UBOUND:
case GFC_ISYM_LCOBOUND:
case GFC_ISYM_UCOBOUND:
+   case GFC_ISYM_MAXLOC:
+   case GFC_ISYM_MINLOC:
case GFC_ISYM_SHAPE:
case GFC_ISYM_THIS_IMAGE:
  loop->dimen = ss->dimen;
@@ -4820,6 +4822,29 @@ done:
case GFC_SS_INTRINSIC:
  switch (expr->value.function.isym->id)
{
+   case GFC_ISYM_MINLOC:
+   case GFC_ISYM_MAXLOC:
+ {
+   gfc_se se;
+   gfc_init_se (&se, nullptr);
+   se.loop = loop;
+   se.ss = ss;
+   gfc_conv_intrinsic_function (&se, expr);
+   gfc_add_block_to_block (&outer_loop->pre, &se.pre);
+   gfc_add_block_to_block (&outer_loop->post, &se.post);
+
+   info->descriptor = se.expr;
+
+   info->data = gfc_conv_array_data (info->descriptor);
+   info->data = gfc_evaluate_now (info->data, &outer_loop->pre);
+
+   info->offset = gfc_index_zero_node;
+   info->start[0] = gfc_index_zero_node;
+   info->end[0] = gfc_index_zero_node;
+   info->stride[0] = gfc_index_one_node;
+   continue;
+ }
+
/* Fall through to supply start and stride.  */
case GFC_ISYM_LBOUND:
case GFC_ISYM_UBOUND:
diff --git a/gcc/fortran/trans-intrinsic.cc b/gcc/fortran/trans-intrinsic.cc
index cc0d00f4e399..a947dd1ba0b2 100644
--- a/gcc/fortran/trans-intrinsic.cc
+++ b/gcc/fortran/trans-intrinsic.cc
@@ -5273,66 +5273,69 @@ strip_kind_from_actual (gfc_actual_arglist * actual)
we need to handle.  For performance reasons we sometimes create two
loops instead of one, where the second one is much simpler.
Examples for minloc intrinsic:
-   1) Result is an array, a call is generated
-   2) Array mask is used and NaNs need to be supported:
-  limit = Infinity;
-  pos = 0;
-  S = from;
-  while (S <= to) {
-   if (mask[S]) {
- if (pos == 0) pos = S + (1 - from);
- if (a[S] <= limit) { limit = a[S]; pos = S + (1 - from); goto lab1; }
-   }
-   S++;
-  }
-  goto lab2;
-  lab1:;
-  while (S <= to) {
-   if (mask[S]) if (a[S] < limit) { limit = a[S]; pos = S + (1 - from); }
-   S++;
-  }
-  lab2:;
-   3) NaNs need to be supported, but it is known at compile time or cheaply
- 

[gcc(refs/users/mikael/heads/inline_minmaxloc_without_dim_v08)] fortran: Disable frontend passes for MINLOC/MAXLOC if it's inlined

[Mikael Morin via Gcc-cvs]

https://gcc.gnu.org/g:41e22a74ed2a25592a4618d57b1c4af228546cf8

commit 41e22a74ed2a25592a4618d57b1c4af228546cf8
Author: Mikael Morin 
Date:   Wed Jul 31 10:09:39 2024 +0200

fortran: Disable frontend passes for MINLOC/MAXLOC if it's inlined

Regression-tested on x86_64-pc-linux-gnu.
OK for master?

-- >8 --

Disable rewriting of MINLOC/MAXLOC expressions for which inline code
generation is supported.  Update the gfc_inline_intrinsic_function_p
predicate (already existing) for that, with the current state of
MINLOC/MAXLOC inlining support, that is only the cases of a scalar
result and non-CHARACTER argument for now.

This change has no effect currently, as the MINLOC/MAXLOC front-end passes
only change expressions of rank 1, but the inlining control predicate
gfc_inline_intrinsic_function_p returns false for those.  However, later
changes will extend MINLOC/MAXLOC inline expansion support to array
expressions and update the inlining control predicate, and this will become
effective.

gcc/fortran/ChangeLog:

* frontend-passes.cc (optimize_minmaxloc): Skip if we can generate
inline code for the unmodified expression.
* trans-intrinsic.cc (gfc_inline_intrinsic_function_p): Add
MINLOC and MAXLOC cases.

Diff:
---
 gcc/fortran/frontend-passes.cc |  3 ++-
 gcc/fortran/trans-intrinsic.cc | 23 +++
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/gcc/fortran/frontend-passes.cc b/gcc/fortran/frontend-passes.cc
index 3c06018fdbbf..8e4c6310ba8d 100644
--- a/gcc/fortran/frontend-passes.cc
+++ b/gcc/fortran/frontend-passes.cc
@@ -2277,7 +2277,8 @@ optimize_minmaxloc (gfc_expr **e)
   || fn->value.function.actual == NULL
   || fn->value.function.actual->expr == NULL
   || fn->value.function.actual->expr->ts.type == BT_CHARACTER
-  || fn->value.function.actual->expr->rank != 1)
+  || fn->value.function.actual->expr->rank != 1
+  || gfc_inline_intrinsic_function_p (fn))
 return;
 
   *e = gfc_get_array_expr (fn->ts.type, fn->ts.kind, &fn->where);
diff --git a/gcc/fortran/trans-intrinsic.cc b/gcc/fortran/trans-intrinsic.cc
index 9f3c3ce47bc5..cc0d00f4e399 100644
--- a/gcc/fortran/trans-intrinsic.cc
+++ b/gcc/fortran/trans-intrinsic.cc
@@ -11650,6 +11650,29 @@ gfc_inline_intrinsic_function_p (gfc_expr *expr)
 case GFC_ISYM_TRANSPOSE:
   return true;
 
+case GFC_ISYM_MINLOC:
+case GFC_ISYM_MAXLOC:
+  {
+   /* Disable inline expansion if code size matters.  */
+   if (optimize_size)
+ return false;
+
+   gfc_actual_arglist *array_arg = expr->value.function.actual;
+   gfc_actual_arglist *dim_arg = array_arg->next;
+
+   gfc_expr *array = array_arg->expr;
+   gfc_expr *dim = dim_arg->expr;
+
+   if (!(array->ts.type == BT_INTEGER
+ || array->ts.type == BT_REAL))
+ return false;
+
+   if (array->rank == 1 && dim != nullptr)
+ return true;
+
+   return false;
+  }
+
 default:
   return false;
 }

[gcc(refs/users/mikael/heads/inline_minmaxloc_without_dim_v08)] fortran: Outline array bound check generation code

[Mikael Morin via Gcc-cvs]

https://gcc.gnu.org/g:fc60928404feeb01833a25da79518a60e80c5ede

commit fc60928404feeb01833a25da79518a60e80c5ede
Author: Mikael Morin 
Date:   Wed Jul 31 10:10:06 2024 +0200

fortran: Outline array bound check generation code

The next patch will need reindenting of the array bound check generation
code.  This outlines it to its own function beforehand, reducing the churn
in the next patch.

Regression-tested on x86_64-pc-linux-gnu.
OK for master?

-- >8 --

gcc/fortran/ChangeLog:

* trans-array.cc (gfc_conv_ss_startstride): Move array bound check
generation code...
(add_check_section_in_array_bounds): ... here as a new function.

Diff:
---
 gcc/fortran/trans-array.cc | 297 ++---
 1 file changed, 143 insertions(+), 154 deletions(-)

diff --git a/gcc/fortran/trans-array.cc b/gcc/fortran/trans-array.cc
index 0c78e1fecd8f..99a603a3afb2 100644
--- a/gcc/fortran/trans-array.cc
+++ b/gcc/fortran/trans-array.cc
@@ -4736,6 +4736,146 @@ gfc_conv_section_startstride (stmtblock_t * block, 
gfc_ss * ss, int dim)
 }
 
 
+/* Generate in INNER the bounds checking code along the dimension DIM for
+   the array associated with SS_INFO.  */
+
+static void
+add_check_section_in_array_bounds (stmtblock_t *inner, gfc_ss_info *ss_info,
+  int dim)
+{
+  gfc_expr *expr = ss_info->expr;
+  locus *expr_loc = &expr->where;
+  const char *expr_name = expr->symtree->name;
+
+  gfc_array_info *info = &ss_info->data.array;
+
+  bool check_upper;
+  if (dim == info->ref->u.ar.dimen - 1
+  && info->ref->u.ar.as->type == AS_ASSUMED_SIZE)
+check_upper = false;
+  else
+check_upper = true;
+
+  /* Zero stride is not allowed.  */
+  tree tmp = fold_build2_loc (input_location, EQ_EXPR, logical_type_node,
+ info->stride[dim], gfc_index_zero_node);
+  char * msg = xasprintf ("Zero stride is not allowed, for dimension %d "
+ "of array '%s'", dim + 1, expr_name);
+  gfc_trans_runtime_check (true, false, tmp, inner, expr_loc, msg);
+  free (msg);
+
+  tree desc = info->descriptor;
+
+  /* This is the run-time equivalent of resolve.cc's
+ check_dimension.  The logical is more readable there
+ than it is here, with all the trees.  */
+  tree lbound = gfc_conv_array_lbound (desc, dim);
+  tree end = info->end[dim];
+  tree ubound = check_upper ? gfc_conv_array_ubound (desc, dim) : NULL_TREE;
+
+  /* non_zerosized is true when the selected range is not
+ empty.  */
+  tree stride_pos = fold_build2_loc (input_location, GT_EXPR, 
logical_type_node,
+info->stride[dim], gfc_index_zero_node);
+  tmp = fold_build2_loc (input_location, LE_EXPR, logical_type_node,
+info->start[dim], end);
+  stride_pos = fold_build2_loc (input_location, TRUTH_AND_EXPR,
+   logical_type_node, stride_pos, tmp);
+
+  tree stride_neg = fold_build2_loc (input_location, LT_EXPR, 
logical_type_node,
+info->stride[dim], gfc_index_zero_node);
+  tmp = fold_build2_loc (input_location, GE_EXPR, logical_type_node,
+info->start[dim], end);
+  stride_neg = fold_build2_loc (input_location, TRUTH_AND_EXPR,
+   logical_type_node, stride_neg, tmp);
+  tree non_zerosized = fold_build2_loc (input_location, TRUTH_OR_EXPR,
+   logical_type_node, stride_pos,
+   stride_neg);
+
+  /* Check the start of the range against the lower and upper
+ bounds of the array, if the range is not empty.
+ If upper bound is present, include both bounds in the
+ error message.  */
+  if (check_upper)
+{
+  tmp = fold_build2_loc (input_location, LT_EXPR, logical_type_node,
+info->start[dim], lbound);
+  tmp = fold_build2_loc (input_location, TRUTH_AND_EXPR, logical_type_node,
+non_zerosized, tmp);
+  tree tmp2 = fold_build2_loc (input_location, GT_EXPR, logical_type_node,
+  info->start[dim], ubound);
+  tmp2 = fold_build2_loc (input_location, TRUTH_AND_EXPR, 
logical_type_node,
+ non_zerosized, tmp2);
+  msg = xasprintf ("Index '%%ld' of dimension %d of array '%s' outside of "
+  "expected range (%%ld:%%ld)", dim + 1, expr_name);
+  gfc_trans_runtime_check (true, false, tmp, inner, expr_loc, msg,
+ fold_convert (long_integer_type_node, info->start[dim]),
+ fold_convert (long_integer_type_node, lbound),
+ fold_convert (long_integer_type_node, ubound));
+  gfc_trans_runtime_check (true, false, tmp2, inner, expr_loc, msg,
+ fold_convert (long_integer_type_node, info->start[dim]),
+ fold_convert (long_integer_type_node, lbound),
+

[gcc(refs/users/mikael/heads/inline_minmaxloc_without_dim_v08)] fortran: Inline integral MINLOC/MAXLOC with no DIM and no MASK [PR90608]

[Mikael Morin via Gcc-cvs]

https://gcc.gnu.org/g:7738e6287f90905786a7ecb31238978efba6923d

commit 7738e6287f90905786a7ecb31238978efba6923d
Author: Mikael Morin 
Date:   Wed Jul 31 10:10:19 2024 +0200

fortran: Inline integral MINLOC/MAXLOC with no DIM and no MASK [PR90608]

Regression-tested on x86_64-pc-linux-gnu.
OK for master?

-- >8 --

Enable generation of inline code for the MINLOC and MAXLOC intrinsic,
if the ARRAY argument is of integral type and of any rank (only the rank 1
case was previously inlined), and neither DIM nor MASK arguments are
present.

This needs a few adjustments in gfc_conv_intrinsic_minmaxloc,
mainly to replace the single variables POS and OFFSET, with collections
of variables, one variable per dimension each.

The restriction to integral ARRAY and absent MASK limits the scope of
the change to the cases where we generate single loop inline code.  The
code generation for the second loop is only accessible with ARRAY of rank
1, so it can continue using a single variable.  A later change will extend
inlining to the double loop cases.

There is some bounds checking code that was previously handled by the
library, and that needed some changes in the scalarizer to avoid regressing.
The bounds check code generation was already supported by the scalarizer,
but it was only applying to array reference sections, checking both
for array bound violation and for shape conformability between all the
involved arrays.  With this change, for MINLOC or MAXLOC, enable the
conformability check between all the scalarized arrays, and disable the
array bound violation check.

PR fortran/90608

gcc/fortran/ChangeLog:

* trans-array.cc (gfc_conv_ss_startstride): Set the MINLOC/MAXLOC
result upper bound using the rank of the ARRAY argument.  Ajdust
the error message for intrinsic result arrays.  Only check array
bounds for array references.  Move bound check decision code...
(bounds_check_needed): ... here as a new predicate.  Allow bound
check for MINLOC/MAXLOC intrinsic results.
* trans-intrinsic.cc (gfc_conv_intrinsic_minmaxloc): Change the
result array upper bound to the rank of ARRAY.  Update the NONEMPTY
variable to depend on the non-empty extent of every dimension.  Use
one variable per dimension instead of a single variable for the
position and the offset.  Update their declaration, initialization,
and update to affect the variable of each dimension.  Use the first
variable only in areas only accessed with rank 1 ARRAY argument.
Set every element of the result using its corresponding variable.
(gfc_inline_intrinsic_function_p): Return true for integral ARRAY
and absent DIM and MASK.

gcc/testsuite/ChangeLog:

* gfortran.dg/maxloc_bounds_4.f90: Additionally accept the error
message emitted by the scalarizer.

Diff:
---
 gcc/fortran/trans-array.cc|  68 +---
 gcc/fortran/trans-intrinsic.cc| 150 +++---
 gcc/testsuite/gfortran.dg/maxloc_bounds_4.f90 |   4 +-
 3 files changed, 165 insertions(+), 57 deletions(-)

diff --git a/gcc/fortran/trans-array.cc b/gcc/fortran/trans-array.cc
index 99a603a3afb2..76448c8ac0e3 100644
--- a/gcc/fortran/trans-array.cc
+++ b/gcc/fortran/trans-array.cc
@@ -4876,6 +4876,35 @@ add_check_section_in_array_bounds (stmtblock_t *inner, 
gfc_ss_info *ss_info,
 }
 
 
+/* Tells whether we need to generate bounds checking code for the array
+   associated with SS.  */
+
+bool
+bounds_check_needed (gfc_ss *ss)
+{
+  /* Catch allocatable lhs in f2003.  */
+  if (flag_realloc_lhs && ss->no_bounds_check)
+return false;
+
+  gfc_ss_info *ss_info = ss->info;
+  if (ss_info->type == GFC_SS_SECTION)
+return true;
+
+  if (!(ss_info->type == GFC_SS_INTRINSIC
+   && ss_info->expr
+   && ss_info->expr->expr_type == EXPR_FUNCTION))
+return false;
+
+  gfc_intrinsic_sym *isym = ss_info->expr->value.function.isym;
+  if (!(isym
+   && (isym->id == GFC_ISYM_MAXLOC
+   || isym->id == GFC_ISYM_MINLOC)))
+return false;
+
+  return gfc_inline_intrinsic_function_p (ss_info->expr);
+}
+
+
 /* Calculates the range start and stride for a SS chain.  Also gets the
descriptor and data pointer.  The range of vector subscripts is the size
of the vector.  Array bounds are also checked.  */
@@ -4977,10 +5006,17 @@ done:
info->data = gfc_conv_array_data (info->descriptor);
info->data = gfc_evaluate_now (info->data, &outer_loop->pre);
 
-   info->offset = gfc_index_zero_node;
+   gfc_expr *array = expr->value.function.actual->expr;
+   tree rank = build_int_cst (gfc_array_index_type, array->rank);
+

[gcc(refs/users/mikael/heads/inline_minmaxloc_without_dim_v08)] fortran: Inline integral MINLOC/MAXLOC with no DIM and scalar MASK [PR90608]

[Mikael Morin via Gcc-cvs]

https://gcc.gnu.org/g:d3d4a1c4f55bdd97ed3acd4eda1547343d9b9066

commit d3d4a1c4f55bdd97ed3acd4eda1547343d9b9066
Author: Mikael Morin 
Date:   Wed Jul 31 10:10:33 2024 +0200

fortran: Inline integral MINLOC/MAXLOC with no DIM and scalar MASK [PR90608]

Regression-tested on x86_64-pc-linux-gnu.
OK for master?

-- >8 --

Enable the generation of inline code for MINLOC/MAXLOC when argument ARRAY
is of integral type, DIM is not present, and MASK is present and is scalar
(only absent MASK or rank 1 ARRAY were inlined before).

Scalar masks are implemented with a wrapping condition around the code one
would generate if MASK wasn't present, so they are easy to support once
inline code without MASK is working.

PR fortran/90608

gcc/fortran/ChangeLog:

* trans-intrinsic.cc (gfc_conv_intrinsic_minmaxloc): Generate
variable initialization for each dimension in the else branch of
the toplevel condition.
(gfc_inline_intrinsic_function_p): Return TRUE for scalar MASK.

gcc/testsuite/ChangeLog:

* gfortran.dg/maxloc_bounds_7.f90: Additionally accept the error 
message
reported by the scalarizer.

Diff:
---
 gcc/fortran/trans-intrinsic.cc| 13 -
 gcc/testsuite/gfortran.dg/maxloc_bounds_7.f90 |  4 ++--
 2 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/gcc/fortran/trans-intrinsic.cc b/gcc/fortran/trans-intrinsic.cc
index ac8bd2d48123..855208717973 100644
--- a/gcc/fortran/trans-intrinsic.cc
+++ b/gcc/fortran/trans-intrinsic.cc
@@ -5886,7 +5886,6 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * 
expr, enum tree_code op)
   /* For a scalar mask, enclose the loop in an if statement.  */
   if (maskexpr && maskss == NULL)
 {
-  gcc_assert (loop.dimen == 1);
   tree ifmask;
 
   gfc_init_se (&maskse, NULL);
@@ -5901,7 +5900,8 @@ gfc_conv_intrinsic_minmaxloc (gfc_se * se, gfc_expr * 
expr, enum tree_code op)
 the pos variable the same way as above.  */
 
   gfc_init_block (&elseblock);
-  gfc_add_modify (&elseblock, pos[0], gfc_index_zero_node);
+  for (int i = 0; i < loop.dimen; i++)
+   gfc_add_modify (&elseblock, pos[i], gfc_index_zero_node);
   elsetmp = gfc_finish_block (&elseblock);
   ifmask = conv_mask_condition (&maskse, maskexpr, optional_mask);
   tmp = build3_v (COND_EXPR, ifmask, tmp, elsetmp);
@@ -11795,9 +11795,12 @@ gfc_inline_intrinsic_function_p (gfc_expr *expr)
if (array->rank == 1)
  return true;
 
-   if (array->ts.type == BT_INTEGER
-   && dim == nullptr
-   && mask == nullptr)
+   if (array->ts.type != BT_INTEGER
+   || dim != nullptr)
+ return false;
+
+   if (mask == nullptr
+   || mask->rank == 0)
  return true;
 
return false;
diff --git a/gcc/testsuite/gfortran.dg/maxloc_bounds_7.f90 
b/gcc/testsuite/gfortran.dg/maxloc_bounds_7.f90
index 206a29b149da..3aa9d3dcebee 100644
--- a/gcc/testsuite/gfortran.dg/maxloc_bounds_7.f90
+++ b/gcc/testsuite/gfortran.dg/maxloc_bounds_7.f90
@@ -1,6 +1,6 @@
 ! { dg-do run }
 ! { dg-options "-fbounds-check" }
-! { dg-shouldfail "Incorrect extent in return value of MAXLOC intrinsic: is 3, 
should be 2" }
+! { dg-shouldfail "Incorrect extent in return value of MAXLOC intrinsic: is 3, 
should be 2|Array bound mismatch for dimension 1 of array 'res' .3/2." }
 module tst
 contains
   subroutine foo(res)
@@ -18,4 +18,4 @@ program main
   integer :: res(3)
   call foo(res)
 end program main
-! { dg-output "Fortran runtime error: Incorrect extent in return value of 
MAXLOC intrinsic: is 3, should be 2" }
+! { dg-output "Fortran runtime error: Incorrect extent in return value of 
MAXLOC intrinsic: is 3, should be 2|Array bound mismatch for dimension 1 of 
array 'res' .3/2." }

[gcc(refs/users/mikael/heads/inline_minmaxloc_without_dim_v08)] fortran: Inline all MINLOC/MAXLOC calls with no DIM [PR90608]

[Mikael Morin via Gcc-cvs]

https://gcc.gnu.org/g:89794e9294e7dfa937ebf92080001cb0bcecfeec

commit 89794e9294e7dfa937ebf92080001cb0bcecfeec
Author: Mikael Morin 
Date:   Wed Jul 31 10:10:49 2024 +0200

fortran: Inline all MINLOC/MAXLOC calls with no DIM [PR90608]

Regression-tested on x86_64-pc-linux-gnu.
OK for master?

-- >8 --

Enable generation of inline MINLOC/MAXLOC code in the case where DIM
is not present, and either ARRAY is of floating point type or MASK is an
array.  Those cases are the remaining bits to fully support inlining of
non-CHARACTER MINLOC/MAXLOC without DIM.  They are treated together because
they generate similar code, the NANs for REAL types being handled a bit like
a second level of masking.  These are the cases for which we generate two
sets of loops.

This change affects the code generating the second loop, that was previously
accessible only in the cases ARRAY has rank 1 only.  The single variable
initialization and update are changed to apply to multiple variables, one
per dimension.

The code generated is as follows (if ARRAY has rank 2):

for (idx11 in lower1..upper1)
  {
for (idx12 in lower2..upper2)
  {
...
if (...)
  {
...
goto second_loop;
  }
  }
  }
second_loop:
for (idx21 in lower1..upper1)
  {
for (idx22 in lower2..upper2)
  {
...
  }
  }

This code leads to processing the first elements redundantly, both in the
first set of loops and in the second one.  The loop over idx22 could
start from idx12 the first time it is run, but as it has to start from
lower2 for the rest of the runs, this change uses the same bounds for both
set of loops for simplicity.  In the rank 1 case, this makes the generated
code worse compared to the inline code that was generated before.  A later
change will introduce conditionals to avoid the duplicate processing and
restore the generated code in that case.

PR fortran/90608

gcc/fortran/ChangeLog:

* trans-intrinsic.cc (gfc_conv_intrinsic_minmaxloc): Initialize
and update all the variables.  Put the label and goto in the
outermost scalarizer loop.  Don't start the second loop where the
first stopped.
(gfc_inline_intrinsic_function_p): Also return TRUE for array MASK
or for any REAL type.

gcc/testsuite/ChangeLog:

* gfortran.dg/maxloc_bounds_5.f90: Additionally accept error
messages reported by the scalarizer.
* gfortran.dg/maxloc_bounds_6.f90: Ditto.

Diff:
---
 gcc/fortran/trans-intrinsic.cc| 127 +-
 gcc/testsuite/gfortran.dg/maxloc_bounds_5.f90 |   4 +-
 gcc/testsuite/gfortran.dg/maxloc_bounds_6.f90 |   4 +-
 3 files changed, 87 insertions(+), 48 deletions(-)

diff --git a/gcc/fortran/trans-intrinsic.cc b/gcc/fortran/trans-intrinsic.cc
index 855208717973..3a6a73d42417 100644
--- a/gcc/fortran/trans-intrinsic.cc
+++ b/gcc/fortran/trans-intrinsic.cc
@@ -5332,12 +5332,55 @@ strip_kind_from_actual (gfc_actual_arglist * actual)
   if (a[S] < limit) { limit = a[S]; pos = S + (1 - from); }
   S++;
 }
-   B: ARRAY has rank 1, and DIM is absent.  Use the same code as the scalar
-  case and wrap the result in an array.
-   C: ARRAY has rank > 1, NANs are not supported, and DIM and MASK are absent.
-  Generate code similar to the single loop scalar case, but using one
-  variable per dimension, for example if ARRAY has rank 2:
-  4) NAN's aren't supported, no MASK:
+   B: Array result, non-CHARACTER type, DIM absent
+  Generate similar code as in the scalar case, using a collection of
+  variables (one per dimension) instead of a single variable as result.
+  Picking only cases 1) and 4) with ARRAY of rank 2, the generated code
+  becomes:
+  1) Array mask is used and NaNs need to be supported:
+limit = Infinity;
+pos0 = 0;
+pos1 = 0;
+S1 = from1;
+while (S1 <= to1) {
+  S0 = from0;
+  while (s0 <= to0 {
+if (mask[S1][S0]) {
+  if (pos0 == 0) {
+pos0 = S0 + (1 - from0);
+pos1 = S1 + (1 - from1);
+  }
+  if (a[S1][S0] <= limit) {
+limit = a[S1][S0];
+pos0 = S0 + (1 - from0);
+pos1 = S1 + (1 - from1);
+goto lab1;
+  }
+}
+S0++;
+  }
+  S1++;
+}
+goto lab2;
+lab1:;
+S1 = from1;
+while (S1 <= to1) {
+   

[gcc(refs/users/mikael/heads/inline_minmaxloc_without_dim_v08)] fortran: Continue MINLOC/MAXLOC second loop where the first stopped [PR90608]

[Mikael Morin via Gcc-cvs]

https://gcc.gnu.org/g:b8a4ddbd04b3137ab6c7fb9e377f7e8573f75062

commit b8a4ddbd04b3137ab6c7fb9e377f7e8573f75062
Author: Mikael Morin 
Date:   Wed Jul 31 10:11:02 2024 +0200

fortran: Continue MINLOC/MAXLOC second loop where the first stopped 
[PR90608]

Regression-tested on x86_64-pc-linux-gnu.
OK for master?

-- >8 --

Continue the second set of loops where the first one stopped in the
generated inline MINLOC/MAXLOC code in the cases where the generated code
contains two sets of loops.  This fixes a regression that was introduced
when enabling the generation of inline MINLOC/MAXLOC code with ARRAY of rank
greater than 1, no DIM argument, and either non-scalar MASK or floating-
point ARRAY.

In the cases where two sets of loops are generated as inline MINLOC/MAXLOC
code, we previously generated code such as (for rank 2 ARRAY, so with two
levels of nesting):

for (idx11 in lower1..upper1)
  {
for (idx12 in lower2..upper2)
  {
...
if (...)
  {
...
goto second_loop;
  }
  }
  }
second_loop:
for (idx21 in lower1..upper1)
  {
for (idx22 in lower2..upper2)
  {
...
  }
  }

which means we process the first elements twice, once in the first set
of loops and once in the second one.  This change avoids this duplicate
processing by using a conditional as lower bound for the second set of
loops, generating code like:

second_loop_entry = false;
for (idx11 in lower1..upper1)
  {
for (idx12 in lower2..upper2)
  {
...
if (...)
  {
...
second_loop_entry = true;
goto second_loop;
  }
  }
  }
second_loop:
for (idx21 in (second_loop_entry ? idx11 : lower1)..upper1)
  {
for (idx22 in (second_loop_entry ? idx12 : lower2)..upper2)
  {
...
second_loop_entry = false;
  }
  }

It was expected that the compiler optimizations would be able to remove the
state variable second_loop_entry.  It is the case if ARRAY has rank 1 (so
without loop nesting), the variable is removed and the loop bounds become
unconditional, which restores previously generated code, fully fixing the
regression.  For larger rank, unfortunately, the state variable and
conditional loop bounds remain, but those cases were previously using
library calls, so it's not a regression.

PR fortran/90608

gcc/fortran/ChangeLog:

* trans-intrinsic.cc (gfc_conv_intrinsic_minmaxloc): Generate a set
of index variables.  Set them using the loop indexes before leaving
the first set of loops.  Generate a new loop entry predicate.
Initialize it.  Set it before leaving the first set of loops.  Clear
it in the body of the second set of loops.  For the second set of
loops, update each loop lower bound to use the corresponding index
variable if the predicate variable is set.

Diff:
---
 gcc/fortran/trans-intrinsic.cc | 33 +++--
 1 file changed, 31 insertions(+), 2 deletions(-)

diff --git a/gcc/fortran/trans-intrinsic.cc b/gcc/fortran/trans-intrinsic.cc
index 3a6a73d42417..89134b1190ba 100644
--- a/gcc/fortran/trans-intrinsic.cc
+++ b/gcc/fortran/trans-intrinsic.cc
@@ -5342,6 +5342,7 @@ strip_kind_from_actual (gfc_actual_arglist * actual)
 pos0 = 0;
 pos1 = 0;
 S1 = from1;
+second_loop_entry = false;
 while (S1 <= to1) {
   S0 = from0;
   while (s0 <= to0 {
@@ -5354,6 +5355,7 @@ strip_kind_from_actual (gfc_actual_arglist * actual)
 limit = a[S1][S0];
 pos0 = S0 + (1 - from0);
 pos1 = S1 + (1 - from1);
+second_loop_entry = true;
 goto lab1;
   }
 }
@@ -5363,9 +5365,9 @@ strip_kind_from_actual (gfc_actual_arglist * actual)
 }
 goto lab2;
 lab1:;
-S1 = from1;
+S1 = second_loop_entry ? S1 : from1;
 while (S1 <= to1) {
-  S0 = from0;
+  S0 = second_loop_entry ? S0 : from0;
   while (S0 <= to0) {
 if (mask[S1][S0])
   if (a[S1][S0] < limit) {
@@ -5373,6 +5375,7 @@ strip_kind_from_actual (gfc_actual_arglist * actual)
 pos0 = S + (1 - from0);
 pos1 

[gcc r15-2434] testsuite: Adjust switch-exp-transform-3.c for 32bit

[Filip Kastl via Gcc-cvs]

https://gcc.gnu.org/g:f40fd85c32c9ab4849065d0d14cd5a7ad67619b8

commit r15-2434-gf40fd85c32c9ab4849065d0d14cd5a7ad67619b8
Author: Filip Kastl 
Date:   Wed Jul 31 13:40:45 2024 +0200

testsuite: Adjust switch-exp-transform-3.c for 32bit

32bit x86 CPUs won't natively support the FFS operation on a 64 bit
type.  Therefore, I'm setting the long long int part of the
switch-exp-transform-3.c test to only execute with 64bit targets.

gcc/testsuite/ChangeLog:

* gcc.target/i386/switch-exp-transform-3.c: Set the long long
int test to only execute with 64bit targets.

Signed-off-by: Filip Kastl 

Diff:
---
 gcc/testsuite/gcc.target/i386/switch-exp-transform-3.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/i386/switch-exp-transform-3.c 
b/gcc/testsuite/gcc.target/i386/switch-exp-transform-3.c
index c8fae70692e5..64a7b1461721 100644
--- a/gcc/testsuite/gcc.target/i386/switch-exp-transform-3.c
+++ b/gcc/testsuite/gcc.target/i386/switch-exp-transform-3.c
@@ -99,6 +99,8 @@ int unopt_unsigned_long(unsigned long bit_position)
 }
 }
 
+#ifdef __x86_64__
+
 int unopt_long_long(long long bit_position)
 {
 switch (bit_position)
@@ -145,4 +147,7 @@ int unopt_unsigned_long_long(unsigned long long 
bit_position)
 }
 }
 
-/* { dg-final { scan-tree-dump-times "Applying exponential index transform" 6 
"switchconv" } } */
+#endif
+
+/* { dg-final { scan-tree-dump-times "Applying exponential index transform" 4 
"switchconv" { target ia32 } } } */
+/* { dg-final { scan-tree-dump-times "Applying exponential index transform" 6 
"switchconv" { target { ! ia32 } } } } */

[gcc r15-2435] c++: array new with value-initialization, again [PR115645]

[Marek Polacek via Gcc-cvs]

https://gcc.gnu.org/g:bbc9c0423ca754e8e6ff80e08948ff52986337a0

commit r15-2435-gbbc9c0423ca754e8e6ff80e08948ff52986337a0
Author: Marek Polacek 
Date:   Wed Jul 17 15:44:26 2024 -0400

c++: array new with value-initialization, again [PR115645]

Unfortunately, my r15-1946 fix broke the attached testcase; the
constexpr evaluation reported an error about not being able to
evaluate the code emitted by build_vec_init.  Jason figured out
it's because we were wrongly setting try_const to false, where
in fact it should have been true.  Value-initialization of scalars
is constexpr, so we should check that alongside of
type_has_constexpr_default_constructor.

PR c++/115645

gcc/cp/ChangeLog:

* init.cc (build_vec_init): When initializing a scalar type, try to
create a constant initializer.

gcc/testsuite/ChangeLog:

* g++.dg/cpp2a/constexpr-new23.C: New test.

Diff:
---
 gcc/cp/init.cc   |  5 +++-
 gcc/testsuite/g++.dg/cpp2a/constexpr-new23.C | 38 
 2 files changed, 42 insertions(+), 1 deletion(-)

diff --git a/gcc/cp/init.cc b/gcc/cp/init.cc
index e9561c146d7b..de82152bd1d3 100644
--- a/gcc/cp/init.cc
+++ b/gcc/cp/init.cc
@@ -4724,7 +4724,10 @@ build_vec_init (tree base, tree maxindex, tree init,
&& TREE_CONSTANT (maxindex)
&& (init ? TREE_CODE (init) == CONSTRUCTOR
: (type_has_constexpr_default_constructor
-  (inner_elt_type)))
+  (inner_elt_type)
+  /* Value-initialization of scalars is constexpr.  */
+  || (explicit_value_init_p
+  && SCALAR_TYPE_P (inner_elt_type
&& (literal_type_p (inner_elt_type)
|| TYPE_HAS_CONSTEXPR_CTOR (inner_elt_type)));
   vec *const_vec = NULL;
diff --git a/gcc/testsuite/g++.dg/cpp2a/constexpr-new23.C 
b/gcc/testsuite/g++.dg/cpp2a/constexpr-new23.C
new file mode 100644
index ..1abbef18fae3
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp2a/constexpr-new23.C
@@ -0,0 +1,38 @@
+// PR c++/115645
+// { dg-do compile { target c++20 } }
+
+using size_t = decltype(sizeof(0));
+
+void* operator new(size_t, void* p) { return p; }
+void* operator new[](size_t, void* p) { return p; }
+
+#define VERIFY(C) if (!(C)) throw
+
+namespace std {
+  template
+constexpr T* construct_at(T* p)
+{
+  if constexpr (__is_array(T))
+return ::new((void*)p) T[1]();
+  else
+return ::new((void*)p) T();
+}
+}
+
+constexpr void
+test_array()
+{
+  int arr[1] { 99 };
+  std::construct_at(&arr);
+  VERIFY( arr[0] == 0 );
+
+  union U {
+long long x = -1;
+int arr[4];
+  } u;
+
+  auto p = std::construct_at(&u.arr);
+  VERIFY( (*p)[0] == 0 );
+}
+
+static_assert( [] { test_array(); return true; }() );

[gcc r15-2436] aarch64: Add march flags for +fp8 arch extensions

[Richard Sandiford via Gcc-cvs]

https://gcc.gnu.org/g:72ebbc3b2bb9bb3649f1222f731a9b4d0197499e

commit r15-2436-g72ebbc3b2bb9bb3649f1222f731a9b4d0197499e
Author: Claudio Bantaloukas 
Date:   Wed Jul 31 14:42:39 2024 +0100

aarch64: Add march flags for +fp8 arch extensions

This introduces the relevant flags to enable access to the fpmr register 
and fp8 intrinsics, which will be added subsequently.

gcc/ChangeLog:

* config/aarch64/aarch64-option-extensions.def (fp8): New.
* config/aarch64/aarch64.h (TARGET_FP8): Likewise.
* doc/invoke.texi (AArch64 Options): Document new -march flags
and extensions.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/acle/fp8.c: New test.

Diff:
---
 gcc/config/aarch64/aarch64-option-extensions.def |  2 ++
 gcc/config/aarch64/aarch64.h |  3 +++
 gcc/doc/invoke.texi  |  2 ++
 gcc/testsuite/gcc.target/aarch64/acle/fp8.c  | 20 
 4 files changed, 27 insertions(+)

diff --git a/gcc/config/aarch64/aarch64-option-extensions.def 
b/gcc/config/aarch64/aarch64-option-extensions.def
index 42ec0eec31e2..6998627f3774 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -232,6 +232,8 @@ AARCH64_OPT_EXTENSION("the", THE, (), (), (), "the")
 
 AARCH64_OPT_EXTENSION("gcs", GCS, (), (), (), "gcs")
 
+AARCH64_OPT_EXTENSION("fp8", FP8, (SIMD), (), (), "fp8")
+
 #undef AARCH64_OPT_FMV_EXTENSION
 #undef AARCH64_OPT_EXTENSION
 #undef AARCH64_FMV_FEATURE
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index b7e330438d9b..2e75c6b81e20 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -463,6 +463,9 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED
 && (aarch64_tune_params.extra_tuning_flags \
 & AARCH64_EXTRA_TUNE_AVOID_PRED_RMW))
 
+/* fp8 instructions are enabled through +fp8.  */
+#define TARGET_FP8 AARCH64_HAVE_ISA (FP8)
+
 /* Standard register usage.  */
 
 /* 31 64-bit general purpose registers R0-R30:
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 86f9b5d1fe5e..ef2213b4e841 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21849,6 +21849,8 @@ Enable support for Armv9.4-a Guarded Control Stack 
extension.
 Enable support for Armv8.9-a/9.4-a translation hardening extension.
 @item rcpc3
 Enable the RCpc3 (Release Consistency) extension.
+@item fp8
+Enable the fp8 (8-bit floating point) extension.
 
 @end table
 
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/fp8.c 
b/gcc/testsuite/gcc.target/aarch64/acle/fp8.c
new file mode 100644
index ..459442be1557
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/fp8.c
@@ -0,0 +1,20 @@
+/* Test the fp8 ACLE intrinsics family.  */
+/* { dg-do compile } */
+/* { dg-options "-O1 -march=armv8-a" } */
+
+#include 
+
+#ifdef __ARM_FEATURE_FP8
+#error "__ARM_FEATURE_FP8 feature macro defined."
+#endif
+
+#pragma GCC push_options
+#pragma GCC target("arch=armv9.4-a+fp8")
+
+/* We do not define __ARM_FEATURE_FP8 until all
+   relevant features have been added. */
+#ifdef __ARM_FEATURE_FP8
+#error "__ARM_FEATURE_FP8 feature macro defined."
+#endif
+
+#pragma GCC pop_options

[gcc r15-2437] aarch64: Add support for moving fpm system register

[Richard Sandiford via Gcc-cvs]

https://gcc.gnu.org/g:6d43c3669a6bd9e84f6d3941e19cc025de59ece0

commit r15-2437-g6d43c3669a6bd9e84f6d3941e19cc025de59ece0
Author: Claudio Bantaloukas 
Date:   Wed Jul 31 14:42:40 2024 +0100

aarch64: Add support for moving fpm system register

Unlike most system registers, fpmr can be heavily written to in code that
exercises the fp8 functionality. That is because every fp8 instrinsic call
can potentially change the value of fpmr.
Rather than just use an unspec, we treat the fpmr system register like
all other registers and use a move operation to read and write to it.

We introduce a new class of moveable system registers that, currently,
only accepts fpmr and a new constraint, Umv, that allows us to
selectively use mrs and msr instructions when expanding rtl for them.
Given that there is code that depends on "real" registers coming before
"fake" ones, we introduce a new constant FPM_REGNUM that uses an
existing value and renumber registers below that.
This requires us to update the bitmaps that describe which registers
belong to each register class.

gcc/ChangeLog:

* config/aarch64/aarch64.cc (aarch64_hard_regno_nregs): Add
support for MOVEABLE_SYSREGS class.
(aarch64_hard_regno_mode_ok): Allow reads and writes to fpmr.
(aarch64_regno_regclass): Support MOVEABLE_SYSREGS class.
(aarch64_class_max_nregs): Likewise.
* config/aarch64/aarch64.h (FIXED_REGISTERS): add fpmr.
(CALL_REALLY_USED_REGISTERS): Likewise.
(REGISTER_NAMES): Likewise.
(enum reg_class): Add MOVEABLE_SYSREGS class.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Update class bitmaps to deal with fpmr,
the new MOVEABLE_REGS class and renumbering of registers.
* config/aarch64/aarch64.md: (FPM_REGNUM): added new register
number, reusing old value.
(FFR_REGNUM): Renumber.
(FFRT_REGNUM): Likewise.
(LOWERING_REGNUM): Likewise.
(TPIDR2_BLOCK_REGNUM): Likewise.
(SME_STATE_REGNUM): Likewise.
(TPIDR2_SETUP_REGNUM): Likewise.
(ZA_FREE_REGNUM): Likewise.
(ZA_SAVED_REGNUM): Likewise.
(ZA_REGNUM): Likewise.
(ZT0_REGNUM): Likewise.
(*mov_aarch64): Add support for moveable sysregs.
(*movsi_aarch64): Likewise.
(*movdi_aarch64): Likewise.
* config/aarch64/constraints.md (MOVEABLE_SYSREGS): New constraint.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/acle/fp8.c: New tests.

Diff:
---
 gcc/config/aarch64/aarch64.cc   |   8 +++
 gcc/config/aarch64/aarch64.h|  14 ++--
 gcc/config/aarch64/aarch64.md   |  30 ++---
 gcc/config/aarch64/constraints.md   |   3 +
 gcc/testsuite/gcc.target/aarch64/acle/fp8.c | 101 
 5 files changed, 142 insertions(+), 14 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index e0cf382998c7..9810f2c03900 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -2018,6 +2018,7 @@ aarch64_hard_regno_nregs (unsigned regno, machine_mode 
mode)
 case PR_HI_REGS:
   return mode == VNx32BImode ? 2 : 1;
 
+case MOVEABLE_SYSREGS:
 case FFR_REGS:
 case PR_AND_FFR_REGS:
 case FAKE_REGS:
@@ -2045,6 +2046,9 @@ aarch64_hard_regno_mode_ok (unsigned regno, machine_mode 
mode)
 /* This must have the same size as _Unwind_Word.  */
 return mode == DImode;
 
+  if (regno == FPM_REGNUM)
+return mode == QImode || mode == HImode || mode == SImode || mode == 
DImode;
+
   unsigned int vec_flags = aarch64_classify_vector_mode (mode);
   if (vec_flags == VEC_SVE_PRED)
 return pr_or_ffr_regnum_p (regno);
@@ -12680,6 +12684,9 @@ aarch64_regno_regclass (unsigned regno)
   if (PR_REGNUM_P (regno))
 return PR_LO_REGNUM_P (regno) ? PR_LO_REGS : PR_HI_REGS;
 
+  if (regno == FPM_REGNUM)
+return MOVEABLE_SYSREGS;
+
   if (regno == FFR_REGNUM || regno == FFRT_REGNUM)
 return FFR_REGS;
 
@@ -13068,6 +13075,7 @@ aarch64_class_max_nregs (reg_class_t regclass, 
machine_mode mode)
 case PR_HI_REGS:
   return mode == VNx32BImode ? 2 : 1;
 
+case MOVEABLE_SYSREGS:
 case STACK_REG:
 case FFR_REGS:
 case PR_AND_FFR_REGS:
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 2e75c6b81e20..2dfb999bea53 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -523,6 +523,7 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED
 1, 1, 1, 1,/* SFP, AP, CC, VG */   \
 0, 0, 0, 0,   0, 0, 0, 0,   /* P0 - P7 */   \
 0, 0, 0, 0,   0, 0, 0, 0,   /* P8 - P15 */  \
+1, /* FPMR */  \
 1, 1,   

[gcc r15-2438] aarch64: Add fpm register helper functions.

[Richard Sandiford via Gcc-cvs]

https://gcc.gnu.org/g:cfe2b6756c691c92aa29337c6973e3b3361de5c9

commit r15-2438-gcfe2b6756c691c92aa29337c6973e3b3361de5c9
Author: Claudio Bantaloukas 
Date:   Wed Jul 31 14:42:41 2024 +0100

aarch64: Add fpm register helper functions.

The ACLE declares several helper types and functions to facilitate 
construction
of `fpm` arguments. These are available when one of the arm_neon.h, 
arm_sve.h,
or arm_sme.h headers is included. These helpers don't map to specific FP8
instructions and there's no expectation that they will produce a given code
sequence, they're just an abstraction and an aid to the programmer. Thus 
they are
implemented in a new header file arm_private_fp8.h
Users are not expected to include this file, as it is a mere implementation 
detail,
subject to change. A check is included to guard against direct inclusion.

gcc/ChangeLog:

* config.gcc (extra_headers): Install arm_private_fp8.h.
* config/aarch64/arm_neon.h: Include arm_private_fp8.h.
* config/aarch64/arm_sve.h: Likewise.
* config/aarch64/arm_private_fp8.h: New file
(fpm_t): New type representing fpmr values.
(enum __ARM_FPM_FORMAT): New enum representing valid fp8 formats.
(enum __ARM_FPM_OVERFLOW): New enum representing how some fp8
calculations work.
(__arm_fpm_init): New.
(__arm_set_fpm_src1_format): Likewise.
(__arm_set_fpm_src2_format): Likewise.
(__arm_set_fpm_dst_format): Likewise.
(__arm_set_fpm_overflow_cvt): Likewise.
(__arm_set_fpm_overflow_mul): Likewise.
(__arm_set_fpm_lscale): Likewise.
(__arm_set_fpm_lscale2): Likewise.
(__arm_set_fpm_nscale): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/acle/fp8-helpers-neon.c: New test of fpmr 
helper
functions.
* gcc.target/aarch64/acle/fp8-helpers-sve.c: New test of fpmr helper
functions presence.
* gcc.target/aarch64/acle/fp8-helpers-sme.c: New test of fpmr helper
functions presence.

Diff:
---
 gcc/config.gcc |  2 +-
 gcc/config/aarch64/arm_neon.h  |  1 +
 gcc/config/aarch64/arm_private_fp8.h   | 80 ++
 gcc/config/aarch64/arm_sve.h   |  1 +
 .../gcc.target/aarch64/acle/fp8-helpers-neon.c | 53 ++
 .../gcc.target/aarch64/acle/fp8-helpers-sme.c  | 12 
 .../gcc.target/aarch64/acle/fp8-helpers-sve.c  | 12 
 7 files changed, 160 insertions(+), 1 deletion(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 7453ade07826..a36dd1bcbc66 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -347,7 +347,7 @@ m32c*-*-*)
 ;;
 aarch64*-*-*)
cpu_type=aarch64
-   extra_headers="arm_fp16.h arm_neon.h arm_bf16.h arm_acle.h arm_sve.h 
arm_sme.h arm_neon_sve_bridge.h"
+   extra_headers="arm_fp16.h arm_neon.h arm_bf16.h arm_acle.h arm_sve.h 
arm_sme.h arm_neon_sve_bridge.h arm_private_fp8.h"
c_target_objs="aarch64-c.o"
cxx_target_objs="aarch64-c.o"
d_target_objs="aarch64-d.o"
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index c4a09528ffd8..e376685489da 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -30,6 +30,7 @@
 #pragma GCC push_options
 #pragma GCC target ("+nothing+simd")
 
+#include 
 #pragma GCC aarch64 "arm_neon.h"
 
 #include 
diff --git a/gcc/config/aarch64/arm_private_fp8.h 
b/gcc/config/aarch64/arm_private_fp8.h
new file mode 100644
index ..5668cc24c99b
--- /dev/null
+++ b/gcc/config/aarch64/arm_private_fp8.h
@@ -0,0 +1,80 @@
+/* AArch64 FP8 helper functions.
+   Do not include this file directly. Use one of arm_neon.h
+   arm_sme.h arm_sve.h instead.
+
+   Copyright (C) 2024 Free Software Foundation, Inc.
+   Contributed by ARM Ltd.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   .  */
+
+#

[gcc r15-2439] testsuite: libgomp: fix dg-do run typo

[Sam James via Gcc-cvs]

https://gcc.gnu.org/g:1c85b16f1916397886a53b70ef360618b5df7977

commit r15-2439-g1c85b16f1916397886a53b70ef360618b5df7977
Author: Sam James 
Date:   Thu Jul 18 03:42:44 2024 +0100

testsuite: libgomp: fix dg-do run typo

'dg-run' is not a valid dejagnu directive, 'dg-do run' is needed here
for the test to be executed.

That said, it actually seems to be executed for me anyway, presumably
a default in the directory, but let's fix it to be consistent with
other uses in the tree and in that test directory even.

libgomp/ChangeLog:
* testsuite/libgomp.c++/declare-target-indirect-1.C: Fix 'dg-run' 
typo.

Diff:
---
 libgomp/testsuite/libgomp.c++/declare-target-indirect-1.C | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libgomp/testsuite/libgomp.c++/declare-target-indirect-1.C 
b/libgomp/testsuite/libgomp.c++/declare-target-indirect-1.C
index 1eac6b3fa96b..bd84b492feec 100644
--- a/libgomp/testsuite/libgomp.c++/declare-target-indirect-1.C
+++ b/libgomp/testsuite/libgomp.c++/declare-target-indirect-1.C
@@ -1,4 +1,4 @@
-// { dg-run }
+// { dg-do run }
 
 #pragma omp begin declare target indirect
 class C

[gcc r15-2440] testsuite: fix 'dg-do-compile' typos

[Sam James via Gcc-cvs]

https://gcc.gnu.org/g:21fc6d35f27cdf4c56e9f093894f6728c55ecb0e

commit r15-2440-g21fc6d35f27cdf4c56e9f093894f6728c55ecb0e
Author: Sam James 
Date:   Tue Jul 30 21:44:12 2024 +0100

testsuite: fix 'dg-do-compile' typos

We want 'dg-do compile', not 'dg-do-compile'. Fix that.

PR target/69194
PR c++/92024
PR c++/110057
* c-c++-common/Wshadow-1.c: Fix 'dg-do compile' typo.
* g++.dg/tree-ssa/devirt-array-destructor-1.C: Likewise.
* g++.dg/tree-ssa/devirt-array-destructor-2.C: Likewise.
* gcc.target/arm/pr69194.c: Likewise.

Diff:
---
 gcc/testsuite/c-c++-common/Wshadow-1.c| 2 +-
 gcc/testsuite/g++.dg/tree-ssa/devirt-array-destructor-1.C | 2 +-
 gcc/testsuite/g++.dg/tree-ssa/devirt-array-destructor-2.C | 2 +-
 gcc/testsuite/gcc.target/arm/pr69194.c| 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/gcc/testsuite/c-c++-common/Wshadow-1.c 
b/gcc/testsuite/c-c++-common/Wshadow-1.c
index 4d1edf07f002..3cd99e9087ec 100644
--- a/gcc/testsuite/c-c++-common/Wshadow-1.c
+++ b/gcc/testsuite/c-c++-common/Wshadow-1.c
@@ -1,4 +1,4 @@
-/* { dg-do-compile } */
+/* { dg-do compile } */
 /* { dg-additional-options "-Wshadow=local -Wno-shadow=compatible-local" } */
 int c;
 void foo(int *c, int *d)   /* { dg-bogus   "Wshadow" } */
diff --git a/gcc/testsuite/g++.dg/tree-ssa/devirt-array-destructor-1.C 
b/gcc/testsuite/g++.dg/tree-ssa/devirt-array-destructor-1.C
index ce8dc2a57cd7..eed9a7c17698 100644
--- a/gcc/testsuite/g++.dg/tree-ssa/devirt-array-destructor-1.C
+++ b/gcc/testsuite/g++.dg/tree-ssa/devirt-array-destructor-1.C
@@ -1,5 +1,5 @@
 // PR c++/110057
-/* { dg-do-compile } */
+/* { dg-do compile } */
 /* Virtual calls should be devirtualized because we know dynamic type of 
object in array at compile time */
 /* { dg-options "-O3 -fdump-tree-optimized -fno-inline"  } */
 
diff --git a/gcc/testsuite/g++.dg/tree-ssa/devirt-array-destructor-2.C 
b/gcc/testsuite/g++.dg/tree-ssa/devirt-array-destructor-2.C
index 6b44dc1a4eea..448f3739700f 100644
--- a/gcc/testsuite/g++.dg/tree-ssa/devirt-array-destructor-2.C
+++ b/gcc/testsuite/g++.dg/tree-ssa/devirt-array-destructor-2.C
@@ -1,5 +1,5 @@
 // PR c++/110057
-/* { dg-do-compile } */
+/* { dg-do compile } */
 /* Virtual calls should be devirtualized because we know dynamic type of 
object in array at compile time */
 /* { dg-options "-O3 -fdump-tree-optimized -fno-inline"  } */
 
diff --git a/gcc/testsuite/gcc.target/arm/pr69194.c 
b/gcc/testsuite/gcc.target/arm/pr69194.c
index 477d5f92c8ec..dc1b0d306c2b 100644
--- a/gcc/testsuite/gcc.target/arm/pr69194.c
+++ b/gcc/testsuite/gcc.target/arm/pr69194.c
@@ -1,5 +1,5 @@
 /* PR target/69194 */
-/* { dg-do-compile } */
+/* { dg-do compile } */
 /* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-O2" } */
 /* { dg-add-options arm_neon } */

[gcc r15-2441] testsuite: fix 'dg-do-preprocess' typo

[Sam James via Gcc-cvs]

https://gcc.gnu.org/g:d398581485b4141b43b11f27c8eb359a99fe4ca9

commit r15-2441-gd398581485b4141b43b11f27c8eb359a99fe4ca9
Author: Sam James 
Date:   Tue Jul 30 21:46:29 2024 +0100

testsuite: fix 'dg-do-preprocess' typo

We want 'dg-do preprocess', not 'dg-do-preprocess'. Fix that.

PR target/106828
* g++.target/loongarch/pr106828.C: Fix 'dg-do compile' typo.

Diff:
---
 gcc/testsuite/g++.target/loongarch/pr106828.C | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/g++.target/loongarch/pr106828.C 
b/gcc/testsuite/g++.target/loongarch/pr106828.C
index 190c1db715f4..0d13cbbd5153 100644
--- a/gcc/testsuite/g++.target/loongarch/pr106828.C
+++ b/gcc/testsuite/g++.target/loongarch/pr106828.C
@@ -1,4 +1,4 @@
-/* { dg-do-preprocess } */
+/* { dg-do preprocess } */
 /* { dg-options "-mabi=lp64d -fsanitize=address" } */
 
 /* Tests whether the compiler supports compile option '-fsanitize=address'.  */

[gcc r15-2443] testsuite: fix dg-require-* order vs dg-additional-sources

[Sam James via Gcc-cvs]

https://gcc.gnu.org/g:d498e79ebe90415047b0bdfdb70e0d579a88965b

commit r15-2443-gd498e79ebe90415047b0bdfdb70e0d579a88965b
Author: Sam James 
Date:   Tue Jul 30 22:01:42 2024 +0100

testsuite: fix dg-require-* order vs dg-additional-sources

Per gccint, 'dg-require-*' must come before any
'dg-additional-sources' directives. Fix a handful of deviant cases.

* gcc.dg/tree-prof/crossmodule-indir-call-topn-1.c: Fix 
dg-require-profiling
directive order.
* gcc.dg/tree-prof/crossmodule-indir-call-topn-2.c: Likewise.

Diff:
---
 gcc/testsuite/gcc.dg/tree-prof/crossmodule-indir-call-topn-1.c | 2 +-
 gcc/testsuite/gcc.dg/tree-prof/crossmodule-indir-call-topn-2.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/tree-prof/crossmodule-indir-call-topn-1.c 
b/gcc/testsuite/gcc.dg/tree-prof/crossmodule-indir-call-topn-1.c
index b57d30f91637..f6ec71a9298d 100644
--- a/gcc/testsuite/gcc.dg/tree-prof/crossmodule-indir-call-topn-1.c
+++ b/gcc/testsuite/gcc.dg/tree-prof/crossmodule-indir-call-topn-1.c
@@ -1,6 +1,6 @@
 /* { dg-require-effective-target lto } */
-/* { dg-additional-sources "crossmodule-indir-call-topn-1a.c" } */
 /* { dg-require-profiling "-fprofile-generate" } */
+/* { dg-additional-sources "crossmodule-indir-call-topn-1a.c" } */
 /* { dg-options "-O2 -flto -DDOJOB=1 -fdump-ipa-profile_estimate" } */
 
 #ifdef FOR_AUTOFDO_TESTING
diff --git a/gcc/testsuite/gcc.dg/tree-prof/crossmodule-indir-call-topn-2.c 
b/gcc/testsuite/gcc.dg/tree-prof/crossmodule-indir-call-topn-2.c
index 6b5ae93214a5..2ace3c3b9bf1 100644
--- a/gcc/testsuite/gcc.dg/tree-prof/crossmodule-indir-call-topn-2.c
+++ b/gcc/testsuite/gcc.dg/tree-prof/crossmodule-indir-call-topn-2.c
@@ -1,6 +1,6 @@
 /* { dg-require-effective-target lto } */
-/* { dg-additional-sources "crossmodule-indir-call-topn-1a.c" } */
 /* { dg-require-profiling "-fprofile-generate" } */
+/* { dg-additional-sources "crossmodule-indir-call-topn-1a.c" } */
 /* { dg-options "-O2 -flto -DDOJOB=1 -fdump-ipa-profile_estimate" } */
 
 #ifdef FOR_AUTOFDO_TESTING

[gcc r15-2442] testsuite: fix dg-require-effective-target order vs dg-additional-sources

[Sam James via Gcc-cvs]

https://gcc.gnu.org/g:9ad3d1c5814976b8dcd3821bb27ec3bfe9c32aec

commit r15-2442-g9ad3d1c5814976b8dcd3821bb27ec3bfe9c32aec
Author: Sam James 
Date:   Tue Jul 30 21:55:30 2024 +0100

testsuite: fix dg-require-effective-target order vs dg-additional-sources

Per gccint, 'dg-require-effective-target' must come before any
'dg-additional-sources' directives. Fix a handful of deviant cases.

gcc/testsuite/ChangeLog:
* gcc.target/aarch64/aapcs64/func-ret-3.c: Fix 
dg-require-effective-target directive order.
* gcc.target/aarch64/aapcs64/func-ret-4.c: Likewise.
* gfortran.dg/PR100914.f90: Likewise.

libgomp/ChangeLog:
* testsuite/libgomp.c++/pr24455.C: Fix dg-require-effective-target 
directive order.
* testsuite/libgomp.c/pr24455.c: Likewise.

Diff:
---
 gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-3.c | 2 +-
 gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-4.c | 2 +-
 gcc/testsuite/gfortran.dg/PR100914.f90| 2 +-
 libgomp/testsuite/libgomp.c++/pr24455.C   | 2 +-
 libgomp/testsuite/libgomp.c/pr24455.c | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-3.c 
b/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-3.c
index 1d35ebf14b4b..ebd2e8dd8791 100644
--- a/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-3.c
+++ b/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-3.c
@@ -4,9 +4,9 @@
in AAPCS64 \S 4.3.5.  */
 
 /* { dg-do run { target aarch64-*-* } } */
+/* { dg-require-effective-target aarch64_big_endian } */
 /* { dg-additional-options "-mbranch-protection=none" } */
 /* { dg-additional-sources "abitest.S" } */
-/* { dg-require-effective-target aarch64_big_endian } */
 
 #ifndef IN_FRAMEWORK
 #define TESTFILE "func-ret-3.c"
diff --git a/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-4.c 
b/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-4.c
index 15e1408c62d7..03d42f3dd047 100644
--- a/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-4.c
+++ b/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-4.c
@@ -5,9 +5,9 @@
are treated as general composite types.  */
 
 /* { dg-do run { target aarch64*-*-* } } */
+/* { dg-require-effective-target aarch64_big_endian } */
 /* { dg-additional-options "-mbranch-protection=none" } */
 /* { dg-additional-sources "abitest.S" } */
-/* { dg-require-effective-target aarch64_big_endian } */
 
 #ifndef IN_FRAMEWORK
 #define TESTFILE "func-ret-4.c"
diff --git a/gcc/testsuite/gfortran.dg/PR100914.f90 
b/gcc/testsuite/gfortran.dg/PR100914.f90
index 8588157e59c0..161f1265fa21 100644
--- a/gcc/testsuite/gfortran.dg/PR100914.f90
+++ b/gcc/testsuite/gfortran.dg/PR100914.f90
@@ -1,7 +1,7 @@
 ! Fails on x86 targets where sizeof(long double) == 16.
 ! { dg-do run }
-! { dg-additional-sources PR100914.c }
 ! { dg-require-effective-target fortran_real_c_float128 }
+! { dg-additional-sources PR100914.c }
 ! { dg-additional-options "-Wno-pedantic" }
 !
 ! Test the fix for PR100914
diff --git a/libgomp/testsuite/libgomp.c++/pr24455.C 
b/libgomp/testsuite/libgomp.c++/pr24455.C
index 8256b6693c8f..9816d37461a5 100644
--- a/libgomp/testsuite/libgomp.c++/pr24455.C
+++ b/libgomp/testsuite/libgomp.c++/pr24455.C
@@ -1,6 +1,6 @@
 // { dg-do run }
-// { dg-additional-sources pr24455-1.C }
 // { dg-require-effective-target tls_runtime }
+// { dg-additional-sources pr24455-1.C }
 // { dg-options "-fno-extern-tls-init" }
 
 extern "C" void abort (void);
diff --git a/libgomp/testsuite/libgomp.c/pr24455.c 
b/libgomp/testsuite/libgomp.c/pr24455.c
index 8af449e7b5c3..4284c1095293 100644
--- a/libgomp/testsuite/libgomp.c/pr24455.c
+++ b/libgomp/testsuite/libgomp.c/pr24455.c
@@ -1,6 +1,6 @@
 /* { dg-do run } */
-/* { dg-additional-sources pr24455-1.c } */
 /* { dg-require-effective-target tls_runtime } */
+/* { dg-additional-sources pr24455-1.c } */
 
 extern void abort (void);

[gcc r15-2444] libstdc++: Handle encodings in localized chrono formatting [PR109162]

[Jonathan Wakely via Gcc-cvs]

https://gcc.gnu.org/g:74b5101cc9e297f7c530642553e3498d4d705cf4

commit r15-2444-g74b5101cc9e297f7c530642553e3498d4d705cf4
Author: Jonathan Wakely 
Date:   Thu Feb 1 11:14:48 2024 +

libstdc++: Handle encodings in localized chrono formatting [PR109162]

This implements the C++23 paper P2419R2 (Clarify handling of encodings
in localized formatting of chrono types). The requirement is that when
the literal encoding is "a Unicode encoding form" and the formatting
locale uses a different encoding, any locale-specific strings such as
"août" for std::chrono::August should be converted to the literal
encoding.

Using the recently-added std::locale::encoding() function we can check
the locale's encoding and then use iconv if a conversion is needed.
Because nl_langinfo_l and iconv_open both allocate memory, a naive
implementation would perform multiple allocations and deallocations for
every snippet of locale-specific text that needs to be converted to
UTF-8. To avoid that, a new internal locale::facet is defined to store
the text_encoding and an iconv_t descriptor, which are then cached in
the formatting locale. This requires access to the internals of a
std::locale object in src/c++20/format.cc, so that new file needs to be
compiled with -fno-access-control, as well as -std=gnu++26 in order to
use std::text_encoding.

Because the new std::text_encoding and std::locale::encoding() symbols
are only in the libstdc++exp.a archive, we need to include
src/c++26/text_encoding.cc in the main library, but not export its
symbols yet. This means they can be used by the two new functions which
are exported from the main library.

The encoding conversions are done for C++20, treating it as a DR that
resolves LWG 3656.

With this change we can increase the value of the __cpp_lib_format macro
for C++23. The value should be 202207 for P2419R2, but we already
implement P2510R3 (Formatting pointers) so can use the value 202304.

libstdc++-v3/ChangeLog:

PR libstdc++/109162
* acinclude.m4 (libtool_VERSION): Update to 6:34:0.
* config/abi/pre/gnu.ver: Disambiguate old patters. Add new
GLIBCXX_3.4.34 symbol version and new exports.
* configure: Regenerate.
* include/bits/chrono_io.h (_ChronoSpec::_M_locale_specific):
Add new accessor functions to use a reserved bit in _Spec.
(__formatter_chrono::_M_parse): Use _M_locale_specific(true)
when chrono-specs contains locale-dependent conversion
specifiers.
(__formatter_chrono::_M_format): Open iconv descriptor if
conversion to UTF-8 will be needed.
(__formatter_chrono::_M_write): New function to write a
localized string with possible character conversion.
(__formatter_chrono::_M_a_A, __formatter_chrono::_M_b_B)
(__formatter_chrono::_M_p, __formatter_chrono::_M_r)
(__formatter_chrono::_M_x, __formatter_chrono::_M_X)
(__formatter_chrono::_M_locale_fmt): Use _M_write.
* include/bits/version.def (format): Update value.
* include/bits/version.h: Regenerate.
* include/std/format (_GLIBCXX_P2518R3): Check feature test
macro instead of __cplusplus.
(basic_format_context): Declare __formatter_chrono as friend.
* src/c++20/Makefile.am: Add new file.
* src/c++20/Makefile.in: Regenerate.
* src/c++20/format.cc: New file.
* testsuite/std/time/format_localized.cc: New test.
* testsuite/util/testsuite_abi.cc: Add new symbol version.

Diff:
---
 libstdc++-v3/acinclude.m4  |   2 +-
 libstdc++-v3/config/abi/pre/gnu.ver|  18 +-
 libstdc++-v3/configure |   2 +-
 libstdc++-v3/include/bits/chrono_io.h  |  95 +++--
 libstdc++-v3/include/bits/version.def  |  29 ++-
 libstdc++-v3/include/bits/version.h|   4 +-
 libstdc++-v3/include/std/format|  16 +-
 libstdc++-v3/src/c++20/Makefile.am |   8 +-
 libstdc++-v3/src/c++20/Makefile.in |  10 +-
 libstdc++-v3/src/c++20/format.cc   | 213 +
 .../testsuite/std/time/format_localized.cc |  90 +
 libstdc++-v3/testsuite/util/testsuite_abi.cc   |   1 +
 12 files changed, 459 insertions(+), 29 deletions(-)

diff --git a/libstdc++-v3/acinclude.m4 b/libstdc++-v3/acinclude.m4
index e04aae25360d..e4ed583b3ae3 100644
--- a/libstdc++-v3/acinclude.m4
+++ b/libstdc++-v3/acinclude.m4
@@ -4230,7 +4230,7 @@ changequote([,])dnl
 fi
 
 # For libtool versioning info, format is CURRENT:REVISION:AGE
-libtool_VERSION=6:33:0
+libtool_VERSION=6:34:0
 
 # Everything parsed; figure out what files and settings to

[gcc r15-2446] libstdc++: Implement C++26 type checking for std::format args [PR115776]

[Jonathan Wakely via Libstdc++-cvs]

https://gcc.gnu.org/g:3836df7e895beda1f159620bfd20024136fda9f0

commit r15-2446-g3836df7e895beda1f159620bfd20024136fda9f0
Author: Jonathan Wakely 
Date:   Tue Jul 9 12:12:56 2024 +0100

libstdc++: Implement C++26 type checking for std::format args [PR115776]

Implement the changes from P2757R3, which enhance the parse context to
be able to do type checking on format arguments, and to use that to
ensure that args used for width and precisions are integral types.

libstdc++-v3/ChangeLog:

PR libstdc++/115776
* include/bits/version.def (format): Update for C++26.
* include/bits/version.h: Regenerate.
* include/std/format (basic_format_parse_context): Remove
default argument from constructor and split into two
constructors. Make the constructor taking size_t private for
C++26 and later.
(basic_format_parse_context::check_dynamic_spec): New member
function template.
(basic_format_parse_context::check_dynamic_spec_integral): New
member function.
(basic_format_parse_context::check_dynamic_spec_string):
Likewise.
(__format::_Spec::_S_parse_width_or_precision): Use
check_dynamic_spec_integral.
(__format::__to_arg_t_enum): New helper function.
(basic_format_arg):  Declare __to_arg_t_enum as friend.
(__format::_Scanner): Define and use a derived parse context
type.
(__format::_Checking_scanner): Make arg types available to parse
context.
* testsuite/std/format/functions/format.cc: Check for new values
of __cpp_lib_format macro.
* testsuite/std/format/parse_ctx.cc: Check all members of
basic_format_parse_context.
* testsuite/std/format/parse_ctx_neg.cc: New test.
* testsuite/std/format/string.cc: Add more checks for dynamic
width and precision args.

Diff:
---
 libstdc++-v3/include/bits/version.def  |  10 +-
 libstdc++-v3/include/bits/version.h|   7 +-
 libstdc++-v3/include/std/format| 142 +++-
 .../testsuite/std/format/functions/format.cc   |   4 +
 libstdc++-v3/testsuite/std/format/parse_ctx.cc | 145 +
 libstdc++-v3/testsuite/std/format/parse_ctx_neg.cc |  39 ++
 libstdc++-v3/testsuite/std/format/string.cc|  13 ++
 7 files changed, 347 insertions(+), 13 deletions(-)

diff --git a/libstdc++-v3/include/bits/version.def 
b/libstdc++-v3/include/bits/version.def
index 1acc9cd5cb9a..bcb33c18aa4d 100644
--- a/libstdc++-v3/include/bits/version.def
+++ b/libstdc++-v3/include/bits/version.def
@@ -1165,11 +1165,11 @@ ftms = {
   // 202305 P2757R3 Type checking format args
   // 202306 P2637R3 Member visit
   // 202311 P2918R2 Runtime format strings II
-  // values = {
-// v = 202305;
-// cxxmin = 26;
-// hosted = yes;
-  // };
+  values = {
+v = 202305;
+cxxmin = 26;
+hosted = yes;
+  };
   // 201907 Text Formatting, Integration of chrono, printf corner cases.
   // 202106 std::format improvements.
   // 202110 Fixing locale handling in chrono formatters, generator-like types.
diff --git a/libstdc++-v3/include/bits/version.h 
b/libstdc++-v3/include/bits/version.h
index 5cd0e213..4d1af34bf8d5 100644
--- a/libstdc++-v3/include/bits/version.h
+++ b/libstdc++-v3/include/bits/version.h
@@ -1304,7 +1304,12 @@
 #undef __glibcxx_want_barrier
 
 #if !defined(__cpp_lib_format)
-# if (__cplusplus >= 202002L) && _GLIBCXX_HOSTED
+# if (__cplusplus >  202302L) && _GLIBCXX_HOSTED
+#  define __glibcxx_format 202305L
+#  if defined(__glibcxx_want_all) || defined(__glibcxx_want_format)
+#   define __cpp_lib_format 202305L
+#  endif
+# elif (__cplusplus >= 202002L) && _GLIBCXX_HOSTED
 #  define __glibcxx_format 202304L
 #  if defined(__glibcxx_want_all) || defined(__glibcxx_want_format)
 #   define __cpp_lib_format 202304L
diff --git a/libstdc++-v3/include/std/format b/libstdc++-v3/include/std/format
index 2669ad8c2440..6a88705ec7b9 100644
--- a/libstdc++-v3/include/std/format
+++ b/libstdc++-v3/include/std/format
@@ -222,6 +222,9 @@ namespace __format
   inline void
   __failed_to_parse_format_spec()
   { __throw_format_error("format error: failed to parse format-spec"); }
+
+  template class _Scanner;
+
 } // namespace __format
   /// @endcond
 
@@ -241,9 +244,8 @@ namespace __format
   using iterator = const_iterator;
 
   constexpr explicit
-  basic_format_parse_context(basic_string_view<_CharT> __fmt,
-size_t __num_args = 0) noexcept
-  : _M_begin(__fmt.begin()), _M_end(__fmt.end()), _M_num_args(__num_args)
+  basic_format_parse_context(basic_string_view<_CharT> __fmt) noexcept
+  : _M_begin(__fmt.begin()), _M_end(__fmt.end())
   { }
 
   basic_format_parse_context(const basic_format_par

[gcc r15-2445] libstdc++: Support P2510R3 "Formatting pointers" as a DR for C++20

[Jonathan Wakely via Libstdc++-cvs]

https://gcc.gnu.org/g:72cd15b20a887bed9b0b1f4196be99fe052247b4

commit r15-2445-g72cd15b20a887bed9b0b1f4196be99fe052247b4
Author: Jonathan Wakely 
Date:   Fri Jul 12 00:30:24 2024 +0100

libstdc++: Support P2510R3 "Formatting pointers" as a DR for C++20

We already enable this for -std=gnu++20 but we can do it for -std=c++20
too. Both libc++ and MSVC also treat this change as a DR for C++20.

Now that the previous change to the value of __cpp_lib_format is
supported, we can finally update it to 202304 to indicate support for
this feature too.

libstdc++-v3/ChangeLog:

* include/bits/version.def (format): Update value for P2510R3.
* include/bits/version.h: Regenerate.
* include/std/format (_GLIBCXX_P2518R3): Remove misspelled macro
and check __glibcxx_format instead.
* testsuite/std/format/functions/format.cc: Check value of the
__cpp_lib_format macro for formatting pointers support.
* testsuite/std/format/parse_ctx.cc: Likewise.

Diff:
---
 libstdc++-v3/include/bits/version.def |  6 +++---
 libstdc++-v3/include/bits/version.h   |  4 ++--
 libstdc++-v3/include/std/format   | 16 
 libstdc++-v3/testsuite/std/format/functions/format.cc |  2 +-
 libstdc++-v3/testsuite/std/format/parse_ctx.cc|  4 ++--
 5 files changed, 12 insertions(+), 20 deletions(-)

diff --git a/libstdc++-v3/include/bits/version.def 
b/libstdc++-v3/include/bits/version.def
index 749473017607..1acc9cd5cb9a 100644
--- a/libstdc++-v3/include/bits/version.def
+++ b/libstdc++-v3/include/bits/version.def
@@ -1162,12 +1162,11 @@ ftms = {
 
 ftms = {
   name = format;
-  // 202304 P2510R3 Formatting pointers
   // 202305 P2757R3 Type checking format args
   // 202306 P2637R3 Member visit
   // 202311 P2918R2 Runtime format strings II
   // values = {
-// v = 202304;
+// v = 202305;
 // cxxmin = 26;
 // hosted = yes;
   // };
@@ -1175,8 +1174,9 @@ ftms = {
   // 202106 std::format improvements.
   // 202110 Fixing locale handling in chrono formatters, generator-like types.
   // 202207 Encodings in localized formatting of chrono, basic-format-string.
+  // 202304 P2510R3 Formatting pointers
   values = {
-v = 202207;
+v = 202304;
 cxxmin = 20;
 hosted = yes;
   };
diff --git a/libstdc++-v3/include/bits/version.h 
b/libstdc++-v3/include/bits/version.h
index 9f8673395dab..5cd0e213 100644
--- a/libstdc++-v3/include/bits/version.h
+++ b/libstdc++-v3/include/bits/version.h
@@ -1305,9 +1305,9 @@
 
 #if !defined(__cpp_lib_format)
 # if (__cplusplus >= 202002L) && _GLIBCXX_HOSTED
-#  define __glibcxx_format 202207L
+#  define __glibcxx_format 202304L
 #  if defined(__glibcxx_want_all) || defined(__glibcxx_want_format)
-#   define __cpp_lib_format 202207L
+#   define __cpp_lib_format 202304L
 #  endif
 # endif
 #endif /* !defined(__cpp_lib_format) && defined(__glibcxx_want_format) */
diff --git a/libstdc++-v3/include/std/format b/libstdc++-v3/include/std/format
index fe00e547671f..2669ad8c2440 100644
--- a/libstdc++-v3/include/std/format
+++ b/libstdc++-v3/include/std/format
@@ -2342,13 +2342,7 @@ namespace __format
 
 // _GLIBCXX_RESOLVE_LIB_DEFECTS
 // P2510R3 Formatting pointers
-#if __glibcxx_format >= 202304L || ! defined __STRICT_ANSI__
-# define _GLIBCXX_P2518R3 1
-#else
-# define _GLIBCXX_P2518R3 0
-#endif
-
-#if _GLIBCXX_P2518R3
+#if __glibcxx_format >= 202304L
__first = __spec._M_parse_zero_fill(__first, __last);
if (__finished())
  return __first;
@@ -2360,11 +2354,9 @@ namespace __format
  {
if (*__first == 'p')
  ++__first;
-#if _GLIBCXX_P2518R3
+#if __glibcxx_format >= 202304L
else if (*__first == 'P')
{
- // _GLIBCXX_RESOLVE_LIB_DEFECTS
- // P2510R3 Formatting pointers
  __spec._M_type = __format::_Pres_P;
  ++__first;
}
@@ -2388,7 +2380,7 @@ namespace __format
  int __n = __ptr - __buf;
  __buf[0] = '0';
  __buf[1] = 'x';
-#if _GLIBCXX_P2518R3
+#if __glibcxx_format >= 202304L
  if (_M_spec._M_type == __format::_Pres_P)
{
  __buf[1] = 'X';
@@ -2413,7 +2405,7 @@ namespace __format
}
 #endif
 
-#if _GLIBCXX_P2518R3
+#if __glibcxx_format >= 202304L
  if (_M_spec._M_zero_fill)
{
  size_t __width = _M_spec._M_get_width(__fc);
diff --git a/libstdc++-v3/testsuite/std/format/functions/format.cc 
b/libstdc++-v3/testsuite/std/format/functions/format.cc
index 78cc1ab482ad..5152bb0b0d06 100644
--- a/libstdc++-v3/testsuite/std/format/functions/format.cc
+++ b/libstdc++-v3/testsuite/std/format/functions/format.cc
@@ -458,7 +458,7 @@ test_pointer()
   s = std::format("{:20} {:20p}", p, pc);
   VERIFY( s == (str_int + ' ' + str_int) );
 
-#if __cplusplus > 202302L || ! defined __STRICT_ANS

[gcc r15-2447] libstdc++: Define C++26 member visit for std::variant [PR110356]

[Jonathan Wakely via Gcc-cvs]

https://gcc.gnu.org/g:f6f2c78d9db37228baa9d1f9926b0c120e24016f

commit r15-2447-gf6f2c78d9db37228baa9d1f9926b0c120e24016f
Author: Jonathan Wakely 
Date:   Tue Jul 9 12:12:56 2024 +0100

libstdc++: Define C++26 member visit for std::variant [PR110356]

Implement the std::variant changes from P2637R3.

libstdc++-v3/ChangeLog:

PR libstdc++/110356
* include/bits/version.def (variant): Update for C++26.
* include/bits/version.h: Regenerate.
* include/std/variant (variant::visit): New member functions.
* testsuite/20_util/variant/visit.cc: Check second alternative.
* testsuite/20_util/variant/visit_member.cc: New test.

Diff:
---
 libstdc++-v3/include/bits/version.def  |   5 +
 libstdc++-v3/include/bits/version.h|   7 +-
 libstdc++-v3/include/std/variant   |  46 
 libstdc++-v3/testsuite/20_util/variant/visit.cc|   5 +-
 .../testsuite/20_util/variant/visit_member.cc  | 117 +
 5 files changed, 178 insertions(+), 2 deletions(-)

diff --git a/libstdc++-v3/include/bits/version.def 
b/libstdc++-v3/include/bits/version.def
index bcb33c18aa4d..806f1e9549be 100644
--- a/libstdc++-v3/include/bits/version.def
+++ b/libstdc++-v3/include/bits/version.def
@@ -478,6 +478,11 @@ ftms = {
 
 ftms = {
   name = variant;
+  values = {
+v = 202306;
+cxxmin = 26;
+extra_cond = "__cpp_concepts >= 202002L && __cpp_constexpr >= 201811L && 
__cpp_explicit_this_parameter";
+  };
   values = {
 v = 202106;
 cxxmin = 20;
diff --git a/libstdc++-v3/include/bits/version.h 
b/libstdc++-v3/include/bits/version.h
index 4d1af34bf8d5..e8ca0faf5dcd 100644
--- a/libstdc++-v3/include/bits/version.h
+++ b/libstdc++-v3/include/bits/version.h
@@ -529,7 +529,12 @@
 #undef __glibcxx_want_type_trait_variable_templates
 
 #if !defined(__cpp_lib_variant)
-# if (__cplusplus >= 202002L) && (__cpp_concepts >= 202002L && __cpp_constexpr 
>= 201811L)
+# if (__cplusplus >  202302L) && (__cpp_concepts >= 202002L && __cpp_constexpr 
>= 201811L && __cpp_explicit_this_parameter)
+#  define __glibcxx_variant 202306L
+#  if defined(__glibcxx_want_all) || defined(__glibcxx_want_variant)
+#   define __cpp_lib_variant 202306L
+#  endif
+# elif (__cplusplus >= 202002L) && (__cpp_concepts >= 202002L && 
__cpp_constexpr >= 201811L)
 #  define __glibcxx_variant 202106L
 #  if defined(__glibcxx_want_all) || defined(__glibcxx_want_variant)
 #   define __cpp_lib_variant 202106L
diff --git a/libstdc++-v3/include/std/variant b/libstdc++-v3/include/std/variant
index 3a23d9bc66d0..d0f7bd0242f8 100644
--- a/libstdc++-v3/include/std/variant
+++ b/libstdc++-v3/include/std/variant
@@ -1390,6 +1390,12 @@ namespace __detail::__variant
 constexpr __detail::__variant::__visit_result_t<_Visitor, _Variants...>
 visit(_Visitor&&, _Variants&&...);
 
+#if __cplusplus > 201703L
+  template
+constexpr _Res
+visit(_Visitor&&, _Variants&&...);
+#endif
+
   template
 _GLIBCXX20_CONSTEXPR
 inline enable_if_t<(is_move_constructible_v<_Types> && ...)
@@ -1758,6 +1764,46 @@ namespace __detail::__variant
  }, __rhs);
   }
 
+#if __cpp_lib_variant >= 202306L // >= C++26
+  // [variant.visit], visitation
+
+  /** Simple visitation for a single variant
+   *
+   * To visit a single variant you can use `var.visit(visitor)`
+   * instead of `std::visit(visitor, var)`.
+   *
+   * @since C++26
+   */
+  template
+   constexpr decltype(auto)
+   visit(this _Self&& __self, _Visitor&& __vis)
+   {
+ using _CVar = __conditional_t>,
+   const variant, variant>;
+ using _Var = __conditional_t,
+  _CVar&&, _CVar&>;
+ return std::visit(std::forward<_Visitor>(__vis), (_Var)__self);
+   }
+
+  /** Simple visitation for a single variant, with explicit return type
+   *
+   * To visit a single variant you can use `var.visit(visitor)`
+   * instead of `std::visit(visitor, var)`.
+   *
+   * @since C++26
+   */
+  template
+   constexpr _Res
+   visit(this _Self&& __self, _Visitor&& __vis)
+   {
+ using _CVar = __conditional_t>,
+   const variant, variant>;
+ using _Var = __conditional_t,
+  _CVar&&, _CVar&>;
+ return std::visit<_Res>(std::forward<_Visitor>(__vis), (_Var)__self);
+   }
+#endif
+
 private:
   template
friend constexpr decltype(auto)
diff --git a/libstdc++-v3/testsuite/20_util/variant/visit.cc 
b/libstdc++-v3/testsuite/20_util/variant/visit.cc
index 7f79e6107aba..6edc7d7c0283 100644
--- a/libstdc++-v3/testsuite/20_util/variant/visit.cc
+++ b/libstdc++-v3/testsuite/20_util/variant/visit.cc
@@ -18,7 +18,7 @@
 // { dg-do run { target c++17 } }
 
 #include 
-#include 
+#include  // ref

[gcc r15-2449] libstdc++: Bump __cpp_lib_format value for std::runtime_format

[Jonathan Wakely via Libstdc++-cvs]

https://gcc.gnu.org/g:96f789d25f99e889fab8cba2c20cd6f80a9b4a0a

commit r15-2449-g96f789d25f99e889fab8cba2c20cd6f80a9b4a0a
Author: Jonathan Wakely 
Date:   Tue Jul 16 10:22:40 2024 +0100

libstdc++: Bump __cpp_lib_format value for std::runtime_format

We already supported this feature, but couldn't set the feature test
macro accordingly because we were missing support for older features.
Now that we support all the older  changes, we can set this to
the correct value.

libstdc++-v3/ChangeLog:

* include/bits/version.def (format): Update value for C++26.
* include/bits/version.h: Regenerate.
* include/std/format (runtime_format, wruntime_format): Check
__cpp_lib_format instead of __cplusplus.
* testsuite/std/format/functions/format.cc: Update expected
value of macro for C++26 mode.

Diff:
---
 libstdc++-v3/include/bits/version.def | 2 +-
 libstdc++-v3/include/bits/version.h   | 4 ++--
 libstdc++-v3/include/std/format   | 2 +-
 libstdc++-v3/testsuite/std/format/functions/format.cc | 4 ++--
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/libstdc++-v3/include/bits/version.def 
b/libstdc++-v3/include/bits/version.def
index ec330911d665..ee0a9e45c441 100644
--- a/libstdc++-v3/include/bits/version.def
+++ b/libstdc++-v3/include/bits/version.def
@@ -1171,7 +1171,7 @@ ftms = {
   // 202306 P2637R3 Member visit
   // 202311 P2918R2 Runtime format strings II
   values = {
-v = 202306;
+v = 202311;
 cxxmin = 26;
 hosted = yes;
   };
diff --git a/libstdc++-v3/include/bits/version.h 
b/libstdc++-v3/include/bits/version.h
index 148ee87e087c..cee497d7443f 100644
--- a/libstdc++-v3/include/bits/version.h
+++ b/libstdc++-v3/include/bits/version.h
@@ -1310,9 +1310,9 @@
 
 #if !defined(__cpp_lib_format)
 # if (__cplusplus >  202302L) && _GLIBCXX_HOSTED
-#  define __glibcxx_format 202306L
+#  define __glibcxx_format 202311L
 #  if defined(__glibcxx_want_all) || defined(__glibcxx_want_format)
-#   define __cpp_lib_format 202306L
+#   define __cpp_lib_format 202311L
 #  endif
 # elif (__cplusplus >= 202002L) && _GLIBCXX_HOSTED
 #  define __glibcxx_format 202304L
diff --git a/libstdc++-v3/include/std/format b/libstdc++-v3/include/std/format
index 715fdf934924..3280dadfb90e 100644
--- a/libstdc++-v3/include/std/format
+++ b/libstdc++-v3/include/std/format
@@ -155,7 +155,7 @@ namespace __format
   = basic_format_string...>;
 #endif
 
-#if __cplusplus > 202302L
+#if __cpp_lib_format >= 202311L // >= C++26
   [[__gnu__::__always_inline__]]
   inline __format::_Runtime_format_string
   runtime_format(string_view __fmt) noexcept
diff --git a/libstdc++-v3/testsuite/std/format/functions/format.cc 
b/libstdc++-v3/testsuite/std/format/functions/format.cc
index 0549d171e5a2..7fc420170458 100644
--- a/libstdc++-v3/testsuite/std/format/functions/format.cc
+++ b/libstdc++-v3/testsuite/std/format/functions/format.cc
@@ -8,7 +8,7 @@
 # error "Feature test macro for std::format is missing in "
 #elif __cpp_lib_format < 202110L
 # error "Feature test macro for std::format has wrong value in "
-#elif __cplusplus > 202302L && __cpp_lib_format < 202306L
+#elif __cplusplus > 202302L && __cpp_lib_format < 202311L
 # error "Feature test macro for std::format has wrong value in "
 #endif
 
@@ -24,7 +24,7 @@
 # error "Feature test macro for std::format is missing in "
 #elif __cpp_lib_format < 202110L
 # error "Feature test macro for std::format has wrong value in "
-#elif __cplusplus > 202302L && __cpp_lib_format < 202306L
+#elif __cplusplus > 202302L && __cpp_lib_format < 202311L
 # error "Feature test macro for std::format has wrong value in "
 #endif

[gcc r15-2450] libstdc++: Only append "@euro" to locale names for Glibc testing

[Jonathan Wakely via Gcc-cvs]

https://gcc.gnu.org/g:5dd1f0d69f51dc6b290977503dcfb7734948e841

commit r15-2450-g5dd1f0d69f51dc6b290977503dcfb7734948e841
Author: Jonathan Wakely 
Date:   Wed Jul 31 12:03:32 2024 +0100

libstdc++: Only append "@euro" to locale names for Glibc testing

The testsuite automatically appends "@euro" to "xx.ISO8859-15" locale
names on all targets except FreeBSD, DragonflyBSD, and NetBSD. It should
only be for Glibc, not all non-BSD targets.

libstdc++-v3/ChangeLog:

* testsuite/lib/libstdc++.exp (check_v3_target_namedlocale):
Only append "@euro" to ".ISO8859-15" locales for Glibc.

Diff:
---
 libstdc++-v3/testsuite/lib/libstdc++.exp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libstdc++-v3/testsuite/lib/libstdc++.exp 
b/libstdc++-v3/testsuite/lib/libstdc++.exp
index 18331c80bc27..2510c7f4cbb9 100644
--- a/libstdc++-v3/testsuite/lib/libstdc++.exp
+++ b/libstdc++-v3/testsuite/lib/libstdc++.exp
@@ -1032,7 +1032,7 @@ proc check_v3_target_namedlocale { args } {
puts $f "strcpy(result, name);"
puts $f "#if defined __FreeBSD__ || defined __DragonFly__ || defined 
__NetBSD__"
puts $f "/* fall-through */"
-   puts $f "#else"
+   puts $f "#elif defined __GLIBC__"
puts $f "if (strstr(result, \"ISO8859-15\")) {"
puts $f "strcat(result, \"@euro\");"
puts $f "}"

[gcc r15-2451] libstdc++: Handle strerror returning null

[Jonathan Wakely via Libstdc++-cvs]

https://gcc.gnu.org/g:ee4cc961ce399f2f3ac92fd711551677d61771da

commit r15-2451-gee4cc961ce399f2f3ac92fd711551677d61771da
Author: Jonathan Wakely 
Date:   Wed Jul 31 13:56:14 2024 +0100

libstdc++: Handle strerror returning null

The linux man page for strerror says that some systems return NULL for
an unknown error number. That violates the C and POSIX standards, but we
can esily handle it to avoid a segfault.

libstdc++-v3/ChangeLog:

* src/c++11/system_error.cc (strerror_string): Handle
non-conforming NULL return from strerror.

Diff:
---
 libstdc++-v3/src/c++11/system_error.cc | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/libstdc++-v3/src/c++11/system_error.cc 
b/libstdc++-v3/src/c++11/system_error.cc
index d01451ba1ef6..38bc04461101 100644
--- a/libstdc++-v3/src/c++11/system_error.cc
+++ b/libstdc++-v3/src/c++11/system_error.cc
@@ -110,7 +110,11 @@ namespace
 #else
   string strerror_string(int err)
   {
-return strerror(err); // XXX Not thread-safe.
+auto str = strerror(err); // XXX Not thread-safe.
+if (str) [[__likely__]]
+  return str;
+// strerror should not return NULL, but some implementations do.
+return "Unknown error";
   }
 #endif

[gcc r15-2448] libstdc++: Define C++26 member visit for std::basic_format_arg [PR110356]

[Jonathan Wakely via Libstdc++-cvs]

https://gcc.gnu.org/g:08782a5d92bacc3af947caf79d19bf25eae02e7b

commit r15-2448-g08782a5d92bacc3af947caf79d19bf25eae02e7b
Author: Jonathan Wakely 
Date:   Tue Jul 16 10:14:45 2024 +0100

libstdc++: Define C++26 member visit for std::basic_format_arg [PR110356]

Implement the std::format changes from P2637R3. This adds visit member
functions to std::basic_format_arg and deprecates the non-member
function std::visit_format_arg.

libstdc++-v3/ChangeLog:

PR libstdc++/110356
* include/bits/c++config (_GLIBCXX26_DEPRECATED): Define.
(_GLIBCXX26_DEPRECATED_SUGGEST): Define.
* include/bits/version.def (format): Update for C++26.
* include/bits/version.h: Regenerate.
* include/std/format (basic_format_arg::visit): New member
functions.
(visit_format_arg): Add deprecated attribute.
* testsuite/std/format/arguments/args.cc: Expect deprecated
warnings. Check member visit.
* testsuite/std/format/functions/format.cc: Update expected
value for __cpp_lib_format macro.
* testsuite/std/format/parse_ctx.cc: Add dg-warning for
deprecation.

Diff:
---
 libstdc++-v3/include/bits/c++config| 10 +
 libstdc++-v3/include/bits/version.def  |  2 +-
 libstdc++-v3/include/bits/version.h|  4 +-
 libstdc++-v3/include/std/format| 16 
 .../testsuite/std/format/arguments/args.cc | 43 ++
 .../testsuite/std/format/functions/format.cc   |  4 +-
 libstdc++-v3/testsuite/std/format/parse_ctx.cc |  2 +-
 7 files changed, 75 insertions(+), 6 deletions(-)

diff --git a/libstdc++-v3/include/bits/c++config 
b/libstdc++-v3/include/bits/c++config
index 6dca2d9467aa..0f0cc7cd6599 100644
--- a/libstdc++-v3/include/bits/c++config
+++ b/libstdc++-v3/include/bits/c++config
@@ -90,6 +90,8 @@
 //   _GLIBCXX20_DEPRECATED_SUGGEST( string-literal )
 //   _GLIBCXX23_DEPRECATED
 //   _GLIBCXX23_DEPRECATED_SUGGEST( string-literal )
+//   _GLIBCXX26_DEPRECATED
+//   _GLIBCXX26_DEPRECATED_SUGGEST( string-literal )
 #ifndef _GLIBCXX_USE_DEPRECATED
 # define _GLIBCXX_USE_DEPRECATED 1
 #endif
@@ -143,6 +145,14 @@
 # define _GLIBCXX23_DEPRECATED_SUGGEST(ALT)
 #endif
 
+#if defined(__DEPRECATED) && (__cplusplus >= 202400L)
+# define _GLIBCXX26_DEPRECATED [[__deprecated__]]
+# define _GLIBCXX26_DEPRECATED_SUGGEST(ALT) _GLIBCXX_DEPRECATED_SUGGEST(ALT)
+#else
+# define _GLIBCXX26_DEPRECATED
+# define _GLIBCXX26_DEPRECATED_SUGGEST(ALT)
+#endif
+
 // Macros for ABI tag attributes.
 #ifndef _GLIBCXX_ABI_TAG_CXX11
 # define _GLIBCXX_ABI_TAG_CXX11 __attribute ((__abi_tag__ ("cxx11")))
diff --git a/libstdc++-v3/include/bits/version.def 
b/libstdc++-v3/include/bits/version.def
index 806f1e9549be..ec330911d665 100644
--- a/libstdc++-v3/include/bits/version.def
+++ b/libstdc++-v3/include/bits/version.def
@@ -1171,7 +1171,7 @@ ftms = {
   // 202306 P2637R3 Member visit
   // 202311 P2918R2 Runtime format strings II
   values = {
-v = 202305;
+v = 202306;
 cxxmin = 26;
 hosted = yes;
   };
diff --git a/libstdc++-v3/include/bits/version.h 
b/libstdc++-v3/include/bits/version.h
index e8ca0faf5dcd..148ee87e087c 100644
--- a/libstdc++-v3/include/bits/version.h
+++ b/libstdc++-v3/include/bits/version.h
@@ -1310,9 +1310,9 @@
 
 #if !defined(__cpp_lib_format)
 # if (__cplusplus >  202302L) && _GLIBCXX_HOSTED
-#  define __glibcxx_format 202305L
+#  define __glibcxx_format 202306L
 #  if defined(__glibcxx_want_all) || defined(__glibcxx_want_format)
-#   define __cpp_lib_format 202305L
+#   define __cpp_lib_format 202306L
 #  endif
 # elif (__cplusplus >= 202002L) && _GLIBCXX_HOSTED
 #  define __glibcxx_format 202304L
diff --git a/libstdc++-v3/include/std/format b/libstdc++-v3/include/std/format
index 6a88705ec7b9..715fdf934924 100644
--- a/libstdc++-v3/include/std/format
+++ b/libstdc++-v3/include/std/format
@@ -3346,6 +3346,18 @@ namespace __format
   explicit operator bool() const noexcept
   { return _M_type != __format::_Arg_none; }
 
+#if __cpp_lib_format >= 202306L // >= C++26
+  template
+   decltype(auto)
+   visit(this basic_format_arg __arg, _Visitor&& __vis)
+   { return __arg._M_visit(std::forward<_Visitor>(__vis), __arg._M_type); }
+
+  template
+   _Res
+   visit(this basic_format_arg __arg, _Visitor&& __vis)
+   { return __arg._M_visit(std::forward<_Visitor>(__vis), __arg._M_type); }
+#endif
+
 private:
   template
friend class basic_format_args;
@@ -3631,6 +3643,7 @@ namespace __format
 };
 
   template
+_GLIBCXX26_DEPRECATED_SUGGEST("std::basic_format_arg::visit")
 inline decltype(auto)
 visit_format_arg(_Visitor&& __vis, basic_format_arg<_Context> __arg)
 {
@@ -3666,6 +3679,8 @@ namespace __format
   }
   };
 
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wdepr

[gcc r15-2452] [PR rtl-optimization/116136] Fix previously latent SUBREG simplification bug

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:89ed5ab210b5e30c325b92e9e40c50e337be1b44

commit r15-2452-g89ed5ab210b5e30c325b92e9e40c50e337be1b44
Author: Jeff Law 
Date:   Wed Jul 31 10:15:01 2024 -0600

[PR rtl-optimization/116136] Fix previously latent SUBREG simplification bug

This fixes a testsuite regression seen on m68k after some of the recent 
ext-dce
changes.  Ultimately Richard S and I have concluded the bug was a latent 
issue
in subreg simplification.

Essentially when simplifying something like

(set (target:M1) (subreg:M1 (subreg:M2 (reg:M1) 0) 0))

Where M1 > M2.  We'd simplify to:

(set (target:M1) (reg:M1))

The problem is on a big endian target that's wrong.   Consider if M1 is DI 
and
M2 is SI.The original should extract bits 32..63 from the source 
register
and store them into bits 0..31 of the target register. In the simplified 
form
it's just a copy, so bits 0..63 of the source end up bits 0..63 of the 
target.

This shows up as the following regressions on the m68k:

> Tests that now fail, but worked before (3 tests):
>
> gcc: gcc.c-torture/execute/960416-1.c   -O2  execution test
> gcc: gcc.c-torture/execute/960416-1.c   -O2 -flto -fno-use-linker-plugin 
-flto-partition=none  execution test
> gcc: gcc.c-torture/execute/960416-1.c   -Os  execution test

The fix is pretty trivial, instead of hardcoding "0" as the byte offset in 
the
test for the simplification, instead we need to use the 
subreg_lowpart_offset.

Anyway, bootstrapped and regression tested on m68k and x86_64 and tested on 
the
other embedded targets as well without regressions.  Naturally it fixes the
regression noted above.  I haven't see other testsuite improvements when I 
spot
checked some of the big endian crosses.

PR rtl-optimization/116136
gcc/
* simplify-rtx.cc (simplify_context::simplify_subreg): Check
that we're working with the lowpart offset rather than byte 0.

Diff:
---
 gcc/simplify-rtx.cc | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
index a49eefb34d43..a20a61c5dddb 100644
--- a/gcc/simplify-rtx.cc
+++ b/gcc/simplify-rtx.cc
@@ -7744,8 +7744,9 @@ simplify_context::simplify_subreg (machine_mode 
outermode, rtx op,
return NULL_RTX;
 
   if (outermode == innermostmode
- && known_eq (byte, 0U)
- && known_eq (SUBREG_BYTE (op), 0))
+ && known_eq (byte, subreg_lowpart_offset (outermode, innermode))
+ && known_eq (SUBREG_BYTE (op),
+  subreg_lowpart_offset (innermode, innermostmode)))
return SUBREG_REG (op);
 
   /* Work out the memory offset of the final OUTERMODE value relative

[gcc r15-2453] libstdc++: drop bogus 'dg_do run' directive

[Sam James via Gcc-cvs]

https://gcc.gnu.org/g:f7221267238395ff66da962271fdcf7c7f9bb7dd

commit r15-2453-gf7221267238395ff66da962271fdcf7c7f9bb7dd
Author: Sam James 
Date:   Tue Jul 30 21:39:48 2024 +0100

libstdc++: drop bogus 'dg_do run' directive

We already have a valid 'dg-do run' (- vs _) directive, so drop the bogus
one.

libstdc++-v3/ChangeLog:
* testsuite/28_regex/traits/char/translate.cc: Drop bogus 'dg_do 
run'.

Diff:
---
 libstdc++-v3/testsuite/28_regex/traits/char/translate.cc | 1 -
 1 file changed, 1 deletion(-)

diff --git a/libstdc++-v3/testsuite/28_regex/traits/char/translate.cc 
b/libstdc++-v3/testsuite/28_regex/traits/char/translate.cc
index e2552e3cbf05..65119e67e25b 100644
--- a/libstdc++-v3/testsuite/28_regex/traits/char/translate.cc
+++ b/libstdc++-v3/testsuite/28_regex/traits/char/translate.cc
@@ -1,4 +1,3 @@
-// { dg_do run }
 // { dg-do run { target c++11 } }
 // { dg-timeout-factor 2 }

[gcc(refs/users/meissner/heads/work174)] Add power5+ to arch flags.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:d964bf62dfeeb413f2af87994b677c85aef6408d

commit d964bf62dfeeb413f2af87994b677c85aef6408d
Author: Michael Meissner 
Date:   Wed Jul 31 12:23:55 2024 -0400

Add power5+ to arch flags.

2024-07-31  Michael Meissner  

gcc/

* config/rs6000/rs6000-arch.def (ARCH_MASK_POWER5X): Add power5+
support.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use arch
masks for power4, power5, power5+, and power6.
* config/rs6000/rs6000.cc (get_arch_flags): Add support for setting 
arch
flags for non power* processors.  Add support for power5+.
(report_architecture_mismatch): Improve error message.

Diff:
---
 gcc/config/rs6000/rs6000-arch.def |  1 +
 gcc/config/rs6000/rs6000-c.cc |  8 
 gcc/config/rs6000/rs6000.cc   | 20 +---
 3 files changed, 22 insertions(+), 7 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-arch.def 
b/gcc/config/rs6000/rs6000-arch.def
index 6725736076da..e5b6e9581331 100644
--- a/gcc/config/rs6000/rs6000-arch.def
+++ b/gcc/config/rs6000/rs6000-arch.def
@@ -39,6 +39,7 @@
 
 ARCH_EXPAND(POWER4,  "power4")
 ARCH_EXPAND(POWER5,  "power5")
+ARCH_EXPAND(POWER5X, "power5+")
 ARCH_EXPAND(POWER6,  "power6")
 ARCH_EXPAND(POWER7,  "power7")
 ARCH_EXPAND(POWER8,  "power8")
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index a8a6a956874f..d7b1625f0867 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -420,13 +420,13 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags,
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
   if ((flags & OPTION_MASK_POWERPC64) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
-  if ((flags & OPTION_MASK_MFCRF) != 0)
+  if ((arch_flags & ARCH_MASK_POWER4) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
-  if ((flags & OPTION_MASK_POPCNTB) != 0)
+  if ((arch_flags & ARCH_MASK_POWER5) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
-  if ((flags & OPTION_MASK_FPRND) != 0)
+  if ((arch_flags & ARCH_MASK_POWER5X) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
-  if ((flags & OPTION_MASK_CMPB) != 0)
+  if ((arch_flags & ARCH_MASK_POWER6) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
   if ((arch_flags & ARCH_MASK_POWER7) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 19adc66cc801..ec1cf85de12f 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1856,6 +1856,8 @@ get_arch_flags (int cpu_index)
 
   case PROCESSOR_POWER5:
ret |= ARCH_MASK_POWER5;
+   if (TARGET_FPRND)
+ ret |= ARCH_MASK_POWER5X;
/* fall through.  */
 
   case PROCESSOR_POWER4:
@@ -1863,6 +1865,18 @@ get_arch_flags (int cpu_index)
break;
 
   default:
+   /* For other processors, set the arch flags based on the ISA bits.  */
+   if (TARGET_MFCRF)
+ ret |= ARCH_MASK_POWER4;
+
+   if (TARGET_POPCNTB)
+ ret |= ARCH_MASK_POWER5;
+
+   if (TARGET_FPRND)
+ ret |= ARCH_MASK_POWER5X;
+
+   if (TARGET_CMPB)
+ ret |= ARCH_MASK_POWER6;
break;
   }
 
@@ -25359,19 +25373,19 @@ report_architecture_mismatch (void)
   OPTION_MASK_P9_VECTOR | OPTION_MASK_P9_MISC | OPTION_MASK_P9_MINMAX
   | OPTION_MASK_MODULO,
   ARCH_MASK_POWER9,
-  "cpu=power9"
+  "-mcpu=power9"
 },
 
 {
   OPTION_MASK_P8_VECTOR | OPTION_MASK_CRYPTO,
   ARCH_MASK_POWER8,
-  "cpu=power8"
+  "-mcpu=power8"
 },
 
 {
   OPTION_MASK_VSX | OPTION_MASK_POPCNTD,
   ARCH_MASK_POWER7,
-  "cpu=power7"
+  "-mcpu=power7"
 },
   };

[gcc(refs/users/meissner/heads/work174)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:00570ace830d9e811e74752afc14c6d1640fc053

commit 00570ace830d9e811e74752afc14c6d1640fc053
Author: Michael Meissner 
Date:   Wed Jul 31 12:24:41 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 16 
 1 file changed, 16 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index ce7ed892daf3..a40533cb986a 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,19 @@
+ Branch work174, patch #11 
+
+Add power5+ to arch flags.
+
+2024-07-31  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000-arch.def (ARCH_MASK_POWER5X): Add power5+
+   support.
+   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use arch
+   masks for power4, power5, power5+, and power6.
+   * config/rs6000/rs6000.cc (get_arch_flags): Add support for setting arch
+   flags for non power* processors.  Add support for power5+.
+   (report_architecture_mismatch): Improve error message.
+
  Branch work174, patch #10 
 
 Use const HOST_WIDE_INT for arch masks.

[gcc r15-2454] testsuite: Fix for targets not passing argc/argv [PR116154]

[Dimitar Dimitrov via Gcc-cvs]

https://gcc.gnu.org/g:f2fac502097f75e4a098a3321f216523b59030be

commit r15-2454-gf2fac502097f75e4a098a3321f216523b59030be
Author: Dimitar Dimitrov 
Date:   Wed Jul 31 19:20:20 2024 +0300

testsuite: Fix for targets not passing argc/argv [PR116154]

PRU and other simulator targets do not pass any argv arguments
to main.  Instead of erroneously relying on argc==0, use a volatile
variable instead.

I reverted the fix for PR67947 in r6-3891-g8a18fcf4aa1d5c, and made sure
that the updated test case still fails for x86_64:

  $ make check-gcc-c RUNTESTFLAGS="dg-torture.exp=pr67947.c"
  ...
  FAIL: gcc.dg/torture/pr67947.c   -O1  execution test
  ...
  # of expected passes8
  # of unexpected failures8

Fix was suggested by Andrew Pinski in PR116154.  Committed as obvious.

PR testsuite/116154

gcc/testsuite/ChangeLog:

* gcc.dg/torture/pr67947.c: Use volatile variable instead of
argc.

Signed-off-by: Dimitar Dimitrov 

Diff:
---
 gcc/testsuite/gcc.dg/torture/pr67947.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/torture/pr67947.c 
b/gcc/testsuite/gcc.dg/torture/pr67947.c
index 368a8b20cbf0..1016f2579cb2 100644
--- a/gcc/testsuite/gcc.dg/torture/pr67947.c
+++ b/gcc/testsuite/gcc.dg/torture/pr67947.c
@@ -11,11 +11,13 @@ __attribute__((noinline, noclone)) void foo (int x)
 c++;
 }
 
+volatile int t = 1;
+
 int
 main (int argc, char* argv[])
 {
   int j, k, b = 0;
-  if (argc == 0)
+  if (t == 0)
 b = 1;
   for (j = 0; j < 3; j++)
 for (k = 0; k < 1; k++)

[gcc(refs/users/meissner/heads/work174)] Update arch flags.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:8f50688bd3b27770be4017a1ce565d64cbda0ca0

commit 8f50688bd3b27770be4017a1ce565d64cbda0ca0
Author: Michael Meissner 
Date:   Wed Jul 31 12:45:27 2024 -0400

Update arch flags.

2024-07-31  Michael Meissner  

gcc/

* config/rs6000/rs6000.cc (get_arch_flags): Rewrite.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 41 ++---
 1 file changed, 26 insertions(+), 15 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index ec1cf85de12f..c89a6ea8e792 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1827,41 +1827,52 @@ get_arch_flags (int cpu_index)
 {
   HOST_WIDE_INT ret = 0;
 
+  const HOST_WIDE_INT ARCH_COMBO_POWER4  = ARCH_MASK_POWER4;
+  const HOST_WIDE_INT ARCH_COMBO_POWER5  = ARCH_MASK_POWER5  | 
ARCH_COMBO_POWER4;
+  const HOST_WIDE_INT ARCH_COMBO_POWER5X = ARCH_MASK_POWER5X | 
ARCH_COMBO_POWER5;
+  const HOST_WIDE_INT ARCH_COMBO_POWER6  = ARCH_MASK_POWER6  | 
ARCH_COMBO_POWER5X;
+  const HOST_WIDE_INT ARCH_COMBO_POWER7  = ARCH_MASK_POWER7  | 
ARCH_COMBO_POWER6;
+  const HOST_WIDE_INT ARCH_COMBO_POWER8  = ARCH_MASK_POWER8  | 
ARCH_COMBO_POWER7;
+  const HOST_WIDE_INT ARCH_COMBO_POWER9  = ARCH_MASK_POWER9  | 
ARCH_COMBO_POWER8;
+  const HOST_WIDE_INT ARCH_COMBO_POWER10 = ARCH_MASK_POWER10 | 
ARCH_COMBO_POWER9;
+  const HOST_WIDE_INT ARCH_COMBO_POWER11 = ARCH_MASK_POWER11 | 
ARCH_COMBO_POWER10;
+
   if (cpu_index >= 0)
 switch (processor_target_table[cpu_index].processor)
   {
   case PROCESSOR_POWER11:
-   ret |= ARCH_MASK_POWER11;
-   /* fall through.  */
+   ret = ARCH_COMBO_POWER11;
+   break;
 
   case PROCESSOR_POWER10:
-   ret |= ARCH_MASK_POWER10;
-   /* fall through.  */
+   ret = ARCH_COMBO_POWER10;
+   break;
 
   case PROCESSOR_POWER9:
-   ret |= ARCH_MASK_POWER9;
-   /* fall through.  */
+   ret = ARCH_COMBO_POWER9;
+   break;
 
   case PROCESSOR_POWER8:
-   ret |= ARCH_MASK_POWER8;
-   /* fall through.  */
+   ret = ARCH_COMBO_POWER8;
+   break;
 
   case PROCESSOR_POWER7:
-   ret |= ARCH_MASK_POWER7;
-   /* fall through.  */
+   ret = ARCH_COMBO_POWER7;
+   break;
 
+  case PROCESSOR_PPCA2:
   case PROCESSOR_POWER6:
-   ret |= ARCH_MASK_POWER6;
-   /* fall through.  */
+   ret = ARCH_COMBO_POWER6;
+   break;
 
   case PROCESSOR_POWER5:
-   ret |= ARCH_MASK_POWER5;
+   ret = ARCH_COMBO_POWER5;
if (TARGET_FPRND)
  ret |= ARCH_MASK_POWER5X;
-   /* fall through.  */
+   break;
 
   case PROCESSOR_POWER4:
-   ret |= ARCH_MASK_POWER4;
+   ret = ARCH_COMBO_POWER4;
break;
 
   default:

[gcc r15-2455] pru: Enable section anchoring by default

[Dimitar Dimitrov via Gcc-cvs]

https://gcc.gnu.org/g:dcdefe47e18fabc340f9862a27ebd521dfa3d38c

commit r15-2455-gdcdefe47e18fabc340f9862a27ebd521dfa3d38c
Author: Dimitar Dimitrov 
Date:   Sun Jul 14 19:45:09 2024 +0300

pru: Enable section anchoring by default

Loading an arbitrary constant address in a register is expensive for
PRU.  So enable section anchoring by default to utilize the unsigned
byte constant offset operand of load/store instructions.

gcc/ChangeLog:

* common/config/pru/pru-common.cc
(TARGET_OPTION_OPTIMIZATION_TABLE): New definition.
* config/pru/pru.cc (TARGET_MIN_ANCHOR_OFFSET): Set minimal
anchor offset.
(TARGET_MAX_ANCHOR_OFFSET): Set maximum anchor offset.

gcc/testsuite/ChangeLog:

* gcc.target/pru/section-anchors-1.c: New test.
* gcc.target/pru/section-anchors-2.c: New test.

Signed-off-by: Dimitar Dimitrov 

Diff:
---
 gcc/common/config/pru/pru-common.cc  | 12 
 gcc/config/pru/pru.cc|  6 ++
 gcc/testsuite/gcc.target/pru/section-anchors-1.c | 14 ++
 gcc/testsuite/gcc.target/pru/section-anchors-2.c | 14 ++
 4 files changed, 46 insertions(+)

diff --git a/gcc/common/config/pru/pru-common.cc 
b/gcc/common/config/pru/pru-common.cc
index e8dbf28b2d28..cdc31783dfd0 100644
--- a/gcc/common/config/pru/pru-common.cc
+++ b/gcc/common/config/pru/pru-common.cc
@@ -33,4 +33,16 @@ along with GCC; see the file COPYING3.  If not see
 #undef TARGET_EXCEPT_UNWIND_INFO
 #define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info
 
+#undef  TARGET_OPTION_OPTIMIZATION_TABLE
+#define TARGET_OPTION_OPTIMIZATION_TABLE pru_option_optimization_table
+
+/* Set default optimization options.  */
+static const struct default_options pru_option_optimization_table[] =
+  {
+/* Enable section anchors by default at -O1 or higher.  */
+{ OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 },
+
+{ OPT_LEVELS_NONE, 0, NULL, 0 }
+  };
+
 struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
diff --git a/gcc/config/pru/pru.cc b/gcc/config/pru/pru.cc
index 491f66432b37..d07000791872 100644
--- a/gcc/config/pru/pru.cc
+++ b/gcc/config/pru/pru.cc
@@ -3249,6 +3249,12 @@ pru_unwind_word_mode (void)
 #undef TARGET_PRINT_OPERAND_ADDRESS
 #define TARGET_PRINT_OPERAND_ADDRESS pru_print_operand_address
 
+#undef  TARGET_MIN_ANCHOR_OFFSET
+#define TARGET_MIN_ANCHOR_OFFSET  0
+
+#undef  TARGET_MAX_ANCHOR_OFFSET
+#define TARGET_MAX_ANCHOR_OFFSET  255
+
 #undef TARGET_OPTION_OVERRIDE
 #define TARGET_OPTION_OVERRIDE pru_option_override
 
diff --git a/gcc/testsuite/gcc.target/pru/section-anchors-1.c 
b/gcc/testsuite/gcc.target/pru/section-anchors-1.c
new file mode 100644
index ..4c8da5136c31
--- /dev/null
+++ b/gcc/testsuite/gcc.target/pru/section-anchors-1.c
@@ -0,0 +1,14 @@
+/* Ensure section anchors are enabled by default.  */
+
+/* { dg-do assemble } */
+/* { dg-options "-O1" } */
+/* { dg-final { object-size text == 24 } } */
+
+int aa;
+int bb;
+
+int
+test (void)
+{
+  return aa + bb;
+}
diff --git a/gcc/testsuite/gcc.target/pru/section-anchors-2.c 
b/gcc/testsuite/gcc.target/pru/section-anchors-2.c
new file mode 100644
index ..bd5467edad99
--- /dev/null
+++ b/gcc/testsuite/gcc.target/pru/section-anchors-2.c
@@ -0,0 +1,14 @@
+/* Ensure section anchors are enabled by default.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+
+int aa;
+int bb;
+
+int
+test (void)
+{
+  return aa + bb;
+  /* { dg-final { scan-assembler {\n\tldi32\tr\d+, \.LANCHOR\d+} } } */
+}

[gcc(refs/users/meissner/heads/work174)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:e86b226352aeacda9e0db3ad9768670ef0c5f8be

commit e86b226352aeacda9e0db3ad9768670ef0c5f8be
Author: Michael Meissner 
Date:   Wed Jul 31 12:48:55 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index a40533cb986a..f7cb9a767f6d 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,13 @@
+ Branch work174, patch #12 
+
+Update arch flags.
+
+2024-07-31  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000.cc (get_arch_flags): Rewrite.
+
  Branch work174, patch #11 
 
 Add power5+ to arch flags.

[gcc(refs/users/meissner/heads/work174)] Add gp, gfx to arch flags.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:92eb0f0e330ba1b78a339846c0840534bcc11c4c

commit 92eb0f0e330ba1b78a339846c0840534bcc11c4c
Author: Michael Meissner 
Date:   Wed Jul 31 13:03:39 2024 -0400

Add gp, gfx to arch flags.

2024-07-31  Michael Meissner  

gcc/

* config/rs6000/rs6000-arch.def (ARCH_MASK_GP): Add gp.
(ARCH_MASK_GFX): Add gfx.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use arch
masks for gp and gfx.
* config/rs6000/rs6000.cc (get_arch_flags): Add support for gp and 
gfx.

Diff:
---
 gcc/config/rs6000/rs6000-arch.def |  2 ++
 gcc/config/rs6000/rs6000-c.cc |  4 ++--
 gcc/config/rs6000/rs6000.cc   | 10 +-
 3 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-arch.def 
b/gcc/config/rs6000/rs6000-arch.def
index e5b6e9581331..91bd2f638cf3 100644
--- a/gcc/config/rs6000/rs6000-arch.def
+++ b/gcc/config/rs6000/rs6000-arch.def
@@ -37,6 +37,8 @@
the appropriate architecture flags based on the actual processor
enumeration.  */
 
+ARCH_EXPAND(GPOPT,   "gpopt")
+ARCH_EXPAND(GFXOPT,  "gfxopt")
 ARCH_EXPAND(POWER4,  "power4")
 ARCH_EXPAND(POWER5,  "power5")
 ARCH_EXPAND(POWER5X, "power5+")
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index d7b1625f0867..63cf580b20b4 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -414,9 +414,9 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags,
 
   /* rs6000_isa_flags and rs6000_arch_flags based options.  */
   rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
-  if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
+  if ((arch_flags & ARCH_MASK_GPOPT) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
-  if ((flags & OPTION_MASK_PPC_GFXOPT) != 0)
+  if ((arch_flags & ARCH_MASK_GFXOPT) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
   if ((flags & OPTION_MASK_POWERPC64) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index c89a6ea8e792..17c22dc59117 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1827,7 +1827,9 @@ get_arch_flags (int cpu_index)
 {
   HOST_WIDE_INT ret = 0;
 
-  const HOST_WIDE_INT ARCH_COMBO_POWER4  = ARCH_MASK_POWER4;
+  const HOST_WIDE_INT ARCH_COMBO_POWER4  = (ARCH_MASK_POWER4
+   | ARCH_MASK_GPOPT
+   | ARCH_MASK_GFXOPT);
   const HOST_WIDE_INT ARCH_COMBO_POWER5  = ARCH_MASK_POWER5  | 
ARCH_COMBO_POWER4;
   const HOST_WIDE_INT ARCH_COMBO_POWER5X = ARCH_MASK_POWER5X | 
ARCH_COMBO_POWER5;
   const HOST_WIDE_INT ARCH_COMBO_POWER6  = ARCH_MASK_POWER6  | 
ARCH_COMBO_POWER5X;
@@ -1888,6 +1890,12 @@ get_arch_flags (int cpu_index)
 
if (TARGET_CMPB)
  ret |= ARCH_MASK_POWER6;
+
+   if (TARGET_PPC_GPOPT)
+ ret |= ARCH_MASK_GPOPT;
+
+   if (TARGET_PPC_GFXOPT)
+ ret |= ARCH_MASK_GFXOPT;
break;
   }

[gcc(refs/users/meissner/heads/work174)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:0b4cf5fc0a949d2815dfcc044729b1f28d996138

commit 0b4cf5fc0a949d2815dfcc044729b1f28d996138
Author: Michael Meissner 
Date:   Wed Jul 31 13:04:36 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index f7cb9a767f6d..b63c515f38e5 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,17 @@
+ Branch work174, patch #13 
+
+Add gp, gfx to arch flags.
+
+2024-07-31  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000-arch.def (ARCH_MASK_GP): Add gp.
+   (ARCH_MASK_GFX): Add gfx.
+   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use arch
+   masks for gp and gfx.
+   * config/rs6000/rs6000.cc (get_arch_flags): Add support for gp and gfx.
+
  Branch work174, patch #12 
 
 Update arch flags.

[gcc(refs/users/meissner/heads/work174)] Revert changes

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:ed2ed00cc99e53cdbb4ca675882a103c412dc6b8

commit ed2ed00cc99e53cdbb4ca675882a103c412dc6b8
Author: Michael Meissner 
Date:   Wed Jul 31 13:07:18 2024 -0400

Revert changes

Diff:
---
 gcc/ChangeLog.meissner| 14 +-
 gcc/config/rs6000/rs6000-arch.def |  2 --
 gcc/config/rs6000/rs6000-c.cc |  4 ++--
 gcc/config/rs6000/rs6000.cc   | 10 +-
 4 files changed, 4 insertions(+), 26 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index b63c515f38e5..ece220b9bd2c 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,16 +1,4 @@
- Branch work174, patch #13 
-
-Add gp, gfx to arch flags.
-
-2024-07-31  Michael Meissner  
-
-gcc/
-
-   * config/rs6000/rs6000-arch.def (ARCH_MASK_GP): Add gp.
-   (ARCH_MASK_GFX): Add gfx.
-   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use arch
-   masks for gp and gfx.
-   * config/rs6000/rs6000.cc (get_arch_flags): Add support for gp and gfx.
+ Branch work174, patch #13 was reverted 

 
  Branch work174, patch #12 
 
diff --git a/gcc/config/rs6000/rs6000-arch.def 
b/gcc/config/rs6000/rs6000-arch.def
index 91bd2f638cf3..e5b6e9581331 100644
--- a/gcc/config/rs6000/rs6000-arch.def
+++ b/gcc/config/rs6000/rs6000-arch.def
@@ -37,8 +37,6 @@
the appropriate architecture flags based on the actual processor
enumeration.  */
 
-ARCH_EXPAND(GPOPT,   "gpopt")
-ARCH_EXPAND(GFXOPT,  "gfxopt")
 ARCH_EXPAND(POWER4,  "power4")
 ARCH_EXPAND(POWER5,  "power5")
 ARCH_EXPAND(POWER5X, "power5+")
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 63cf580b20b4..d7b1625f0867 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -414,9 +414,9 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags,
 
   /* rs6000_isa_flags and rs6000_arch_flags based options.  */
   rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
-  if ((arch_flags & ARCH_MASK_GPOPT) != 0)
+  if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
-  if ((arch_flags & ARCH_MASK_GFXOPT) != 0)
+  if ((flags & OPTION_MASK_PPC_GFXOPT) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
   if ((flags & OPTION_MASK_POWERPC64) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 17c22dc59117..c89a6ea8e792 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1827,9 +1827,7 @@ get_arch_flags (int cpu_index)
 {
   HOST_WIDE_INT ret = 0;
 
-  const HOST_WIDE_INT ARCH_COMBO_POWER4  = (ARCH_MASK_POWER4
-   | ARCH_MASK_GPOPT
-   | ARCH_MASK_GFXOPT);
+  const HOST_WIDE_INT ARCH_COMBO_POWER4  = ARCH_MASK_POWER4;
   const HOST_WIDE_INT ARCH_COMBO_POWER5  = ARCH_MASK_POWER5  | 
ARCH_COMBO_POWER4;
   const HOST_WIDE_INT ARCH_COMBO_POWER5X = ARCH_MASK_POWER5X | 
ARCH_COMBO_POWER5;
   const HOST_WIDE_INT ARCH_COMBO_POWER6  = ARCH_MASK_POWER6  | 
ARCH_COMBO_POWER5X;
@@ -1890,12 +1888,6 @@ get_arch_flags (int cpu_index)
 
if (TARGET_CMPB)
  ret |= ARCH_MASK_POWER6;
-
-   if (TARGET_PPC_GPOPT)
- ret |= ARCH_MASK_GPOPT;
-
-   if (TARGET_PPC_GFXOPT)
- ret |= ARCH_MASK_GFXOPT;
break;
   }

[gcc(refs/users/meissner/heads/work174)] Revert changes

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:892f4318a3eb42c414386caa67fb32b9c8496902

commit 892f4318a3eb42c414386caa67fb32b9c8496902
Author: Michael Meissner 
Date:   Wed Jul 31 13:14:34 2024 -0400

Revert changes

Diff:
---
 gcc/ChangeLog.meissner  | 190 +
 gcc/config/rs6000/rs6000-arch.def   |  48 
 gcc/config/rs6000/rs6000-c.cc   |  25 +-
 gcc/config/rs6000/rs6000-cpus.def   |   8 +-
 gcc/config/rs6000/rs6000-opts.h |  19 --
 gcc/config/rs6000/rs6000-protos.h   |   5 +-
 gcc/config/rs6000/rs6000.cc | 363 ++--
 gcc/config/rs6000/rs6000.h  |   6 -
 gcc/config/rs6000/rs6000.opt|  19 +-
 gcc/testsuite/gcc.target/powerpc/ppc-target-4.c |  40 +--
 gcc/testsuite/gcc.target/powerpc/pr115688.c |   3 +-
 11 files changed, 136 insertions(+), 590 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index ece220b9bd2c..d9918e29052d 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,192 +1,4 @@
- Branch work174, patch #13 was reverted 

-
- Branch work174, patch #12 
-
-Update arch flags.
-
-2024-07-31  Michael Meissner  
-
-gcc/
-
-   * config/rs6000/rs6000.cc (get_arch_flags): Rewrite.
-
- Branch work174, patch #11 
-
-Add power5+ to arch flags.
-
-2024-07-31  Michael Meissner  
-
-gcc/
-
-   * config/rs6000/rs6000-arch.def (ARCH_MASK_POWER5X): Add power5+
-   support.
-   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use arch
-   masks for power4, power5, power5+, and power6.
-   * config/rs6000/rs6000.cc (get_arch_flags): Add support for setting arch
-   flags for non power* processors.  Add support for power5+.
-   (report_architecture_mismatch): Improve error message.
-
- Branch work174, patch #10 
-
-Use const HOST_WIDE_INT for arch masks.
-
-2024-07-30  Michael Meissner  
-
-   * config/rs6000/rs6000-opts.h (ARCH_MASK_*): Encode the masks as const
-   HOST_WIDE_INT and not as an enumeratio.
-
- Branch work174, patch #9 was reverted 
- Branch work174, patch #8 was reverted 
- Branch work174, patch #7 was reverted 
-
- Branch work174, patch #6 
-
-Update tests to work with architecture flags changes.
-
-Two tests used -mvsx to raise the processor level to at least power7.  These
-tests were rewritten to add cpu=power7 support.
-
-2024-07-29  Michael Meissner  
-
-gcc/testsuite/
-
-   * gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add cpu=power7
-   when we need to add VSX support.  Add test for adding cpu=power7 no-vsx
-   to generate only Altivec instructions.
-   * gcc.target/powerpc/pr115688.c: Add cpu=power7 when requesting VSX
-   instructions.
-
- Branch work174, patch #5 
-
-Do not allow -mvsx to boost processor to power7.
-
-This patch restructures the code so that -mvsx for example will not silently
-convert the processor to power7.  The user must now use -mcpu=power7 or higher.
-This means if the user does -mvsx and the default processor does not have VSX
-support, it will be an error.
-
-2024-07-29  Michael Meissner  
-
-gcc/
-
-   * config/rs6000/rs6000.cc (report_architecture_mismatch): New function.
-   Report an error if the user used an option such as -mvsx when the
-   default processor would not allow the option.
-   (rs6000_option_override_internal): Move some ISA checking code into
-   report_architecture_mismatch.
-
- Branch work174, patch #4 
-
-Use architecture flags for defining _ARCH_PWR macros.
-
-For the newer architectures, this patch changes GCC to define the _ARCH_PWR
-macros using the new architecture flags instead of relying on isa options like
--mpower10.
-
-The -mpower8-internal, -mpower10, and -mpower11 options were removed.  The
--mpower11 option was removed completely, since it was just added in GCC 15.  
The
-other two options were marked as WarnRemoved, and the various ISA bits were
-removed.
-
-TARGET_POWER8 and TARGET_POWER10 were re-defined to use the architeture bits
-instead of the ISA bits.
-
-There are other internal isa bits that aren't removed with this patch because
-the built-in function support uses those bits.
-
-2024-07-29  Michael Meissner  
-
-gcc/
-
-   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add support to
-   use architecture flags instead of ISA flags for setting most of the
-   _ARCH_PWR* macros.
-   (rs6000_cpu_cpp_builtins): Likewise.
-   * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove
- 

[gcc r15-2456] [target/116104] Fix more rtl-checking failures in ext-dce

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:69a9ee05c68bd1fe7f5b3be86baacc8f0a599915

commit r15-2456-g69a9ee05c68bd1fe7f5b3be86baacc8f0a599915
Author: Jeff Law 
Date:   Wed Jul 31 11:30:27 2024 -0600

[target/116104] Fix more rtl-checking failures in ext-dce

More enable-rtl-checking fixes for ext-dce.  Very similar to the one 
recently
posted, this time covering more of the shift ops.

I checked all instances of CONSTANT_P guarding [U]INTVAL and fixed all that
looked wrong.  I also created a dummy assembler/linker so that I could run 
the
GCC testsuite on gcn and verified that wasn't tripping any rtl-checking 
bugs in
ext-dce anymore.

Obviously this has also gone through x86 bootstrap and regression tested.

Pushing to the trunk.

pr target/116104
gcc/
* ext-dce.cc (carry_backpropagate): Change more guards of [U]INTVAL 
to
test CONST_INT_P rather than CONSTANT_P, fixing rtl-checking 
failures.

Diff:
---
 gcc/ext-dce.cc | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/gcc/ext-dce.cc b/gcc/ext-dce.cc
index f7b0eb114180..97a664271183 100644
--- a/gcc/ext-dce.cc
+++ b/gcc/ext-dce.cc
@@ -501,7 +501,7 @@ carry_backpropagate (unsigned HOST_WIDE_INT mask, enum 
rtx_code code, rtx x)
 /* We propagate for the shifted operand, but not the shift
count.  The count is handled specially.  */
 case LSHIFTRT:
-  if (CONSTANT_P (XEXP (x, 1))
+  if (CONST_INT_P (XEXP (x, 1))
  && known_lt (UINTVAL (XEXP (x, 1)), GET_MODE_BITSIZE (mode)))
return mmask & (mask << INTVAL (XEXP (x, 1)));
   return mmask;
@@ -509,7 +509,7 @@ carry_backpropagate (unsigned HOST_WIDE_INT mask, enum 
rtx_code code, rtx x)
 /* We propagate for the shifted operand, but not the shift
count.  The count is handled specially.  */
 case ASHIFTRT:
-  if (CONSTANT_P (XEXP (x, 1))
+  if (CONST_INT_P (XEXP (x, 1))
  && known_lt (UINTVAL (XEXP (x, 1)), GET_MODE_BITSIZE (mode)))
{
  HOST_WIDE_INT sign = 0;
@@ -526,7 +526,7 @@ carry_backpropagate (unsigned HOST_WIDE_INT mask, enum 
rtx_code code, rtx x)
return 0;
   if (XEXP (x, 1) == const1_rtx)
return mmask;
-  if (CONSTANT_P (XEXP (x, 1)))
+  if (CONST_INT_P (XEXP (x, 1)))
{
  if (pow2p_hwi (INTVAL (XEXP (x, 1
return mmask & (mask << (GET_MODE_BITSIZE (mode).to_constant ()
@@ -549,7 +549,7 @@ carry_backpropagate (unsigned HOST_WIDE_INT mask, enum 
rtx_code code, rtx x)
count.  The count is handled specially.  */
 case SS_ASHIFT:
 case US_ASHIFT:
-  if (CONSTANT_P (XEXP (x, 1))
+  if (CONST_INT_P (XEXP (x, 1))
  && UINTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode).to_constant ())
{
  return ((mmask & ~((unsigned HOST_WIDE_INT)mmask

[gcc(refs/users/meissner/heads/work174)] Add rs6000 architecture masks.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:e9d20aedfb2cc5881f0ae01006c224243a32ee0e

commit e9d20aedfb2cc5881f0ae01006c224243a32ee0e
Author: Michael Meissner 
Date:   Wed Jul 31 13:21:05 2024 -0400

Add rs6000 architecture masks.

This patch begins the journey to move architecture bits that are not user 
ISA
options from rs6000_isa_flags to a new targt variable rs6000_arch_flags.  
The
intention is to remove switches that are currently isa options, but the user
should not be using this particular option. For example, we want users to 
use
-mcpu=power10 and not just -mpower10.

2024-07-31  Michael Meissner  

gcc/

* config/rs6000/rs6000-arch.def: New file.
* config/rs6000/rs6000-opts.h: Use rs6000-arch.def to create the
architecture masks needed.
* config/rs6000/rs6000.cc (rs6000_print_isa_options): Add an
architecture flags argument, change all callers.
(get_arch_flag): New function.
(rs6000_debug_reg_global): Update rs6000_print_isa_options calls.
(rs6000_option_override_internal): Likewise.
(struct rs6000_arch_mask): New structure.
(rs6000_arch_masks): New table of architecutre masks and names.
(rs6000_function_specific_save): Save architecture flags.
(rs6000_function_specific_restore): Restore architecture flags.
(rs6000_function_specific_print): Update rs6000_print_isa_options 
calls.
(rs6000_print_options_internal): Add architecture flags options.
(rs6000_can_inline_p): Don't allow inling if the callee requires a 
newer
architecture than the caller.
* config/rs6000/rs6000.opt (rs6000_arch_flags): New target variable.
(x_rs6000_arch_flags): New save/restore field for rs6000_arch_flags.

Diff:
---
 gcc/config/rs6000/rs6000-arch.def |  48 +++
 gcc/config/rs6000/rs6000-opts.h   |  19 
 gcc/config/rs6000/rs6000.cc   | 176 ++
 gcc/config/rs6000/rs6000.opt  |   8 ++
 4 files changed, 234 insertions(+), 17 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-arch.def 
b/gcc/config/rs6000/rs6000-arch.def
new file mode 100644
index ..e5b6e9581331
--- /dev/null
+++ b/gcc/config/rs6000/rs6000-arch.def
@@ -0,0 +1,48 @@
+/* IBM RS/6000 CPU architecture features by processor type.
+   Copyright (C) 1991-2024 Free Software Foundation, Inc.
+   Contributed by Richard Kenner (ken...@vlsi1.ultra.nyu.edu)
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   .  */
+
+/* This file defines architecture features that are based on the -mcpu=
+   option, and not on user options that can be turned on or off.  The intention
+   is for newer processors (power7 and above) to not add new ISA bits for the
+   particular processor, but add these bits.  Otherwise we have to add a bunch
+   of hidden options, just so we have the proper ISA bits.
+
+   For example, in the past we added -mpower8-internal, so that on power8,
+   power9, and power10 would inherit the option, but we had to mark the option
+   generate a warning if the user actually used it.  These options have been
+   moved from the ISA flags to the arch flags.
+
+   To use this, define the macro ARCH_EXPAND which takes 2 arguments.  The
+   first argument is the processor name in upper case, and the second argument
+   is a text name for the processor.
+
+   The function get_arch_flags when passed a processor index number will set up
+   the appropriate architecture flags based on the actual processor
+   enumeration.  */
+
+ARCH_EXPAND(POWER4,  "power4")
+ARCH_EXPAND(POWER5,  "power5")
+ARCH_EXPAND(POWER5X, "power5+")
+ARCH_EXPAND(POWER6,  "power6")
+ARCH_EXPAND(POWER7,  "power7")
+ARCH_EXPAND(POWER8,  "power8")
+ARCH_EXPAND(POWER9,  "power9")
+ARCH_EXPAND(POWER10, "power10")
+ARCH_EXPAND(POWER11, "power11")
diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index 88e357835a5c..c7764e66cd03 100644
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -71,6 +71,25 @@ enum processor_type
PROCESSOR_TITAN
 };
 
+/* Define an enumeration to number the architecture masks.  */
+#undef  ARCH_EXPAND
+#define ARCH_EXPAND(PROC, NAME)ARCH_ENUM_ ## PROC,
+
+enum {
+#include "rs6000-arch.def"
+  ARCH_ENUM_LAST

[gcc(refs/users/meissner/heads/work174)] Make clone_targets use architecture flags.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:19ef02a218312d0971442cac73042211e0fac41f

commit 19ef02a218312d0971442cac73042211e0fac41f
Author: Michael Meissner 
Date:   Wed Jul 31 13:22:36 2024 -0400

Make clone_targets use architecture flags.

This patch expands on the previous patch and changes the target_clones 
support
to use an architecture mask instead of isa bits.

2024-07-31  Michael Meissner  

gcc/

* config/rs6000/rs6000.cc (struct clone_map): Switch to use 
architecture
flags instead of ISA flags for target_clone support.
(rs6000_clone_map): Likewise.
(rs6000_clone_priority): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 22 +++---
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index a77a079e6c44..0b113b68eff9 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -251,17 +251,17 @@ enum {
 
 /* Map compiler ISA bits into HWCAP names.  */
 struct clone_map {
-  HOST_WIDE_INT isa_mask;  /* rs6000_isa mask */
+  HOST_WIDE_INT arch_mask; /* rs6000_arch_mask.  */
   const char *name;/* name to use in __builtin_cpu_supports.  */
 };
 
 static const struct clone_map rs6000_clone_map[CLONE_MAX] = {
-  { 0, "" },   /* Default options.  */
-  { OPTION_MASK_CMPB,  "arch_2_05" },  /* ISA 2.05 (power6).  */
-  { OPTION_MASK_POPCNTD,   "arch_2_06" },  /* ISA 2.06 (power7).  */
-  { OPTION_MASK_P8_VECTOR, "arch_2_07" },  /* ISA 2.07 (power8).  */
-  { OPTION_MASK_P9_VECTOR, "arch_3_00" },  /* ISA 3.0 (power9).  */
-  { OPTION_MASK_POWER10,   "arch_3_1" },   /* ISA 3.1 (power10).  */
+  { 0, "" },   /* Default options.  */
+  { ARCH_MASK_POWER6,  "arch_2_05" },  /* ISA 2.05 (power6).  */
+  { ARCH_MASK_POWER7,  "arch_2_06" },  /* ISA 2.06 (power7).  */
+  { ARCH_MASK_POWER8,  "arch_2_07" },  /* ISA 2.07 (power8).  */
+  { ARCH_MASK_POWER9,  "arch_3_00" },  /* ISA 3.0 (power9).  */
+  { ARCH_MASK_POWER10, "arch_3_1" },   /* ISA 3.1 (power10).  */
 };
 
 
@@ -25433,7 +25433,7 @@ static int
 rs6000_clone_priority (tree fndecl)
 {
   tree fn_opts = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
-  HOST_WIDE_INT isa_masks;
+  HOST_WIDE_INT arch_masks;
   int ret = CLONE_DEFAULT;
   tree attrs = lookup_attribute ("target", DECL_ATTRIBUTES (fndecl));
   const char *attrs_str = NULL;
@@ -25449,12 +25449,12 @@ rs6000_clone_priority (tree fndecl)
fn_opts = target_option_default_node;
 
   if (!fn_opts || !TREE_TARGET_OPTION (fn_opts))
-   isa_masks = rs6000_isa_flags;
+   arch_masks = rs6000_arch_flags;
   else
-   isa_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_isa_flags;
+   arch_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_arch_flags;
 
   for (ret = CLONE_MAX - 1; ret != 0; ret--)
-   if ((rs6000_clone_map[ret].isa_mask & isa_masks) != 0)
+   if ((rs6000_clone_map[ret].arch_mask & arch_masks) != 0)
  break;
 }

[gcc(refs/users/meissner/heads/work174)] Set .machine from the architecture flags

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:c8a3a625126a05f3e88fc9a73b327710d964814c

commit c8a3a625126a05f3e88fc9a73b327710d964814c
Author: Michael Meissner 
Date:   Wed Jul 31 13:25:40 2024 -0400

Set .machine from the architecture flags

This patch switches the handling of .machine to use architecture masks if 
they
exist (power4 through power11).  All of the other PowerPCs will continue to 
use
the existing code for setting the .machine option.

2024-07-31  Michael Meissner  

gcc/

* config/rs6000/rs6000 (rs6000_machine_from_flags): Set .machine 
from
the architecture flags.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 17 +
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 0b113b68eff9..bd84b880fdc7 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -5990,27 +5990,28 @@ rs6000_machine_from_flags (void)
 return "ppc64";
 #endif
 
+  HOST_WIDE_INT arch_flags = rs6000_arch_flags;
   HOST_WIDE_INT flags = rs6000_isa_flags;
 
   /* Disable the flags that should never influence the .machine selection.  */
   flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL
 | OPTION_MASK_ALTIVEC);
 
-  if ((flags & (POWER11_MASKS_SERVER & ~ISA_3_1_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER11) != 0)
 return "power11";
-  if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER10) != 0)
 return "power10";
-  if ((flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER9) != 0)
 return "power9";
-  if ((flags & (ISA_2_7_MASKS_SERVER & ~ISA_2_6_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER8) != 0)
 return "power8";
-  if ((flags & (ISA_2_6_MASKS_SERVER & ~ISA_2_5_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER7) != 0)
 return "power7";
-  if ((flags & (ISA_2_5_MASKS_SERVER & ~ISA_2_4_MASKS)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER6) != 0)
 return "power6";
-  if ((flags & (ISA_2_4_MASKS & ~ISA_2_1_MASKS)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER5) != 0)
 return "power5";
-  if ((flags & ISA_2_1_MASKS) != 0)
+  if ((arch_flags & ARCH_MASK_POWER4) != 0)
 return "power4";
   if ((flags & OPTION_MASK_POWERPC64) != 0)
 return "ppc64";

[gcc(refs/users/meissner/heads/work174)] Use architecture flags for defining _ARCH_PWR macros.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:bd791494894f276e8b8d81790f3a8670d953b8fd

commit bd791494894f276e8b8d81790f3a8670d953b8fd
Author: Michael Meissner 
Date:   Wed Jul 31 13:36:25 2024 -0400

Use architecture flags for defining _ARCH_PWR macros.

For the newer architectures, this patch changes GCC to define the 
_ARCH_PWR
macros using the new architecture flags instead of relying on isa options 
like
-mpower10.

The -mpower8-internal, -mpower10, and -mpower11 options were removed.  The
-mpower11 option was removed completely, since it was just added in GCC 15. 
 The
other two options were marked as WarnRemoved, and the various ISA bits were
removed.

TARGET_POWER8 and TARGET_POWER10 were re-defined to use the architeture bits
instead of the ISA bits.

There are other internal isa bits that aren't removed with this patch 
because
the built-in function support uses those bits.

2024-07-31  Michael Meissner  

gcc/

* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add 
support to
use architecture flags instead of ISA flags for setting most of the
_ARCH_PWR* macros.
(rs6000_cpu_cpp_builtins): Update rs6000_target_modify_macros call.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove
OPTION_MASK_POWER8.
(ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10.
(POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11.
(POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10, and
OPTION_MASK_POWER11.
* config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): 
Update
declaration.
(rs6000_target_modify_macros_ptr): Likewise.
* config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): 
Likewise.
(rs6000_option_override_internal): Use architecture flags instead 
of ISA
flags.
(rs6000_opt_masks): Remove -mpower10 and -mpower11 support.
(rs6000_pragma_target_parse): Use architecture flags as well as ISA
flags.
* config/rs6000/rs6000.h (TARGET_POWER8): New macro.
(TARGET_POWER10): Likewise.
* config/rs6000/rs6000.opt (-mpower8-internal): Remove ISA flag 
bits.
(-mpower10): Likewise.
(-mpower11): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-c.cc | 27 +++
 gcc/config/rs6000/rs6000-cpus.def |  8 +---
 gcc/config/rs6000/rs6000-protos.h |  5 +++--
 gcc/config/rs6000/rs6000.cc   | 19 +++
 gcc/config/rs6000/rs6000.h|  6 ++
 gcc/config/rs6000/rs6000.opt  | 11 ++-
 6 files changed, 38 insertions(+), 38 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 04882c396bfe..c8f33289fa38 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -338,7 +338,8 @@ rs6000_define_or_undefine_macro (bool define_p, const char 
*name)
#pragma GCC target, we need to adjust the macros dynamically.  */
 
 void
-rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
+rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
+HOST_WIDE_INT arch_flags)
 {
   if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
 fprintf (stderr,
@@ -411,7 +412,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
summary of the flags associated with particular cpu
definitions.  */
 
-  /* rs6000_isa_flags based options.  */
+  /* rs6000_isa_flags and rs6000_arch_flags based options.  */
   rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
   if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
@@ -419,23 +420,25 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
   if ((flags & OPTION_MASK_POWERPC64) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
-  if ((flags & OPTION_MASK_MFCRF) != 0)
+  if ((flags & OPTION_MASK_POWERPC64) != 0)
+rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
+  if ((arch_flags & ARCH_MASK_POWER4) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
-  if ((flags & OPTION_MASK_POPCNTB) != 0)
+  if ((arch_flags & ARCH_MASK_POWER5) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
-  if ((flags & OPTION_MASK_FPRND) != 0)
+  if ((arch_flags & ARCH_MASK_POWER5X) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
-  if ((flags & OPTION_MASK_CMPB) != 0)
+  if ((arch_flags & ARCH_MASK_POWER6) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
-  if ((flags & OPTION_MASK_POPCNTD) != 0)
+  if ((arch_flags & ARCH_MASK_POWER7) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
-  if ((flags & OPTION_

[gcc(refs/users/meissner/heads/work174)] Do not allow -mvsx to boost processor to power7.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:505c018b5ecc7b1f05019a3255153718d18e81a3

commit 505c018b5ecc7b1f05019a3255153718d18e81a3
Author: Michael Meissner 
Date:   Wed Jul 31 13:39:16 2024 -0400

Do not allow -mvsx to boost processor to power7.

This patch restructures the code so that -mvsx for example will not silently
convert the processor to power7.  The user must now use -mcpu=power7 or 
higher.
This means if the user does -mvsx and the default processor does not have 
VSX
support, it will be an error.

2024-07-31  Michael Meissner  

gcc/

* config/rs6000/rs6000.cc (report_architecture_mismatch): New 
function.
Report an error if the user used an option such as -mvsx when the
default processor would not allow the option.
(rs6000_option_override_internal): Move some ISA checking code into
report_architecture_mismatch.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 129 +++-
 1 file changed, 79 insertions(+), 50 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index caab770cd951..c89a6ea8e792 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1172,6 +1172,7 @@ const int INSN_NOT_AVAILABLE = -1;
 static void rs6000_print_isa_options (FILE *, int, const char *,
  HOST_WIDE_INT, HOST_WIDE_INT);
 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
+static void report_architecture_mismatch (void);
 
 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
 static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
@@ -3698,7 +3699,6 @@ rs6000_option_override_internal (bool global_init_p)
   bool ret = true;
 
   HOST_WIDE_INT set_masks;
-  HOST_WIDE_INT ignore_masks;
   int cpu_index = -1;
   int tune_index;
   struct cl_target_option *main_target_opt
@@ -3967,59 +3967,13 @@ rs6000_option_override_internal (bool global_init_p)
 dwarf_offset_size = POINTER_SIZE_UNITS;
 #endif
 
-  /* Handle explicit -mno-{altivec,vsx} and turn off all of
- the options that depend on those flags.  */
-  ignore_masks = rs6000_disable_incompatible_switches ();
-
-  /* For the newer switches (vsx, dfp, etc.) set some of the older options,
- unless the user explicitly used the -mno- to disable the code.  */
-  if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
-rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_P9_MINMAX)
-{
-  if (cpu_index >= 0)
-   {
- if (cpu_index == PROCESSOR_POWER9)
-   {
- /* legacy behavior: allow -mcpu=power9 with certain
-capabilities explicitly disabled.  */
- rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
-   }
- else
-   error ("power9 target option is incompatible with %<%s=%> "
-  "for  less than power9", "-mcpu");
-   }
-  else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
-  != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
-  & rs6000_isa_flags_explicit))
-   /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
-  were explicitly cleared.  */
-   error ("%qs incompatible with explicitly disabled options",
-  "-mpower9-minmax");
-  else
-   rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
-}
-  else if (TARGET_P8_VECTOR || TARGET_POWER8 || TARGET_CRYPTO)
-rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_VSX)
-rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_POPCNTD)
-rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_DFP)
-rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_CMPB)
-rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_FPRND)
-rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
-  else if (TARGET_POPCNTB)
-rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
-  else if (TARGET_ALTIVEC)
-rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
+  /* Report trying to use things like -mmodulo to imply -mcpu=power9.  */
+  report_architecture_mismatch ();
 
   /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
  target attribute or pragma which automatically enables both options,
  unless the altivec ABI was set.  This is set by default for 64-bit, but
- not for 32-bit.  Don't move this before the above code using ignore_masks,
+ not for 32-bit.  Don't move this before report_architecture_mismatch
  since it can reset the cleared VSX/ALTIVEC flag again.  */
   if (main_target_opt && !main_target_opt->x_rs6000_altivec_abi)
 {
@@ -25410,6 +25364,81 @@ rs6000_disable_incompatible_switches (void)
   return ignore_masks;
 }
 
+/* In the past, we would boost up the ISA if you sele

[gcc(refs/users/meissner/heads/work174)] Update tests to work with architecture flags changes.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:99e205eb7b5a43789691a29e59d7f7fdffb3b199

commit 99e205eb7b5a43789691a29e59d7f7fdffb3b199
Author: Michael Meissner 
Date:   Wed Jul 31 13:51:08 2024 -0400

Update tests to work with architecture flags changes.

Two tests used -mvsx to raise the processor level to at least power7.  These
tests were rewritten to add cpu=power7 support.

2024-07-31  Michael Meissner  

gcc/testsuite/

* gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add 
cpu=power7
when we need to add VSX support.  Add test for adding cpu=power7 
no-vsx
to generate only Altivec instructions.
* gcc.target/powerpc/pr115688.c: Add cpu=power7 when requesting VSX
instructions.
* gcc.target/powerpc/vsx-cpu-mismatch.c: New test.

Diff:
---
 gcc/testsuite/gcc.target/powerpc/ppc-target-4.c| 40 --
 gcc/testsuite/gcc.target/powerpc/pr115688.c|  3 +-
 .../gcc.target/powerpc/vsx-cpu-mismatch.c  |  8 +
 3 files changed, 40 insertions(+), 11 deletions(-)

diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c 
b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
index db9ba500e0e1..42f5aa354d0a 100644
--- a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
@@ -1,8 +1,8 @@
 /* { dg-do compile { target { powerpc*-*-* } } } */
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -ffast-math -mdejagnu-cpu=power5 -mno-altivec 
-mabi=altivec -fno-unroll-loops" } */
-/* { dg-final { scan-assembler-times "vaddfp" 1 } } */
+/* { dg-options "-O3 -ffast-math -mdejagnu-cpu=power5 -mno-altivec 
-mabi=altivec -fno-unroll-loops" } */
+/* { dg-final { scan-assembler-times "vaddfp" 2 } } */
 /* { dg-final { scan-assembler-times "xvaddsp" 1 } } */
 /* { dg-final { scan-assembler-times "fadds" 1 } } */
 
@@ -18,10 +18,6 @@
 #error "__VSX__ should not be defined."
 #endif
 
-#pragma GCC target("altivec,vsx")
-#include 
-#pragma GCC reset_options
-
 #pragma GCC push_options
 #pragma GCC target("altivec,no-vsx")
 
@@ -33,6 +29,7 @@
 #error "__VSX__ should not be defined."
 #endif
 
+/* Altivec build, generate vaddfp.  */
 void
 av_add (vector float *a, vector float *b, vector float *c)
 {
@@ -40,10 +37,11 @@ av_add (vector float *a, vector float *b, vector float *c)
   unsigned long n = SIZE / 4;
 
   for (i = 0; i < n; i++)
-a[i] = vec_add (b[i], c[i]);
+a[i] = b[i] + c[i];
 }
 
-#pragma GCC target("vsx")
+/* cpu=power7 must be used to enable VSX.  */
+#pragma GCC target("cpu=power7,vsx")
 
 #ifndef __ALTIVEC__
 #error "__ALTIVEC__ should be defined."
@@ -53,6 +51,7 @@ av_add (vector float *a, vector float *b, vector float *c)
 #error "__VSX__ should be defined."
 #endif
 
+/* VSX build on power7, generate xsaddsp.  */
 void
 vsx_add (vector float *a, vector float *b, vector float *c)
 {
@@ -60,11 +59,31 @@ vsx_add (vector float *a, vector float *b, vector float *c)
   unsigned long n = SIZE / 4;
 
   for (i = 0; i < n; i++)
-a[i] = vec_add (b[i], c[i]);
+a[i] = b[i] + c[i];
+}
+
+#pragma GCC target("cpu=power7,no-vsx")
+
+#ifndef __ALTIVEC__
+#error "__ALTIVEC__ should be defined."
+#endif
+
+#ifdef __VSX__
+#error "__VSX__ should not be defined."
+#endif
+
+/* Altivec build on power7 with no VSX, generate vaddfp.  */
+void
+av2_add (vector float *a, vector float *b, vector float *c)
+{
+  unsigned long i;
+  unsigned long n = SIZE / 4;
+
+  for (i = 0; i < n; i++)
+a[i] = b[i] + c[i];
 }
 
 #pragma GCC pop_options
-#pragma GCC target("no-vsx,no-altivec")
 
 #ifdef __ALTIVEC__
 #error "__ALTIVEC__ should not be defined."
@@ -74,6 +93,7 @@ vsx_add (vector float *a, vector float *b, vector float *c)
 #error "__VSX__ should not be defined."
 #endif
 
+/* Default power5 build, generate scalar fadds.  */
 void
 norm_add (float *a, float *b, float *c)
 {
diff --git a/gcc/testsuite/gcc.target/powerpc/pr115688.c 
b/gcc/testsuite/gcc.target/powerpc/pr115688.c
index 5222e66ef170..00c7c301436a 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr115688.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr115688.c
@@ -7,7 +7,8 @@
 
 /* Verify there is no ICE under 32 bit env.  */
 
-__attribute__((target("vsx")))
+/* cpu=power7 must be used to enable VSX.  */
+__attribute__((target("cpu=power7,vsx")))
 int test (void)
 {
   return 0;
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-cpu-mismatch.c 
b/gcc/testsuite/gcc.target/powerpc/vsx-cpu-mismatch.c
new file mode 100644
index ..ff1efd622523
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-cpu-mismatch.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx } */
+/* { dg-options "-O2 -mdejagnu-cpu=power5 -mvsx" } */
+/* { dg-error "‘vsx’ needs at least ‘-mcpu=power7’" } */
+
+/* Make sure -mcpu=power5 -mvsx gives an error if the cpu is not capable of VSX
+   support.  */
+int x;

[gcc(refs/users/meissner/heads/work174)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:763aa18d706801668d3358fb246169dca5b56a58

commit 763aa18d706801668d3358fb246169dca5b56a58
Author: Michael Meissner 
Date:   Wed Jul 31 13:53:32 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 151 -
 1 file changed, 150 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index d9918e29052d..c4f04d2a0134 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,4 +1,153 @@
- Branch work174, patch #1..13 were reverted 

+ Branch work174, patch #25 
+
+Update tests to work with architecture flags changes.
+
+Two tests used -mvsx to raise the processor level to at least power7.  These
+tests were rewritten to add cpu=power7 support.
+
+2024-07-31  Michael Meissner  
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add cpu=power7
+   when we need to add VSX support.  Add test for adding cpu=power7 no-vsx
+   to generate only Altivec instructions.
+   * gcc.target/powerpc/pr115688.c: Add cpu=power7 when requesting VSX
+   instructions.
+   * gcc.target/powerpc/vsx-cpu-mismatch.c: New test.
+
+ Branch work174, patch #24 
+
+Do not allow -mvsx to boost processor to power7.
+
+This patch restructures the code so that -mvsx for example will not silently
+convert the processor to power7.  The user must now use -mcpu=power7 or higher.
+This means if the user does -mvsx and the default processor does not have VSX
+support, it will be an error.
+
+2024-07-31  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000.cc (report_architecture_mismatch): New function.
+   Report an error if the user used an option such as -mvsx when the
+   default processor would not allow the option.
+   (rs6000_option_override_internal): Move some ISA checking code into
+   report_architecture_mismatch.
+
+ Branch work174, patch #23 
+
+Use architecture flags for defining _ARCH_PWR macros.
+
+For the newer architectures, this patch changes GCC to define the _ARCH_PWR
+macros using the new architecture flags instead of relying on isa options like
+-mpower10.
+
+The -mpower8-internal, -mpower10, and -mpower11 options were removed.  The
+-mpower11 option was removed completely, since it was just added in GCC 15.  
The
+other two options were marked as WarnRemoved, and the various ISA bits were
+removed.
+
+TARGET_POWER8 and TARGET_POWER10 were re-defined to use the architeture bits
+instead of the ISA bits.
+
+There are other internal isa bits that aren't removed with this patch because
+the built-in function support uses those bits.
+
+2024-07-31  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add support to
+   use architecture flags instead of ISA flags for setting most of the
+   _ARCH_PWR* macros.
+   (rs6000_cpu_cpp_builtins): Update rs6000_target_modify_macros call.
+   * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove
+   OPTION_MASK_POWER8.
+   (ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10.
+   (POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11.
+   (POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10, and
+   OPTION_MASK_POWER11.
+   * config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): Update
+   declaration.
+   (rs6000_target_modify_macros_ptr): Likewise.
+   * config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): Likewise.
+   (rs6000_option_override_internal): Use architecture flags instead of ISA
+   flags.
+   (rs6000_opt_masks): Remove -mpower10 and -mpower11 support.
+   (rs6000_pragma_target_parse): Use architecture flags as well as ISA
+   flags.
+   * config/rs6000/rs6000.h (TARGET_POWER8): New macro.
+   (TARGET_POWER10): Likewise.
+   * config/rs6000/rs6000.opt (-mpower8-internal): Remove ISA flag bits.
+   (-mpower10): Likewise.
+   (-mpower11): Likewise.
+
+ Branch work174, patch #22 
+
+Set .machine from the architecture flags
+
+This patch switches the handling of .machine to use architecture masks if they
+exist (power4 through power11).  All of the other PowerPCs will continue to use
+the existing code for setting the .machine option.
+
+2024-07-31  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000 (rs6000_machine_from_flags): Set .machine from
+   the architecture flags.
+
+ Branch work174, patch #21 
+
+Make clone_targets use architecture flags.
+
+This patch expands on the previous patch and changes the target_clones support
+to use an architecture mask instead of isa bits.
+
+2024-07-31  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000.cc (struct clone_

[gcc(refs/users/meissner/heads/work174)] Move ARCH_* to rs6000.h.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:931131603c0563365105feb0613079e1a9e1ca23

commit 931131603c0563365105feb0613079e1a9e1ca23
Author: Michael Meissner 
Date:   Wed Jul 31 14:32:02 2024 -0400

Move ARCH_* to rs6000.h.

2024-07-31  Michael Meissner  

gcc/

* config/rs6000/rs6000-opts.h: Move ARCH_* stuff from here.
* config/rs6000/rs6000.h: Move ARCH_* stuff here.

Diff:
---
 gcc/config/rs6000/rs6000-opts.h | 20 
 gcc/config/rs6000/rs6000.h  | 24 
 2 files changed, 24 insertions(+), 20 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index c7764e66cd03..f61cf7d1f662 100644
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -71,26 +71,6 @@ enum processor_type
PROCESSOR_TITAN
 };
 
-/* Define an enumeration to number the architecture masks.  */
-#undef  ARCH_EXPAND
-#define ARCH_EXPAND(PROC, NAME)ARCH_ENUM_ ## PROC,
-
-enum {
-#include "rs6000-arch.def"
-  ARCH_ENUM_LAST
-};
-
-/* Create an architecture mask for the newer architectures (power6 and
-   up)..  */
-#undef  ARCH_EXPAND
-#define ARCH_EXPAND(PROC, NAME)
\
-  static const HOST_WIDE_INT ARCH_MASK_ ## PROC
\
-= HOST_WIDE_INT_1 << ARCH_ENUM_ ## PROC;
-
-#include "rs6000-arch.def"
-
-#undef ARCH_EXPAND
-
 /* Types of costly dependences.  */
 enum rs6000_dependence_cost
 {
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index ccf6a4201542..f011fa2523c0 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -2487,3 +2487,27 @@ while (0)
issues have been resolved.  */
 #define RS6000_DISABLE_SCALAR_MODULO 1
 
+
+
+/* Create the architecture flags.  */
+/* Define an enumeration to number the architecture masks.  */
+#ifdef GCC_HWINT_H
+#undef  ARCH_EXPAND
+#define ARCH_EXPAND(PROC, NAME)ARCH_ENUM_ ## PROC,
+
+enum {
+#include "rs6000-arch.def"
+  ARCH_ENUM_LAST
+};
+
+/* Create an architecture mask for the newer architectures (power6 and
+   up)..  */
+#undef  ARCH_EXPAND
+#define ARCH_EXPAND(PROC, NAME)
\
+  static const HOST_WIDE_INT ARCH_MASK_ ## PROC
\
+= HOST_WIDE_INT_1 << ARCH_ENUM_ ## PROC;
+
+#include "rs6000-arch.def"
+
+#undef ARCH_EXPAND
+#endif /* GCC_HWINT_H.  */

[gcc(refs/users/meissner/heads/work174)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:4e8a80e5233b5665133847d813044fd91bf6dd47

commit 4e8a80e5233b5665133847d813044fd91bf6dd47
Author: Michael Meissner 
Date:   Wed Jul 31 14:32:47 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index c4f04d2a0134..d53cd48662b0 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,14 @@
+ Branch work174, patch #26 
+
+Move ARCH_* to rs6000.h.
+
+2024-07-31  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000-opts.h: Move ARCH_* stuff from here.
+   * config/rs6000/rs6000.h: Move ARCH_* stuff here.
+
  Branch work174, patch #25 
 
 Update tests to work with architecture flags changes.

[gcc r15-2457] dir-locals: apply our C settings in C++ also

[Arsen Arsenovic via Gcc-cvs]

https://gcc.gnu.org/g:ebf4f095568e8e4af042f3e5a8cb655d9172

commit r15-2457-gebf4f095568e8e4af042f3e5a8cb655d9172
Author: Arsen Arsenović 
Date:   Wed Jul 31 16:53:35 2024 +0200

dir-locals: apply our C settings in C++ also

This also works with Emacs 30 Tree-Sitter C and C++ modes, as they are
submodes.

ChangeLog:

* .dir-locals.el: Change c-mode to a list of C, C++ and ObjC
modes that Emacs currently provides.

Diff:
---
 .dir-locals.el | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/.dir-locals.el b/.dir-locals.el
index fa031cbded99..2c12b3866633 100644
--- a/.dir-locals.el
+++ b/.dir-locals.el
@@ -18,6 +18,10 @@
  (tcl-continued-indent-level . 4)
  (indent-tabs-mode . t)))
  (nil . ((bug-reference-url-format . "https://gcc.gnu.org/PR%s";)))
+ ;; Please keep C and C++ in sync.
  (c-mode . ((c-file-style . "GNU")
(indent-tabs-mode . t)
-   (fill-column . 79
+   (fill-column . 79)))
+ (c++-mode . ((c-file-style . "GNU")
+ (indent-tabs-mode . t)
+ (fill-column . 79

[gcc(refs/users/meissner/heads/work174)] Revert changes

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:cf133c7218a584ef35be364f159d729cc7ff1e5a

commit cf133c7218a584ef35be364f159d729cc7ff1e5a
Author: Michael Meissner 
Date:   Wed Jul 31 14:38:51 2024 -0400

Revert changes

Diff:
---
 gcc/ChangeLog.meissner | 162 +
 gcc/config/rs6000/rs6000-arch.def  |  48 ---
 gcc/config/rs6000/rs6000-c.cc  |  27 +-
 gcc/config/rs6000/rs6000-cpus.def  |   8 +-
 gcc/config/rs6000/rs6000-opts.h|   1 +
 gcc/config/rs6000/rs6000-protos.h  |   5 +-
 gcc/config/rs6000/rs6000.cc| 363 ++---
 gcc/config/rs6000/rs6000.h |  30 --
 gcc/config/rs6000/rs6000.opt   |  19 +-
 gcc/testsuite/gcc.target/powerpc/ppc-target-4.c|  40 +--
 gcc/testsuite/gcc.target/powerpc/pr115688.c|   3 +-
 .../gcc.target/powerpc/vsx-cpu-mismatch.c  |   8 -
 12 files changed, 137 insertions(+), 577 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index d53cd48662b0..df473b6b2313 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,164 +1,4 @@
- Branch work174, patch #26 
-
-Move ARCH_* to rs6000.h.
-
-2024-07-31  Michael Meissner  
-
-gcc/
-
-   * config/rs6000/rs6000-opts.h: Move ARCH_* stuff from here.
-   * config/rs6000/rs6000.h: Move ARCH_* stuff here.
-
- Branch work174, patch #25 
-
-Update tests to work with architecture flags changes.
-
-Two tests used -mvsx to raise the processor level to at least power7.  These
-tests were rewritten to add cpu=power7 support.
-
-2024-07-31  Michael Meissner  
-
-gcc/testsuite/
-
-   * gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add cpu=power7
-   when we need to add VSX support.  Add test for adding cpu=power7 no-vsx
-   to generate only Altivec instructions.
-   * gcc.target/powerpc/pr115688.c: Add cpu=power7 when requesting VSX
-   instructions.
-   * gcc.target/powerpc/vsx-cpu-mismatch.c: New test.
-
- Branch work174, patch #24 
-
-Do not allow -mvsx to boost processor to power7.
-
-This patch restructures the code so that -mvsx for example will not silently
-convert the processor to power7.  The user must now use -mcpu=power7 or higher.
-This means if the user does -mvsx and the default processor does not have VSX
-support, it will be an error.
-
-2024-07-31  Michael Meissner  
-
-gcc/
-
-   * config/rs6000/rs6000.cc (report_architecture_mismatch): New function.
-   Report an error if the user used an option such as -mvsx when the
-   default processor would not allow the option.
-   (rs6000_option_override_internal): Move some ISA checking code into
-   report_architecture_mismatch.
-
- Branch work174, patch #23 
-
-Use architecture flags for defining _ARCH_PWR macros.
-
-For the newer architectures, this patch changes GCC to define the _ARCH_PWR
-macros using the new architecture flags instead of relying on isa options like
--mpower10.
-
-The -mpower8-internal, -mpower10, and -mpower11 options were removed.  The
--mpower11 option was removed completely, since it was just added in GCC 15.  
The
-other two options were marked as WarnRemoved, and the various ISA bits were
-removed.
-
-TARGET_POWER8 and TARGET_POWER10 were re-defined to use the architeture bits
-instead of the ISA bits.
-
-There are other internal isa bits that aren't removed with this patch because
-the built-in function support uses those bits.
-
-2024-07-31  Michael Meissner  
-
-gcc/
-
-   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add support to
-   use architecture flags instead of ISA flags for setting most of the
-   _ARCH_PWR* macros.
-   (rs6000_cpu_cpp_builtins): Update rs6000_target_modify_macros call.
-   * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove
-   OPTION_MASK_POWER8.
-   (ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10.
-   (POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11.
-   (POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10, and
-   OPTION_MASK_POWER11.
-   * config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): Update
-   declaration.
-   (rs6000_target_modify_macros_ptr): Likewise.
-   * config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): Likewise.
-   (rs6000_option_override_internal): Use architecture flags instead of ISA
-   flags.
-   (rs6000_opt_masks): Remove -mpower10 and -mpower11 support.
-   (rs6000_pragma_target_parse): Use architecture flags as well as ISA
-   flags.
-   * config/rs6000/rs6000.h (TARGET_POWER8): New macro.
-   (TARGET_POWER10): Likewise.
-   * config/rs6000/rs6000.opt (-mpower8-internal): Remove ISA flag bits.
-   (-mpower10): Likew

[gcc r15-2458] match: Fix types matching for `(?:) !=/== (?:)` [PR116134]

[Andrew Pinski via Gcc-cvs]

https://gcc.gnu.org/g:c65653f5685a106661596a413744953ea9cdbc60

commit r15-2458-gc65653f5685a106661596a413744953ea9cdbc60
Author: Andrew Pinski 
Date:   Mon Jul 29 11:33:58 2024 -0700

match: Fix types matching for `(?:) !=/== (?:)` [PR116134]

The problem here is that in generic types of comparisons don't need
to be boolean types (or vector boolean types). And fixes that by making
sure the types of the conditions match before doing the optimization.

Bootstrapped and tested on x86_64-linux-gnu with no regressions.

PR middle-end/116134

gcc/ChangeLog:

* match.pd (`(a ? x : y) eq/ne (b ? x : y)`): Check that
a and b types match.
(`(a ? x : y) eq/ne (b ? y : x)`): Likewise.

gcc/testsuite/ChangeLog:

* gcc.dg/torture/pr116134-1.c: New test.

Signed-off-by: Andrew Pinski 

Diff:
---
 gcc/match.pd  | 10 ++
 gcc/testsuite/gcc.dg/torture/pr116134-1.c |  9 +
 2 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/gcc/match.pd b/gcc/match.pd
index 1c8601229e3d..881a827860f0 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -5640,12 +5640,14 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
  (for eqne (eq ne)
   (simplify
(eqne:c (cnd @0 @1 @2) (cnd @3 @1 @2))
-(cnd (bit_xor @0 @3) { constant_boolean_node (eqne == NE_EXPR, type); }
- { constant_boolean_node (eqne != NE_EXPR, type); }))
+(if (types_match (TREE_TYPE (@0), TREE_TYPE (@3)))
+ (cnd (bit_xor @0 @3) { constant_boolean_node (eqne == NE_EXPR, type); }
+  { constant_boolean_node (eqne != NE_EXPR, type); })))
   (simplify
(eqne:c (cnd @0 @1 @2) (cnd @3 @2 @1))
-(cnd (bit_xor @0 @3) { constant_boolean_node (eqne != NE_EXPR, type); }
- { constant_boolean_node (eqne == NE_EXPR, type); }
+(if (types_match (TREE_TYPE (@0), TREE_TYPE (@3)))
+ (cnd (bit_xor @0 @3) { constant_boolean_node (eqne != NE_EXPR, type); }
+  { constant_boolean_node (eqne == NE_EXPR, type); })
 
 /* Canonicalize mask ? { 0, ... } : { -1, ...} to ~mask if the mask
types are compatible.  */
diff --git a/gcc/testsuite/gcc.dg/torture/pr116134-1.c 
b/gcc/testsuite/gcc.dg/torture/pr116134-1.c
new file mode 100644
index ..ab595f996805
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/torture/pr116134-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+
+/* This used to ICE as comparisons on generic can be different types. */
+/* PR middle-end/116134  */
+
+int a;
+int b;
+int d;
+void c() { 1UL <= (d < b) != (1UL & (0 < a | 0L)); }

[gcc(refs/users/meissner/heads/work174)] Add rs6000 architecture masks.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:24c6c233d76aa1af64d71b62a159daa37cef565d

commit 24c6c233d76aa1af64d71b62a159daa37cef565d
Author: Michael Meissner 
Date:   Wed Jul 31 15:42:58 2024 -0400

Add rs6000 architecture masks.

This patch begins the journey to move architecture bits that are not user 
ISA
options from rs6000_isa_flags to a new targt variable rs6000_arch_flags.  
The
intention is to remove switches that are currently isa options, but the user
should not be using this particular option. For example, we want users to 
use
-mcpu=power10 and not just -mpower10.

2024-07-31  Michael Meissner  

gcc/

* config/rs6000/rs6000-arch.def: New file.
* config/rs6000/rs6000.cc (rs6000_print_isa_options): Add an
architecture flags argument, change all callers.
(get_arch_flag): New function.
(rs6000_debug_reg_global): Update rs6000_print_isa_options calls.
(rs6000_option_override_internal): Likewise.
(struct rs6000_arch_mask): New structure.
(rs6000_arch_masks): New table of architecutre masks and names.
(rs6000_function_specific_save): Save architecture flags.
(rs6000_function_specific_restore): Restore architecture flags.
(rs6000_function_specific_print): Update rs6000_print_isa_options 
calls.
(rs6000_print_options_internal): Add architecture flags options.
(rs6000_can_inline_p): Don't allow inling if the callee requires a 
newer
architecture than the caller.
* config/rs6000/rs6000.h: Use rs6000-arch.def to create the 
architecture
masks.
* config/rs6000/rs6000.opt (rs6000_arch_flags): New target variable.
(x_rs6000_arch_flags): New save/restore field for rs6000_arch_flags.

Diff:
---
 gcc/config/rs6000/rs6000-arch.def |  48 +++
 gcc/config/rs6000/rs6000.cc   | 176 ++
 gcc/config/rs6000/rs6000.h|  24 ++
 gcc/config/rs6000/rs6000.opt  |   8 ++
 4 files changed, 239 insertions(+), 17 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-arch.def 
b/gcc/config/rs6000/rs6000-arch.def
new file mode 100644
index ..e5b6e9581331
--- /dev/null
+++ b/gcc/config/rs6000/rs6000-arch.def
@@ -0,0 +1,48 @@
+/* IBM RS/6000 CPU architecture features by processor type.
+   Copyright (C) 1991-2024 Free Software Foundation, Inc.
+   Contributed by Richard Kenner (ken...@vlsi1.ultra.nyu.edu)
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   .  */
+
+/* This file defines architecture features that are based on the -mcpu=
+   option, and not on user options that can be turned on or off.  The intention
+   is for newer processors (power7 and above) to not add new ISA bits for the
+   particular processor, but add these bits.  Otherwise we have to add a bunch
+   of hidden options, just so we have the proper ISA bits.
+
+   For example, in the past we added -mpower8-internal, so that on power8,
+   power9, and power10 would inherit the option, but we had to mark the option
+   generate a warning if the user actually used it.  These options have been
+   moved from the ISA flags to the arch flags.
+
+   To use this, define the macro ARCH_EXPAND which takes 2 arguments.  The
+   first argument is the processor name in upper case, and the second argument
+   is a text name for the processor.
+
+   The function get_arch_flags when passed a processor index number will set up
+   the appropriate architecture flags based on the actual processor
+   enumeration.  */
+
+ARCH_EXPAND(POWER4,  "power4")
+ARCH_EXPAND(POWER5,  "power5")
+ARCH_EXPAND(POWER5X, "power5+")
+ARCH_EXPAND(POWER6,  "power6")
+ARCH_EXPAND(POWER7,  "power7")
+ARCH_EXPAND(POWER8,  "power8")
+ARCH_EXPAND(POWER9,  "power9")
+ARCH_EXPAND(POWER10, "power10")
+ARCH_EXPAND(POWER11, "power11")
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 0bcc6a2d0ab6..a77a079e6c44 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1170,7 +1170,7 @@ enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, 
enum reg_class)
 const int INSN_NOT_AVAILABLE = -1;
 
 static void rs6000_print_isa_options (FILE *, int, const char *,
- HOST_WIDE_INT);
+   

[gcc(refs/users/meissner/heads/work174)] Make clone_targets use architecture flags.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:639ae4d8122237bc56419b2028865a3172f6119c

commit 639ae4d8122237bc56419b2028865a3172f6119c
Author: Michael Meissner 
Date:   Wed Jul 31 15:43:54 2024 -0400

Make clone_targets use architecture flags.

This patch expands on the previous patch and changes the target_clones 
support
to use an architecture mask instead of isa bits.

2024-07-31  Michael Meissner  

gcc/

* config/rs6000/rs6000.cc (struct clone_map): Switch to use 
architecture
flags instead of ISA flags for target_clone support.
(rs6000_clone_map): Likewise.
(rs6000_clone_priority): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 22 +++---
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index a77a079e6c44..0b113b68eff9 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -251,17 +251,17 @@ enum {
 
 /* Map compiler ISA bits into HWCAP names.  */
 struct clone_map {
-  HOST_WIDE_INT isa_mask;  /* rs6000_isa mask */
+  HOST_WIDE_INT arch_mask; /* rs6000_arch_mask.  */
   const char *name;/* name to use in __builtin_cpu_supports.  */
 };
 
 static const struct clone_map rs6000_clone_map[CLONE_MAX] = {
-  { 0, "" },   /* Default options.  */
-  { OPTION_MASK_CMPB,  "arch_2_05" },  /* ISA 2.05 (power6).  */
-  { OPTION_MASK_POPCNTD,   "arch_2_06" },  /* ISA 2.06 (power7).  */
-  { OPTION_MASK_P8_VECTOR, "arch_2_07" },  /* ISA 2.07 (power8).  */
-  { OPTION_MASK_P9_VECTOR, "arch_3_00" },  /* ISA 3.0 (power9).  */
-  { OPTION_MASK_POWER10,   "arch_3_1" },   /* ISA 3.1 (power10).  */
+  { 0, "" },   /* Default options.  */
+  { ARCH_MASK_POWER6,  "arch_2_05" },  /* ISA 2.05 (power6).  */
+  { ARCH_MASK_POWER7,  "arch_2_06" },  /* ISA 2.06 (power7).  */
+  { ARCH_MASK_POWER8,  "arch_2_07" },  /* ISA 2.07 (power8).  */
+  { ARCH_MASK_POWER9,  "arch_3_00" },  /* ISA 3.0 (power9).  */
+  { ARCH_MASK_POWER10, "arch_3_1" },   /* ISA 3.1 (power10).  */
 };
 
 
@@ -25433,7 +25433,7 @@ static int
 rs6000_clone_priority (tree fndecl)
 {
   tree fn_opts = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
-  HOST_WIDE_INT isa_masks;
+  HOST_WIDE_INT arch_masks;
   int ret = CLONE_DEFAULT;
   tree attrs = lookup_attribute ("target", DECL_ATTRIBUTES (fndecl));
   const char *attrs_str = NULL;
@@ -25449,12 +25449,12 @@ rs6000_clone_priority (tree fndecl)
fn_opts = target_option_default_node;
 
   if (!fn_opts || !TREE_TARGET_OPTION (fn_opts))
-   isa_masks = rs6000_isa_flags;
+   arch_masks = rs6000_arch_flags;
   else
-   isa_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_isa_flags;
+   arch_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_arch_flags;
 
   for (ret = CLONE_MAX - 1; ret != 0; ret--)
-   if ((rs6000_clone_map[ret].isa_mask & isa_masks) != 0)
+   if ((rs6000_clone_map[ret].arch_mask & arch_masks) != 0)
  break;
 }

[gcc(refs/users/meissner/heads/work174)] Set .machine from the architecture flags

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:2920fb64d02df44fe4221464730c858d89b1ee9e

commit 2920fb64d02df44fe4221464730c858d89b1ee9e
Author: Michael Meissner 
Date:   Wed Jul 31 15:44:49 2024 -0400

Set .machine from the architecture flags

This patch switches the handling of .machine to use architecture masks if 
they
exist (power4 through power11).  All of the other PowerPCs will continue to 
use
the existing code for setting the .machine option.

2024-07-31  Michael Meissner  

gcc/

* config/rs6000/rs6000 (rs6000_machine_from_flags): Set .machine 
from
the architecture flags.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 17 +
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 0b113b68eff9..bd84b880fdc7 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -5990,27 +5990,28 @@ rs6000_machine_from_flags (void)
 return "ppc64";
 #endif
 
+  HOST_WIDE_INT arch_flags = rs6000_arch_flags;
   HOST_WIDE_INT flags = rs6000_isa_flags;
 
   /* Disable the flags that should never influence the .machine selection.  */
   flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL
 | OPTION_MASK_ALTIVEC);
 
-  if ((flags & (POWER11_MASKS_SERVER & ~ISA_3_1_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER11) != 0)
 return "power11";
-  if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER10) != 0)
 return "power10";
-  if ((flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER9) != 0)
 return "power9";
-  if ((flags & (ISA_2_7_MASKS_SERVER & ~ISA_2_6_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER8) != 0)
 return "power8";
-  if ((flags & (ISA_2_6_MASKS_SERVER & ~ISA_2_5_MASKS_SERVER)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER7) != 0)
 return "power7";
-  if ((flags & (ISA_2_5_MASKS_SERVER & ~ISA_2_4_MASKS)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER6) != 0)
 return "power6";
-  if ((flags & (ISA_2_4_MASKS & ~ISA_2_1_MASKS)) != 0)
+  if ((arch_flags & ARCH_MASK_POWER5) != 0)
 return "power5";
-  if ((flags & ISA_2_1_MASKS) != 0)
+  if ((arch_flags & ARCH_MASK_POWER4) != 0)
 return "power4";
   if ((flags & OPTION_MASK_POWERPC64) != 0)
 return "ppc64";

[gcc(refs/users/meissner/heads/work174)] Use architecture flags for defining _ARCH_PWR macros.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:afb06327c13661d9c172f8af2b8d29ffb6dc769c

commit afb06327c13661d9c172f8af2b8d29ffb6dc769c
Author: Michael Meissner 
Date:   Wed Jul 31 15:47:32 2024 -0400

Use architecture flags for defining _ARCH_PWR macros.

For the newer architectures, this patch changes GCC to define the 
_ARCH_PWR
macros using the new architecture flags instead of relying on isa options 
like
-mpower10.

The -mpower8-internal, -mpower10, and -mpower11 options were removed.  The
-mpower11 option was removed completely, since it was just added in GCC 15. 
 The
other two options were marked as WarnRemoved, and the various ISA bits were
removed.

TARGET_POWER8 and TARGET_POWER10 were re-defined to use the architeture bits
instead of the ISA bits.

There are other internal isa bits that aren't removed with this patch 
because
the built-in function support uses those bits.

2024-07-31  Michael Meissner  

gcc/

* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add 
support to
use architecture flags instead of ISA flags for setting most of the
_ARCH_PWR* macros.
(rs6000_cpu_cpp_builtins): Update rs6000_target_modify_macros call.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove
OPTION_MASK_POWER8.
(ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10.
(POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11.
(POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10, and
OPTION_MASK_POWER11.
* config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): 
Update
declaration.
(rs6000_target_modify_macros_ptr): Likewise.
* config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): 
Likewise.
(rs6000_option_override_internal): Use architecture flags instead 
of ISA
flags.
(rs6000_opt_masks): Remove -mpower10 and -mpower11, which are no 
longer
in the ISA flags.
(rs6000_pragma_target_parse): Use architecture flags as well as ISA
flags.
* config/rs6000/rs6000.h (TARGET_POWER8): New macro.
(TARGET_POWER10): Likewise.
* config/rs6000/rs6000.opt (-mpower8-internal): Remove ISA flag 
bits.
(-mpower10): Likewise.
(-mpower11): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-c.cc | 27 +++
 gcc/config/rs6000/rs6000-cpus.def |  8 +---
 gcc/config/rs6000/rs6000-protos.h |  5 +++--
 gcc/config/rs6000/rs6000.cc   | 19 +++
 gcc/config/rs6000/rs6000.h|  6 ++
 gcc/config/rs6000/rs6000.opt  | 11 ++-
 6 files changed, 38 insertions(+), 38 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 04882c396bfe..c8f33289fa38 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -338,7 +338,8 @@ rs6000_define_or_undefine_macro (bool define_p, const char 
*name)
#pragma GCC target, we need to adjust the macros dynamically.  */
 
 void
-rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
+rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
+HOST_WIDE_INT arch_flags)
 {
   if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
 fprintf (stderr,
@@ -411,7 +412,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
summary of the flags associated with particular cpu
definitions.  */
 
-  /* rs6000_isa_flags based options.  */
+  /* rs6000_isa_flags and rs6000_arch_flags based options.  */
   rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
   if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
@@ -419,23 +420,25 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
   if ((flags & OPTION_MASK_POWERPC64) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
-  if ((flags & OPTION_MASK_MFCRF) != 0)
+  if ((flags & OPTION_MASK_POWERPC64) != 0)
+rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
+  if ((arch_flags & ARCH_MASK_POWER4) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
-  if ((flags & OPTION_MASK_POPCNTB) != 0)
+  if ((arch_flags & ARCH_MASK_POWER5) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
-  if ((flags & OPTION_MASK_FPRND) != 0)
+  if ((arch_flags & ARCH_MASK_POWER5X) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
-  if ((flags & OPTION_MASK_CMPB) != 0)
+  if ((arch_flags & ARCH_MASK_POWER6) != 0)
 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
-  if ((flags & OPTION_MASK_POPCNTD) != 0)
+  if ((arch_flags & ARCH_MASK_POWER7) != 0)
 rs6000_define_or_undefine_macro (defin

[gcc(refs/users/meissner/heads/work174)] Do not allow -mvsx to boost processor to power7.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:e6835cb108e4d85835f3925a5dc2bb0f12a59ccf

commit e6835cb108e4d85835f3925a5dc2bb0f12a59ccf
Author: Michael Meissner 
Date:   Wed Jul 31 15:48:35 2024 -0400

Do not allow -mvsx to boost processor to power7.

This patch restructures the code so that -mvsx for example will not silently
convert the processor to power7.  The user must now use -mcpu=power7 or 
higher.
This means if the user does -mvsx and the default processor does not have 
VSX
support, it will be an error.

2024-07-31  Michael Meissner  

gcc/

* config/rs6000/rs6000.cc (report_architecture_mismatch): New 
function.
Report an error if the user used an option such as -mvsx when the
default processor would not allow the option.
(rs6000_option_override_internal): Move some ISA checking code into
report_architecture_mismatch.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 129 +++-
 1 file changed, 79 insertions(+), 50 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index caab770cd951..c89a6ea8e792 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1172,6 +1172,7 @@ const int INSN_NOT_AVAILABLE = -1;
 static void rs6000_print_isa_options (FILE *, int, const char *,
  HOST_WIDE_INT, HOST_WIDE_INT);
 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
+static void report_architecture_mismatch (void);
 
 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
 static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
@@ -3698,7 +3699,6 @@ rs6000_option_override_internal (bool global_init_p)
   bool ret = true;
 
   HOST_WIDE_INT set_masks;
-  HOST_WIDE_INT ignore_masks;
   int cpu_index = -1;
   int tune_index;
   struct cl_target_option *main_target_opt
@@ -3967,59 +3967,13 @@ rs6000_option_override_internal (bool global_init_p)
 dwarf_offset_size = POINTER_SIZE_UNITS;
 #endif
 
-  /* Handle explicit -mno-{altivec,vsx} and turn off all of
- the options that depend on those flags.  */
-  ignore_masks = rs6000_disable_incompatible_switches ();
-
-  /* For the newer switches (vsx, dfp, etc.) set some of the older options,
- unless the user explicitly used the -mno- to disable the code.  */
-  if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
-rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_P9_MINMAX)
-{
-  if (cpu_index >= 0)
-   {
- if (cpu_index == PROCESSOR_POWER9)
-   {
- /* legacy behavior: allow -mcpu=power9 with certain
-capabilities explicitly disabled.  */
- rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
-   }
- else
-   error ("power9 target option is incompatible with %<%s=%> "
-  "for  less than power9", "-mcpu");
-   }
-  else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
-  != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
-  & rs6000_isa_flags_explicit))
-   /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
-  were explicitly cleared.  */
-   error ("%qs incompatible with explicitly disabled options",
-  "-mpower9-minmax");
-  else
-   rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
-}
-  else if (TARGET_P8_VECTOR || TARGET_POWER8 || TARGET_CRYPTO)
-rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_VSX)
-rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_POPCNTD)
-rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_DFP)
-rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
-  else if (TARGET_CMPB)
-rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_FPRND)
-rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
-  else if (TARGET_POPCNTB)
-rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
-  else if (TARGET_ALTIVEC)
-rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
+  /* Report trying to use things like -mmodulo to imply -mcpu=power9.  */
+  report_architecture_mismatch ();
 
   /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
  target attribute or pragma which automatically enables both options,
  unless the altivec ABI was set.  This is set by default for 64-bit, but
- not for 32-bit.  Don't move this before the above code using ignore_masks,
+ not for 32-bit.  Don't move this before report_architecture_mismatch
  since it can reset the cleared VSX/ALTIVEC flag again.  */
   if (main_target_opt && !main_target_opt->x_rs6000_altivec_abi)
 {
@@ -25410,6 +25364,81 @@ rs6000_disable_incompatible_switches (void)
   return ignore_masks;
 }
 
+/* In the past, we would boost up the ISA if you sele

[gcc(refs/users/meissner/heads/work174)] Update tests to work with architecture flags changes.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:3ebfce704214d77aede5ec371330bbf66e46b2ad

commit 3ebfce704214d77aede5ec371330bbf66e46b2ad
Author: Michael Meissner 
Date:   Wed Jul 31 15:49:52 2024 -0400

Update tests to work with architecture flags changes.

Two tests used -mvsx to raise the processor level to at least power7.  These
tests were rewritten to add cpu=power7 support.

2024-07-31  Michael Meissner  

gcc/testsuite/

* gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add 
cpu=power7
when we need to add VSX support.  Add test for adding cpu=power7 
no-vsx
to generate only Altivec instructions.
* gcc.target/powerpc/pr115688.c: Add cpu=power7 when requesting VSX
instructions.

Diff:
---
 gcc/testsuite/gcc.target/powerpc/ppc-target-4.c | 40 ++---
 gcc/testsuite/gcc.target/powerpc/pr115688.c |  3 +-
 2 files changed, 32 insertions(+), 11 deletions(-)

diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c 
b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
index db9ba500e0e1..42f5aa354d0a 100644
--- a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
@@ -1,8 +1,8 @@
 /* { dg-do compile { target { powerpc*-*-* } } } */
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -ffast-math -mdejagnu-cpu=power5 -mno-altivec 
-mabi=altivec -fno-unroll-loops" } */
-/* { dg-final { scan-assembler-times "vaddfp" 1 } } */
+/* { dg-options "-O3 -ffast-math -mdejagnu-cpu=power5 -mno-altivec 
-mabi=altivec -fno-unroll-loops" } */
+/* { dg-final { scan-assembler-times "vaddfp" 2 } } */
 /* { dg-final { scan-assembler-times "xvaddsp" 1 } } */
 /* { dg-final { scan-assembler-times "fadds" 1 } } */
 
@@ -18,10 +18,6 @@
 #error "__VSX__ should not be defined."
 #endif
 
-#pragma GCC target("altivec,vsx")
-#include 
-#pragma GCC reset_options
-
 #pragma GCC push_options
 #pragma GCC target("altivec,no-vsx")
 
@@ -33,6 +29,7 @@
 #error "__VSX__ should not be defined."
 #endif
 
+/* Altivec build, generate vaddfp.  */
 void
 av_add (vector float *a, vector float *b, vector float *c)
 {
@@ -40,10 +37,11 @@ av_add (vector float *a, vector float *b, vector float *c)
   unsigned long n = SIZE / 4;
 
   for (i = 0; i < n; i++)
-a[i] = vec_add (b[i], c[i]);
+a[i] = b[i] + c[i];
 }
 
-#pragma GCC target("vsx")
+/* cpu=power7 must be used to enable VSX.  */
+#pragma GCC target("cpu=power7,vsx")
 
 #ifndef __ALTIVEC__
 #error "__ALTIVEC__ should be defined."
@@ -53,6 +51,7 @@ av_add (vector float *a, vector float *b, vector float *c)
 #error "__VSX__ should be defined."
 #endif
 
+/* VSX build on power7, generate xsaddsp.  */
 void
 vsx_add (vector float *a, vector float *b, vector float *c)
 {
@@ -60,11 +59,31 @@ vsx_add (vector float *a, vector float *b, vector float *c)
   unsigned long n = SIZE / 4;
 
   for (i = 0; i < n; i++)
-a[i] = vec_add (b[i], c[i]);
+a[i] = b[i] + c[i];
+}
+
+#pragma GCC target("cpu=power7,no-vsx")
+
+#ifndef __ALTIVEC__
+#error "__ALTIVEC__ should be defined."
+#endif
+
+#ifdef __VSX__
+#error "__VSX__ should not be defined."
+#endif
+
+/* Altivec build on power7 with no VSX, generate vaddfp.  */
+void
+av2_add (vector float *a, vector float *b, vector float *c)
+{
+  unsigned long i;
+  unsigned long n = SIZE / 4;
+
+  for (i = 0; i < n; i++)
+a[i] = b[i] + c[i];
 }
 
 #pragma GCC pop_options
-#pragma GCC target("no-vsx,no-altivec")
 
 #ifdef __ALTIVEC__
 #error "__ALTIVEC__ should not be defined."
@@ -74,6 +93,7 @@ vsx_add (vector float *a, vector float *b, vector float *c)
 #error "__VSX__ should not be defined."
 #endif
 
+/* Default power5 build, generate scalar fadds.  */
 void
 norm_add (float *a, float *b, float *c)
 {
diff --git a/gcc/testsuite/gcc.target/powerpc/pr115688.c 
b/gcc/testsuite/gcc.target/powerpc/pr115688.c
index 5222e66ef170..00c7c301436a 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr115688.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr115688.c
@@ -7,7 +7,8 @@
 
 /* Verify there is no ICE under 32 bit env.  */
 
-__attribute__((target("vsx")))
+/* cpu=power7 must be used to enable VSX.  */
+__attribute__((target("cpu=power7,vsx")))
 int test (void)
 {
   return 0;

[gcc(refs/users/meissner/heads/work174)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:0419f3a66728eea2cfb6969cb004ac5a2ace4ea5

commit 0419f3a66728eea2cfb6969cb004ac5a2ace4ea5
Author: Michael Meissner 
Date:   Wed Jul 31 15:51:46 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 149 +
 1 file changed, 149 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index df473b6b2313..8e1fc5989cc9 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,152 @@
+ Branch work174, patch #35 
+
+Update tests to work with architecture flags changes.
+
+Two tests used -mvsx to raise the processor level to at least power7.  These
+tests were rewritten to add cpu=power7 support.
+
+2024-07-31  Michael Meissner  
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add cpu=power7
+   when we need to add VSX support.  Add test for adding cpu=power7 no-vsx
+   to generate only Altivec instructions.
+   * gcc.target/powerpc/pr115688.c: Add cpu=power7 when requesting VSX
+   instructions.
+
+ Branch work174, patch #34 
+
+Do not allow -mvsx to boost processor to power7.
+
+This patch restructures the code so that -mvsx for example will not silently
+convert the processor to power7.  The user must now use -mcpu=power7 or higher.
+This means if the user does -mvsx and the default processor does not have VSX
+support, it will be an error.
+
+2024-07-31  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000.cc (report_architecture_mismatch): New function.
+   Report an error if the user used an option such as -mvsx when the
+   default processor would not allow the option.
+   (rs6000_option_override_internal): Move some ISA checking code into
+   report_architecture_mismatch.
+
+ Branch work174, patch #33 
+
+Use architecture flags for defining _ARCH_PWR macros.
+
+For the newer architectures, this patch changes GCC to define the _ARCH_PWR
+macros using the new architecture flags instead of relying on isa options like
+-mpower10.
+
+The -mpower8-internal, -mpower10, and -mpower11 options were removed.  The
+-mpower11 option was removed completely, since it was just added in GCC 15.  
The
+other two options were marked as WarnRemoved, and the various ISA bits were
+removed.
+
+TARGET_POWER8 and TARGET_POWER10 were re-defined to use the architeture bits
+instead of the ISA bits.
+
+There are other internal isa bits that aren't removed with this patch because
+the built-in function support uses those bits.
+
+2024-07-31  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add support to
+   use architecture flags instead of ISA flags for setting most of the
+   _ARCH_PWR* macros.
+   (rs6000_cpu_cpp_builtins): Update rs6000_target_modify_macros call.
+   * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove
+   OPTION_MASK_POWER8.
+   (ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10.
+   (POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11.
+   (POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10, and
+   OPTION_MASK_POWER11.
+   * config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): Update
+   declaration.
+   (rs6000_target_modify_macros_ptr): Likewise.
+   * config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): Likewise.
+   (rs6000_option_override_internal): Use architecture flags instead of ISA
+   flags.
+   (rs6000_opt_masks): Remove -mpower10 and -mpower11, which are no longer
+   in the ISA flags.
+   (rs6000_pragma_target_parse): Use architecture flags as well as ISA
+   flags.
+   * config/rs6000/rs6000.h (TARGET_POWER8): New macro.
+   (TARGET_POWER10): Likewise.
+   * config/rs6000/rs6000.opt (-mpower8-internal): Remove ISA flag bits.
+   (-mpower10): Likewise.
+   (-mpower11): Likewise.
+
+ Branch work174, patch #32 
+
+Set .machine from the architecture flags
+
+This patch switches the handling of .machine to use architecture masks if they
+exist (power4 through power11).  All of the other PowerPCs will continue to use
+the existing code for setting the .machine option.
+
+2024-07-31  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000 (rs6000_machine_from_flags): Set .machine from
+   the architecture flags.
+
+ Branch work174, patch #31 
+
+Make clone_targets use architecture flags.
+
+This patch expands on the previous patch and changes the target_clones support
+to use an architecture mask instead of isa bits.
+
+2024-07-31  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000.cc (struct clone_map): Switch to use architecture
+   flags instead of ISA flags for target_clone support.
+   (rs6000_clone_map): L

[gcc r15-2459] Fortran: Add newline character to test input.

[Jerry DeLisle via Gcc-cvs]

https://gcc.gnu.org/g:6886f1c164af9381b4dd6c4d5202a3bbca225168

commit r15-2459-g6886f1c164af9381b4dd6c4d5202a3bbca225168
Author: Jerry DeLisle 
Date:   Wed Jul 31 08:58:17 2024 -0700

Fortran: Add newline character to test input.

gcc/testsuite/ChangeLog:

PR libfortran/105361

* gfortran.dg/pr105361.f90: Add newline character to test
input to provide more compliant test.

Diff:
---
 gcc/testsuite/gfortran.dg/pr105361.f90 | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gfortran.dg/pr105361.f90 
b/gcc/testsuite/gfortran.dg/pr105361.f90
index e2d3b07cacaa..62821c2802df 100644
--- a/gcc/testsuite/gfortran.dg/pr105361.f90
+++ b/gcc/testsuite/gfortran.dg/pr105361.f90
@@ -27,7 +27,7 @@ program main
   type(foo) :: a, b
   real :: c, d
   open(10, access="stream") 
-  write(10) "1 2" ! // NEW_LINE('A')
+  write(10) "1 2" // NEW_LINE('A')
   close(10)
   open(10)
   read(10,*) c, d

[gcc r15-2460] libstdc++: Fix src/c++20/format.cc for non-gthreads targets

[Jonathan Wakely via Libstdc++-cvs]

https://gcc.gnu.org/g:e7d88ff8aaa244f3f722fc1dc50e8dc31d5c8fde

commit r15-2460-ge7d88ff8aaa244f3f722fc1dc50e8dc31d5c8fde
Author: Jonathan Wakely 
Date:   Wed Jul 31 20:27:33 2024 +0100

libstdc++: Fix src/c++20/format.cc for non-gthreads targets

libstdc++-v3/ChangeLog:

* src/c++20/format.cc [!_GLIBCXX_HAS_GTHREADS] (mutex): Define
dummy mutex type.
* testsuite/std/time/format_localized.cc: Use loop variable
instead of creating the same locale on every iteration.

Diff:
---
 libstdc++-v3/src/c++20/format.cc| 17 +
 libstdc++-v3/testsuite/std/time/format_localized.cc |  2 +-
 2 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/libstdc++-v3/src/c++20/format.cc b/libstdc++-v3/src/c++20/format.cc
index bcf1dd156a70..1a24fcab7f76 100644
--- a/libstdc++-v3/src/c++20/format.cc
+++ b/libstdc++-v3/src/c++20/format.cc
@@ -49,6 +49,15 @@ namespace __format
 #if defined _GLIBCXX_USE_NL_LANGINFO_L && __CHAR_BIT__ == 8
 namespace
 {
+#ifndef _GLIBCXX_HAS_GTHREADS
+// Dummy mutex
+struct mutex
+{
+  void lock() const { }
+  void unlock() const { }
+};
+#endif
+
 // A non-standard locale::facet that caches the locale's std::text_encoding
 // and an iconv descriptor for converting from that encoding to UTF-8.
 struct __encoding : locale::facet
@@ -59,7 +68,7 @@ struct __encoding : locale::facet
   __encoding(const text_encoding& enc, size_t refs = 0)
   : facet(refs), _M_enc(enc)
   {
-#if defined _GLIBCXX_HAVE_ICONV
+#ifdef _GLIBCXX_HAVE_ICONV
 using enum text_encoding::id;
 switch (_M_enc.mib())
   {
@@ -74,14 +83,14 @@ struct __encoding : locale::facet
 
   ~__encoding()
   {
-#if defined _GLIBCXX_HAVE_ICONV
+#ifdef _GLIBCXX_HAVE_ICONV
 if (_M_cd != (::iconv_t)-1)
   ::iconv_close(_M_cd);
 #endif
   }
 
   text_encoding _M_enc;
-#if defined _GLIBCXX_HAVE_ICONV
+#ifdef _GLIBCXX_HAVE_ICONV
   ::iconv_t _M_cd = (::iconv_t)-1;
   mutable mutex mx;
 #endif
@@ -93,7 +102,7 @@ struct __encoding : locale::facet
 if (input.empty()) [[unlikely]]
   return codecvt_base::noconv;
 
-#if defined _GLIBCXX_HAVE_ICONV
+#ifdef _GLIBCXX_HAVE_ICONV
 if (_M_cd == (::iconv_t)-1)
   return codecvt_base::error;
 
diff --git a/libstdc++-v3/testsuite/std/time/format_localized.cc 
b/libstdc++-v3/testsuite/std/time/format_localized.cc
index 64a1582b945e..393d0d200e45 100644
--- a/libstdc++-v3/testsuite/std/time/format_localized.cc
+++ b/libstdc++-v3/testsuite/std/time/format_localized.cc
@@ -75,7 +75,7 @@ test_en()
 
   for (auto l : {ISO_8859(1,en_US), ISO_8859(15,en_US), "en_US.UTF-8", "C"})
 {
-  std::locale loc(ISO_8859(1,en_US));
+  std::locale loc(l);
   auto s = std::format(loc, "{:L%b %B %a %A}", sys_days(2024y/July/30));
   VERIFY( s == "Jul July Tue Tuesday" );
 }

[gcc r15-2461] libstdc++: Fix unexpected compilation error in neg tests

[Francois Dumont via Libstdc++-cvs]

https://gcc.gnu.org/g:787f2d52d595e316d24f2baadf114bb8a4d8c70f

commit r15-2461-g787f2d52d595e316d24f2baadf114bb8a4d8c70f
Author: François Dumont 
Date:   Wed Jul 31 22:25:20 2024 +0200

libstdc++: Fix unexpected compilation error in neg tests

Fix a compilation error that is not expected by the tests preserving
the expected ones.

The 'test' variable declaration is missing since commit
a9260b7eb688df43a724e25421ba40f35a89fee9 that removed the test global
variable in testsuite files.

libstdc++-v3/ChangeLog:

* testsuite/23_containers/map/operators/1_neg.cc (test01): Add test 
variable
declaration.
* testsuite/23_containers/set/operators/1_neg.cc (test01): Likewise.

Diff:
---
 libstdc++-v3/testsuite/23_containers/map/operators/1_neg.cc | 9 -
 libstdc++-v3/testsuite/23_containers/set/operators/1_neg.cc | 9 -
 2 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/libstdc++-v3/testsuite/23_containers/map/operators/1_neg.cc 
b/libstdc++-v3/testsuite/23_containers/map/operators/1_neg.cc
index 1cb089306906..0eb1eee640b8 100644
--- a/libstdc++-v3/testsuite/23_containers/map/operators/1_neg.cc
+++ b/libstdc++-v3/testsuite/23_containers/map/operators/1_neg.cc
@@ -28,14 +28,13 @@ void test01()
 {
   std::map mapByIndex;
   std::map mapByName;
-  
+
   mapByIndex.insert(std::pair(0, 1));
   mapByIndex.insert(std::pair(6, 5));
-  
+
   std::map::iterator itr(mapByIndex.begin());
 
   // NB: notice, it's not mapByIndex!!
-  test &= itr != mapByName.end(); // { dg-error "no" } 
-  test &= itr == mapByName.end(); // { dg-error "no" } 
+  bool __attribute__((unused)) test = itr != mapByName.end(); // { dg-error 
"no" }
+  test &= itr == mapByName.end(); // { dg-error "no" }
 }
-
diff --git a/libstdc++-v3/testsuite/23_containers/set/operators/1_neg.cc 
b/libstdc++-v3/testsuite/23_containers/set/operators/1_neg.cc
index be90ba51cd4e..28d08f308e17 100644
--- a/libstdc++-v3/testsuite/23_containers/set/operators/1_neg.cc
+++ b/libstdc++-v3/testsuite/23_containers/set/operators/1_neg.cc
@@ -28,11 +28,10 @@ void test01()
 {
   std::set setByIndex;
   std::set setByName;
-  
+
   std::set::iterator itr(setByIndex.begin());
-  
+
   // NB: it's not setByIndex!!
-  test &= itr != setByName.end(); // { dg-error "no" } 
-  test &= itr == setByName.end(); // { dg-error "no" } 
+  bool __attribute__((unused)) test = itr != setByName.end(); // { dg-error 
"no" }
+  test &= itr == setByName.end(); // { dg-error "no" }
 }
-

[gcc r15-2463] diagnostics: SARIF output: tweak ASCII art in comment

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:f829e627f40c95855df1c1b6a2903e360f37715b

commit r15-2463-gf829e627f40c95855df1c1b6a2903e360f37715b
Author: David Malcolm 
Date:   Wed Jul 31 20:38:40 2024 -0400

diagnostics: SARIF output: tweak ASCII art in comment

gcc/ChangeLog:
* diagnostic-format-sarif.cc: Tweak ASCII art in comment
to show edges for both directions in the digraph.

Signed-off-by: David Malcolm 

Diff:
---
 gcc/diagnostic-format-sarif.cc | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/gcc/diagnostic-format-sarif.cc b/gcc/diagnostic-format-sarif.cc
index 84b3e651e462..5900b9ea9b75 100644
--- a/gcc/diagnostic-format-sarif.cc
+++ b/gcc/diagnostic-format-sarif.cc
@@ -290,17 +290,17 @@ private:
. |  have 'char'"|| | with type 'int'")|
. | in include-chain-1-2.h| | in include-chain-1-1.h   |
. +---+ +--+
-   .   |  |
-   .   | included-by  | included-by
-   .   V  V
+   .^ |^ |
+   .   includes | | included-by   includes | | included-by
+   .| V| V
.  ++++
.  |"id": 1 ||"id": 3 |
.  | #include "include-chain-1-2.h" || #include "include-chain-1-1.h" |
.  | in include-chain-1.h   || in include-chain-1.h   |
.  ++++
-   . |  |
-   . | included-by  | included-by
-   . V  V
+   .   ^ |   ^|
+   .  includes | | included-by  includes || included-by
+   .   | V   |V
.  ++
.  |"id": 4 |
.  | The  #include "include-chain-1.h"  |

[gcc r15-2464] diagnostics: SARIF output: eliminate some uses of "line_table" global

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:c990667996ff79cc5be6c898621811eeed4ad0a4

commit r15-2464-gc990667996ff79cc5be6c898621811eeed4ad0a4
Author: David Malcolm 
Date:   Wed Jul 31 20:38:40 2024 -0400

diagnostics: SARIF output: eliminate some uses of "line_table" global

No functional change intended.

gcc/ChangeLog:
* diagnostic-format-sarif.cc (sarif_builder::sarif_builder): Assert
that m_line_maps is nonnull.
(diagnostic_output_format_init_sarif_stderr): Add "line_maps"
param and pass to format ctor.
(diagnostic_output_format_init_sarif_file): Likewise.
(diagnostic_output_format_init_sarif_stream): Likewise.
* diagnostic.cc (diagnostic_output_format_init): Pass "line_table"
as line_maps param to the above.
* diagnostic.h (diagnostic_output_format_init_sarif_stderr): Add
"line_maps" param.
(diagnostic_output_format_init_sarif_file): Likewise.
(diagnostic_output_format_init_sarif_stream): Likewise.

Signed-off-by: David Malcolm 

Diff:
---
 gcc/diagnostic-format-sarif.cc | 14 +++---
 gcc/diagnostic.cc  |  2 ++
 gcc/diagnostic.h   |  3 +++
 3 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/gcc/diagnostic-format-sarif.cc b/gcc/diagnostic-format-sarif.cc
index 5900b9ea9b75..2232883281bf 100644
--- a/gcc/diagnostic-format-sarif.cc
+++ b/gcc/diagnostic-format-sarif.cc
@@ -1302,6 +1302,8 @@ sarif_builder::sarif_builder (diagnostic_context &context,
   m_tabstop (context.m_tabstop),
   m_formatted (formatted)
 {
+  gcc_assert (m_line_maps);
+
   /* Mark MAIN_INPUT_FILENAME_ as the artifact that the tool was
  instructed to scan.
  Only quote the contents if it gets referenced by physical locations,
@@ -2988,13 +2990,15 @@ diagnostic_output_format_init_sarif (diagnostic_context 
&context)
 
 void
 diagnostic_output_format_init_sarif_stderr (diagnostic_context &context,
+   const line_maps *line_maps,
const char *main_input_filename_,
bool formatted)
 {
+  gcc_assert (line_maps);
   diagnostic_output_format_init_sarif (context);
   context.set_output_format
 (new sarif_stream_output_format (context,
-line_table,
+line_maps,
 main_input_filename_,
 formatted,
 stderr));
@@ -3005,14 +3009,16 @@ diagnostic_output_format_init_sarif_stderr 
(diagnostic_context &context,
 
 void
 diagnostic_output_format_init_sarif_file (diagnostic_context &context,
+ const line_maps *line_maps,
  const char *main_input_filename_,
  bool formatted,
  const char *base_file_name)
 {
+  gcc_assert (line_maps);
   diagnostic_output_format_init_sarif (context);
   context.set_output_format
 (new sarif_file_output_format (context,
-  line_table,
+  line_maps,
   main_input_filename_,
   formatted,
   base_file_name));
@@ -3022,14 +3028,16 @@ diagnostic_output_format_init_sarif_file 
(diagnostic_context &context,
 
 void
 diagnostic_output_format_init_sarif_stream (diagnostic_context &context,
+   const line_maps *line_maps,
const char *main_input_filename_,
bool formatted,
FILE *stream)
 {
+  gcc_assert (line_maps);
   diagnostic_output_format_init_sarif (context);
   context.set_output_format
 (new sarif_stream_output_format (context,
-line_table,
+line_maps,
 main_input_filename_,
 formatted,
 stream));
diff --git a/gcc/diagnostic.cc b/gcc/diagnostic.cc
index 46cddfe94d1d..71d2f44e40c8 100644
--- a/gcc/diagnostic.cc
+++ b/gcc/diagnostic.cc
@@ -1857,12 +1857,14 @@ diagnostic_output_format_init (diagnostic_context 
&context,
 
 case DIAGNOSTICS_OUTPUT_FORMAT_SARIF_STDERR:
   diagnostic_output_format_init_sarif_stderr (context,
+ line_table,
  main_input_filename_,
  json_formatting);
   break;
 
 case DIAGNOSTICS_OUTPUT_FORMAT_SARIF_FILE:
   diagnostic_output_format_init_sarif_file (context,
+  

[gcc r15-2465] diagnostics: SARIF output: capture unlabelled secondary locations

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:a874b8301d9aa0421522d5aa11736f1510edb13a

commit r15-2465-ga874b8301d9aa0421522d5aa11736f1510edb13a
Author: David Malcolm 
Date:   Wed Jul 31 20:38:41 2024 -0400

diagnostics: SARIF output: capture unlabelled secondary locations

This patch extends
* the work done in r15-2291-gd7a688fc960f78 to capture labels
  on location ranges in rich_locations in SARIF form as
  "annotations" (§3.28.6)
* the work done in r15-2354-g4d1f71d49e396c to support
  related locations (§3.27.22 and §3.34)

so that all location ranges in a rich_location now get captured in
the SARIF output:
- those with a label are handled as before as "annotations" (§3.28.6),
  per r15-2291-gd7a688fc960f78
- those without a label now get captured, in the result's
  "relatedLocations" (§3.27.22)

For example, given:

  int missing_semicolon (void)
  {
return 42
  }

for which the textual output looks like this:

  PATH/missing-semicolon.c: In function 'missing_semicolon':
  PATH/missing-semicolon.c:9:12: error: expected ';' before '}' token
  9 |   return 42
|^
|;
 10 | }
| ~

with this patch the SARIF output now has this for the result's location:

   "relationships": [{"target": 0,
  "kinds": ["relevant"]}]}],

where the result gains a related location :

  "relatedLocations": [{"physicalLocation": {"artifactLocation": { 
[...snip...] },
 "region": {"startLine": 10,
"startColumn": 1,
"endColumn": 2},
 "contextRegion": {"startLine": 
10,
   "snippet": 
{"text": "}\n"}}},
"id": 0}]}]}]}

i.e. that the error also has the secondary location at the trailing
close brace which has the relationship "relevant" to the primary
location (at the suggested insertion point).

The patch also adds test coverage for the SARIF encoding of the fix-it hint.

gcc/ChangeLog:
* diagnostic-format-sarif.cc

(sarif_location_manager::worklist_item::unlabelled_secondary_location):
New enum value.
(sarif_location_manager::m_unlabelled_secondary_locations): New
field.
(sarif_location_manager::process_worklist_item): Handle unlabelled
secondary locations.
(sarif_builder::make_location_object): Generalize code to handle
ranges within a rich_location so as well as using annotations for
those with labels, we now add related locations for those without
labels.

gcc/testsuite/ChangeLog:
* gcc.dg/sarif-output/missing-semicolon.c: New test.
* gcc.dg/sarif-output/sarif.py (get_location_physical_region): New.
(get_location_snippet_text): New.
* gcc.dg/sarif-output/test-missing-semicolon.py: New test.

Signed-off-by: David Malcolm 

Diff:
---
 gcc/diagnostic-format-sarif.cc | 54 +--
 .../gcc.dg/sarif-output/missing-semicolon.c| 22 ++
 gcc/testsuite/gcc.dg/sarif-output/sarif.py |  3 +
 .../gcc.dg/sarif-output/test-missing-semicolon.py  | 79 ++
 4 files changed, 152 insertions(+), 6 deletions(-)

diff --git a/gcc/diagnostic-format-sarif.cc b/gcc/diagnostic-format-sarif.cc
index 2232883281bf..7c2e96f4f746 100644
--- a/gcc/diagnostic-format-sarif.cc
+++ b/gcc/diagnostic-format-sarif.cc
@@ -323,7 +323,11 @@ public:
 {
  /* Process a #include relationship where m_location_obj
was #included-d at m_where.  */
- included_from
+ included_from,
+
+ /* Process a location_t that was added as a secondary location
+   to a rich_location without a label.  */
+ unlabelled_secondary_location
 };
 
 worklist_item (sarif_location &location_obj,
@@ -369,6 +373,7 @@ private:
 
   std::list m_worklist;
   std::map m_included_from_locations;
+  std::map m_unlabelled_secondary_locations;
 };
 
 /* Subclass of sarif_object for SARIF "result" objects
@@ -559,6 +564,7 @@ public:
- diagnostic groups (see limitations below)
- logical locations (e.g. cfun)
- labelled ranges (as annotations)
+   - secondary ranges without labels (as related locations)
 
Known limitations:
- GCC supports one-deep nesting of diagnostics (via auto_diagnostic_group),
@@ -566,9 +572,6 @@ public:
  diagnostics (e.g. we ignore fix-it hints on them)
- although we capture command-line arguments (section 3.20.2), we don't
  yet capture response files.
-   - doesn't capture secondary locations within a rich_loca

[gcc r15-2466] testsuite: drop unused import within sarif.py

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:5cb7adeaf5420c7a4e07f70ac09ee087b2e60654

commit r15-2466-g5cb7adeaf5420c7a4e07f70ac09ee087b2e60654
Author: David Malcolm 
Date:   Wed Jul 31 20:38:41 2024 -0400

testsuite: drop unused import within sarif.py

No functional change intended.

gcc/testsuite/ChangeLog:
* gcc.dg/sarif-output/sarif.py: Drop unused import of gzip.

Signed-off-by: David Malcolm 

Diff:
---
 gcc/testsuite/gcc.dg/sarif-output/sarif.py | 1 -
 1 file changed, 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/sarif-output/sarif.py 
b/gcc/testsuite/gcc.dg/sarif-output/sarif.py
index a34678791aca..7daf35b58190 100644
--- a/gcc/testsuite/gcc.dg/sarif-output/sarif.py
+++ b/gcc/testsuite/gcc.dg/sarif-output/sarif.py
@@ -1,4 +1,3 @@
-import gzip
 import json
 import os

[gcc r15-2467] diagnostics: handle logical locations with NULL name

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:55982d1682921fdaf595c28f84f63d600558d150

commit r15-2467-g55982d1682921fdaf595c28f84f63d600558d150
Author: David Malcolm 
Date:   Wed Jul 31 20:38:41 2024 -0400

diagnostics: handle logical locations with NULL name

gcc/ChangeLog:
* diagnostic-path.cc
(thread_event_printer::print_swimlane_for_event_range): Gracefully
handle logical_location::get_name_for_path_output returning null.

Signed-off-by: David Malcolm 

Diff:
---
 gcc/diagnostic-path.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/diagnostic-path.cc b/gcc/diagnostic-path.cc
index b497d89d0594..37751843f9ae 100644
--- a/gcc/diagnostic-path.cc
+++ b/gcc/diagnostic-path.cc
@@ -860,7 +860,8 @@ public:
 if (const logical_location *logical_loc = range->m_logical_loc)
   {
label_text name (logical_loc->get_name_for_path_output ());
-   pp_printf (pp, "%qs: ", name.get ());
+   if (name.get ())
+ pp_printf (pp, "%qs: ", name.get ());
   }
 if (range->m_start_idx == range->m_end_idx)
   pp_printf (pp, "event %i",

[gcc r15-2468] testsuite: split out parts of jit.dg/jit.exp into a new lib/valgrind.exp

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:64fbaf36a3834c394422cdf86985c7cc45179925

commit r15-2468-g64fbaf36a3834c394422cdf86985c7cc45179925
Author: David Malcolm 
Date:   Wed Jul 31 20:38:41 2024 -0400

testsuite: split out parts of jit.dg/jit.exp into a new lib/valgrind.exp

I want to reuse some of the support for valgrind in jit.exp
in my upcoming testsuite for https://gcc.gnu.org/wiki/libdiagnostics
so this patch splits that out into a valgrind.exp.

No functional change intended.

gcc/testsuite/ChangeLog:
* jit.dg/jit.exp: Add load_lib valgrind.exp.
(proc report_leak): Move to valgrind.exp, and add argument
leak_report_function rather than hardcoding xfail.
(parse_valgrind_logfile): Likewise.
(fixed_host_execute): Pass xfail to parse_valgrind_logfile.
* lib/valgrind.exp: New file, based on the above.

Signed-off-by: David Malcolm 

Diff:
---
 gcc/testsuite/jit.dg/jit.exp   | 47 +++---
 gcc/testsuite/lib/valgrind.exp | 58 ++
 2 files changed, 62 insertions(+), 43 deletions(-)

diff --git a/gcc/testsuite/jit.dg/jit.exp b/gcc/testsuite/jit.dg/jit.exp
index 893ff5f6dd05..57b133b6d8c6 100644
--- a/gcc/testsuite/jit.dg/jit.exp
+++ b/gcc/testsuite/jit.dg/jit.exp
@@ -38,6 +38,7 @@ load_lib gcc.exp
 load_lib g++.exp
 load_lib dejagnu.exp
 load_lib target-supports-dg.exp
+load_lib valgrind.exp
 
 # Skip these tests for targets that don't support -lgccjit
 if { ![check_effective_target_lgccjit] } {
@@ -47,48 +48,6 @@ if { ![check_effective_target_lgccjit] } {
 # The default do-what keyword.
 set dg-do-what-default compile
 
-# Look for lines of the form:
-#   definitely lost: 11,316 bytes in 235 blocks
-#   indirectly lost: 352 bytes in 4 blocks
-# Ideally these would report zero bytes lost (which is a PASS);
-# for now, report non-zero leaks as XFAILs.
-proc report_leak {kind name logfile line} {
-set match [regexp "$kind lost: .*" $line result]
-if $match {
-   verbose "Saw \"$result\" within \"$line\"" 4
-   # Extract bytes and blocks.
-   # These can contain commas as well as numerals,
-   # but we only care about whether we have zero.
-   regexp "$kind lost: (.+) bytes in (.+) blocks" \
-   $result -> bytes blocks
-   verbose "bytes: '$bytes'" 4
-   verbose "blocks: '$blocks'" 4
-   if { $bytes == 0 } {
-   pass "$name: $logfile: $result"
-   } else {
-   xfail "$name: $logfile: $result"
-   }
-}
-}
-
-proc parse_valgrind_logfile {name logfile} {
-verbose "parse_valgrind_logfile: $logfile" 2
-if [catch {set f [open $logfile]}] {
-   fail "$name: unable to read $logfile"
-   return
-}
-
-while { [gets $f line] >= 0 } {
-   # Strip off the PID prefix e.g. ==7675==
-   set line [regsub "==\[0-9\]*== " $line ""]
-   verbose $line 2
-
-   report_leak "definitely" $name $logfile $line
-   report_leak "indirectly" $name $logfile $line
-}
-close $f
-}
-
 # Given WRES, the result from "wait", issue a PASS
 # if the spawnee exited cleanly, or a FAIL for various kinds of
 # unexpected exits.
@@ -327,7 +286,9 @@ proc fixed_host_execute {args} {
  
 if $run_under_valgrind {
upvar 2 name name
-   parse_valgrind_logfile $name $valgrind_logfile
+   # Use xfail to report leaks, as libgccjit isn't yet clean of
+   # memory leaks (PR jit/63854)
+   parse_valgrind_logfile $name $valgrind_logfile xfail
 }
 
 # force a close of the executable to be safe.
diff --git a/gcc/testsuite/lib/valgrind.exp b/gcc/testsuite/lib/valgrind.exp
new file mode 100644
index ..7d4f7ce51da1
--- /dev/null
+++ b/gcc/testsuite/lib/valgrind.exp
@@ -0,0 +1,58 @@
+# Copyright (C) 2014-2024 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# .
+
+# Look for lines of the form:
+#   definitely lost: 11,316 bytes in 235 blocks
+#   indirectly lost: 352 bytes in 4 blocks
+# Report zero bytes lost as a a PASS.
+# Use LEAK_REPORT_FUNCTION to report non-zero bytes lost (either fail or xfail)
+
+proc report_leak {kind name logfile line leak_report_function} {
+set match [regexp "$kind lost: .*" $line result]
+if $match {
+   verbose "Saw \"$result\" within \"$line\"" 4
+   # Extract b

[gcc r15-2469] Fix ICE when using -gcodeview with empty struct

[Mark Harmstone via Gcc-cvs]

https://gcc.gnu.org/g:4c88b4e635f6025a897c5d059628e63ec5ba948f

commit r15-2469-g4c88b4e635f6025a897c5d059628e63ec5ba948f
Author: Mark Harmstone 
Date:   Fri Jul 26 20:46:33 2024 +0100

Fix ICE when using -gcodeview with empty struct

Empty structs result in empty LF_FIELDLIST types, which are valid, but
we weren't accounting for this and assuming they had to contain
subtypes.

gcc/
* dwarf2codeview.cc (get_type_num_struct): Fix NULL pointer 
dereference.

Diff:
---
 gcc/dwarf2codeview.cc | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/gcc/dwarf2codeview.cc b/gcc/dwarf2codeview.cc
index b16c6960f63e..470cbae71103 100644
--- a/gcc/dwarf2codeview.cc
+++ b/gcc/dwarf2codeview.cc
@@ -2858,8 +2858,11 @@ get_type_num_struct (dw_die_ref type, bool in_struct, 
bool *is_fwd_ref)
   ct2 = ct->next;
   ct->next = NULL;
 
-  if (ct->lf_fieldlist.last_subtype->kind == LF_INDEX)
-   ct->lf_fieldlist.last_subtype->lf_index.type_num = last_type;
+  if (ct->lf_fieldlist.last_subtype
+ && ct->lf_fieldlist.last_subtype->kind == LF_INDEX)
+   {
+ ct->lf_fieldlist.last_subtype->lf_index.type_num = last_type;
+   }
 
   add_custom_type (ct);
   last_type = ct->num;

[gcc r15-2470] RISC-V: NFC: Do not use zicond for pr105314 testcases

[xiao via Gcc-cvs]

https://gcc.gnu.org/g:edad1b05010fedc7224515570592b2bd2153b21a

commit r15-2470-gedad1b05010fedc7224515570592b2bd2153b21a
Author: Xiao Zeng 
Date:   Thu Jul 25 09:50:03 2024 +0800

RISC-V: NFC: Do not use zicond for pr105314 testcases

gcc/testsuite/ChangeLog:

* gcc.target/riscv/pr105314-rtl.c: Skip zicond.
* gcc.target/riscv/pr105314-rtl32.c: Ditto.
* gcc.target/riscv/pr105314.c: Ditto.

Signed-off-by: Xiao Zeng 

Diff:
---
 gcc/testsuite/gcc.target/riscv/pr105314-rtl.c   | 2 +-
 gcc/testsuite/gcc.target/riscv/pr105314-rtl32.c | 2 +-
 gcc/testsuite/gcc.target/riscv/pr105314.c   | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/pr105314-rtl.c 
b/gcc/testsuite/gcc.target/riscv/pr105314-rtl.c
index 693291f4dbd2..570918f9d9ab 100644
--- a/gcc/testsuite/gcc.target/riscv/pr105314-rtl.c
+++ b/gcc/testsuite/gcc.target/riscv/pr105314-rtl.c
@@ -1,7 +1,7 @@
 /* PR rtl-optimization/105314 */
 /* { dg-do compile } */
 /* { dg-require-effective-target rv64 } */
-/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" "-flto" } } */
+/* { dg-skip-if "" { *-*-* } { "-march=*zicond*" "-O0" "-Og" "-Os" "-Oz" 
"-flto" } } */
 /* { dg-options "-fdump-rtl-ce1" } */
 
 long __RTL (startwith ("ce1"))
diff --git a/gcc/testsuite/gcc.target/riscv/pr105314-rtl32.c 
b/gcc/testsuite/gcc.target/riscv/pr105314-rtl32.c
index 9f9600f7679f..018b6c43095f 100644
--- a/gcc/testsuite/gcc.target/riscv/pr105314-rtl32.c
+++ b/gcc/testsuite/gcc.target/riscv/pr105314-rtl32.c
@@ -1,7 +1,7 @@
 /* PR rtl-optimization/105314 */
 /* { dg-do compile } */
 /* { dg-require-effective-target rv32 } */
-/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" "-flto" } } */
+/* { dg-skip-if "" { *-*-* } { "-march=*zicond*" "-O0" "-Og" "-Os" "-Oz" 
"-flto" } } */
 /* { dg-options "-fdump-rtl-ce1" } */
 
 long __RTL (startwith ("ce1"))
diff --git a/gcc/testsuite/gcc.target/riscv/pr105314.c 
b/gcc/testsuite/gcc.target/riscv/pr105314.c
index 1a7ea671791c..75f6ecda2bbe 100644
--- a/gcc/testsuite/gcc.target/riscv/pr105314.c
+++ b/gcc/testsuite/gcc.target/riscv/pr105314.c
@@ -1,6 +1,6 @@
 /* PR rtl-optimization/105314 */
 /* { dg-do compile } */
-/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-skip-if "" { *-*-* } { "-march=*zicond*" "-O0" "-Og" "-Os" "-Oz" } } */
 /* { dg-options "-fdump-rtl-ce1" } */
 
 long

[gcc r15-2471] i386: Remove ndd support for *add_4 [PR113744]

[Kong Lingling via Gcc-cvs]

https://gcc.gnu.org/g:25dba615e3c191f0a7264538b6d260e91ca2624a

commit r15-2471-g25dba615e3c191f0a7264538b6d260e91ca2624a
Author: Lingling Kong 
Date:   Thu Aug 1 11:05:41 2024 +0800

i386: Remove ndd support for *add_4 [PR113744]

*add_4 and *adddi_4 are for shorter opcode from cmp to
inc/dec or add $128. But NDD code is longer than the cmp code,
so there is no need to support ndd.

gcc/ChangeLog:

PR target/113744
* config/i386/i386.md (*add_4): Remove ndd support.
(*adddi_4): Ditto.

Co-Authored-By: Hu, Lin1 

Diff:
---
 gcc/config/i386/i386.md | 40 +++-
 1 file changed, 15 insertions(+), 25 deletions(-)

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index fb10fdc9f96d..3c293c146569 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -7146,35 +7146,31 @@
 (define_insn "*adddi_4"
   [(set (reg FLAGS_REG)
(compare
- (match_operand:DI 1 "nonimmediate_operand" "0,rm")
- (match_operand:DI 2 "x86_64_immediate_operand" "e,e")))
-   (clobber (match_scratch:DI 0 "=r,r"))]
+ (match_operand:DI 1 "nonimmediate_operand" "0")
+ (match_operand:DI 2 "x86_64_immediate_operand" "e")))
+   (clobber (match_scratch:DI 0 "=r"))]
   "TARGET_64BIT
&& ix86_match_ccmode (insn, CCGCmode)"
 {
-  bool use_ndd = get_attr_isa (insn) == ISA_APX_NDD;
   switch (get_attr_type (insn))
 {
 case TYPE_INCDEC:
   if (operands[2] == constm1_rtx)
-return use_ndd ? "inc{q}\t{%1, %0|%0, %1}" : "inc{q}\t%0";
+   return "inc{q}\t%0";
   else
 {
  gcc_assert (operands[2] == const1_rtx);
- return use_ndd ? "dec{q}\t{%1, %0|%0, %1}" : "dec{q}\t%0";
+ return "dec{q}\t%0";
}
 
 default:
   if (x86_maybe_negate_const_int (&operands[2], DImode))
-   return use_ndd ? "add{q}\t{%2, %1, %0|%0, %1, %2}"
-  : "add{q}\t{%2, %0|%0, %2}";
+   return "add{q}\t{%2, %0|%0, %2}";
 
-  return use_ndd ? "sub{q}\t{%2, %1, %0|%0, %1, %2}"
-: "sub{q}\t{%2, %0|%0, %2}";
+  return "sub{q}\t{%2, %0|%0, %2}";
 }
 }
-  [(set_attr "isa" "*,apx_ndd")
-   (set (attr "type")
+  [(set (attr "type")
  (if_then_else (match_operand:DI 2 "incdec_operand")
(const_string "incdec")
(const_string "alu")))
@@ -7195,36 +7191,30 @@
 (define_insn "*add_4"
   [(set (reg FLAGS_REG)
(compare
- (match_operand:SWI124 1 "nonimmediate_operand" "0,rm")
+ (match_operand:SWI124 1 "nonimmediate_operand" "0")
  (match_operand:SWI124 2 "const_int_operand")))
-   (clobber (match_scratch:SWI124 0 "=,r"))]
+   (clobber (match_scratch:SWI124 0 "="))]
   "ix86_match_ccmode (insn, CCGCmode)"
 {
-  bool use_ndd = get_attr_isa (insn) == ISA_APX_NDD;
   switch (get_attr_type (insn))
 {
 case TYPE_INCDEC:
   if (operands[2] == constm1_rtx)
-return use_ndd ? "inc{}\t{%1, %0|%0, %1}"
-  : "inc{}\t%0";
+return "inc{}\t%0";
   else
 {
  gcc_assert (operands[2] == const1_rtx);
- return use_ndd ? "dec{}\t{%1, %0|%0, %1}"
-: "dec{}\t%0";
+ return "dec{}\t%0";
}
 
 default:
   if (x86_maybe_negate_const_int (&operands[2], mode))
-   return use_ndd ? "add{}\t{%2, %1, %0|%0, %1, %2}"
-  : "add{}\t{%2, %0|%0, %2}";
+   return "add{}\t{%2, %0|%0, %2}";
 
-  return use_ndd ? "sub{}\t{%2, %1, %0|%0, %1, %2}"
-: "sub{}\t{%2, %0|%0, %2}";
+  return "sub{}\t{%2, %0|%0, %2}";
 }
 }
-  [(set_attr "isa" "*,apx_ndd")
-   (set (attr "type")
+  [(set (attr "type")
  (if_then_else (match_operand: 2 "incdec_operand")
(const_string "incdec")
(const_string "alu")))

[gcc(refs/users/meissner/heads/work174)] Change TARGET_POPCNTB to TARGET_POWER5

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:1f24b2b913ab7c1d330c9815432a457e8082f136

commit 1f24b2b913ab7c1d330c9815432a457e8082f136
Author: Michael Meissner 
Date:   Wed Jul 31 23:03:19 2024 -0400

Change TARGET_POPCNTB to TARGET_POWER5

As part of the architecture flags patches, this patch changes the use of
TARGET_POPCNTB to TARGET_POWER5.  The POPCNTB instruction was added in ISA 
2.02
(power5).

2024-07-31  Michael Meissner  

* config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
TARGET_POWER5 instead of TARGET_POPCNTB.
* config/rs6000/rs6000.h (TARGET_POWER5): New macro.
(TARGET_EXTRA_BUILTINS): Use TARGET_POWER5 instead of 
TARGET_POPCNTB.
(TARGET_FRE): Likewise.
(TARGET_FRSQRTES): Likewise.
* config/rs6000/rs6000.md (enabled attribute): Likewise.
(popcount): Use TARGET_POWER5 instead of TARGET_POPCNTB.  Drop
test for TARGET_POPCNTD (i.e power7), since TARGET_POPCNTB will 
always
be set if TARGET_POPCNTD is set.
(popcntb2): Use TARGET_POWER5 instead of TARGET_POPCNTB.
(parity2): Likewise.
(parity2_cmpb): Remove TARGET_POPCNTB test, since it will 
always
be true when TARGET_CMPB (i.e. power6) is set.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  2 +-
 gcc/config/rs6000/rs6000.h  | 14 --
 gcc/config/rs6000/rs6000.md | 10 +-
 3 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 099cbc822459..ba2eba15378e 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -155,7 +155,7 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_ALWAYS:
   return true;
 case ENB_P5:
-  return TARGET_POPCNTB;
+  return TARGET_POWER5;
 case ENB_P6:
   return TARGET_CMPB;
 case ENB_P6_64:
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index f011fa2523c0..5e77962f70b2 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -520,9 +520,11 @@ extern int rs6000_vector_align[];
 #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN
 #endif
 
-/* In the past we represented power8, power10 as an ISA bit and used internal
-   switches the user was not supposed to use for -mpower8-internal and
-   -mpower10.  Now we use architecture flags for this.  */
+/* In the past we represented the various power cpus (power4, power5, power6,
+   etc.) via ISA bits that highlighted a new instruction or we used an extra
+   option to represent the hardware (i.e. -mpower8-internal or -mpower10).  Now
+   we use architecture flags for this.  */
+#define TARGET_POWER5  ((rs6000_arch_flags & ARCH_MASK_POWER5)  != 0)
 #define TARGET_POWER8  ((rs6000_arch_flags & ARCH_MASK_POWER8)  != 0)
 #define TARGET_POWER10 ((rs6000_arch_flags & ARCH_MASK_POWER10) != 0)
 
@@ -533,7 +535,7 @@ extern int rs6000_vector_align[];
 
 #define TARGET_EXTRA_BUILTINS  (TARGET_POWERPC64\
 || TARGET_PPC_GPOPT /* 970/power4 */\
-|| TARGET_POPCNTB   /* ISA 2.02 */  \
+|| TARGET_POWER5/* ISA 2.02 */  \
 || TARGET_CMPB  /* ISA 2.05 */  \
 || TARGET_POPCNTD   /* ISA 2.06 */  \
 || TARGET_ALTIVEC   \
@@ -549,9 +551,9 @@ extern int rs6000_vector_align[];
 #define TARGET_FRES(TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT)
 
 #define TARGET_FRE (TARGET_HARD_FLOAT \
-&& (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
+&& (TARGET_POWER5 || VECTOR_UNIT_VSX_P (DFmode)))
 
-#define TARGET_FRSQRTES(TARGET_HARD_FLOAT && TARGET_POPCNTB \
+#define TARGET_FRSQRTES(TARGET_HARD_FLOAT && TARGET_POWER5 \
 && TARGET_PPC_GFXOPT)
 
 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT \
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index cfb22a3cb7da..4fe6e34412aa 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -365,7 +365,7 @@
  (const_int 1)
 
  (and (eq_attr "isa" "p5")
- (match_test "TARGET_POPCNTB"))
+ (match_test "TARGET_POWER5"))
  (const_int 1)
 
  (and (eq_attr "isa" "p6")
@@ -2475,7 +2475,7 @@
 (define_expand "popcount2"
   [(set (match_operand:GPR 0 "gpc_reg_operand")
(popcount:GPR (match_operand:GPR 1 "gpc_reg_operand")))]
-  "TARGET_POPCNTB || TARGET_POPCNTD"
+  "TARGET_POWER5"
 {
   rs6000_emit_popcount (operands[0], operands[1]);
   DONE;
@@ -2485,7 +2485,7 @@
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" 

[gcc(refs/users/meissner/heads/work174)] Change TARGET_FPRND to TARGET_POWER5X

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:e20f69cd4e9c83e429e7c252f2d67df520e6d455

commit e20f69cd4e9c83e429e7c252f2d67df520e6d455
Author: Michael Meissner 
Date:   Wed Jul 31 23:16:51 2024 -0400

Change TARGET_FPRND to TARGET_POWER5X

As part of the architecture flags patches, this patch changes the use of
TARGET_FPRND to TARGET_POWER5X.  The FPRND instruction was added in power5+.

2024-07-31  Michael Meissner  

* config/rs6000/rs6000.cc (report_architecture_mismatch): Use
TARGET_POWER5X instead of TARGET_FPRND.
* config/rs6000/rs6000.h (TARGET_POWER5X): New macro.
* config/rs6000/rs6000.md (fmod3): Use TARGET_POWER5X instead 
of
TARGET_FPRND.
(remainder3): Likewise.
(fctiwuz_): Likewise.
(btrunc2): Likewise.
(ceil2): Likewise.
(floor2): Likewise.
(round): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000.cc |  2 +-
 gcc/config/rs6000/rs6000.h  |  1 +
 gcc/config/rs6000/rs6000.md | 14 +++---
 3 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index c89a6ea8e792..7d50fd97ad87 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -25431,7 +25431,7 @@ report_architecture_mismatch (void)
 rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
   else if (TARGET_CMPB)
 rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_FPRND)
+  else if (TARGET_POWER5X)
 rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
   else if (TARGET_POPCNTB)
 rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 5e77962f70b2..727167f4288f 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -525,6 +525,7 @@ extern int rs6000_vector_align[];
option to represent the hardware (i.e. -mpower8-internal or -mpower10).  Now
we use architecture flags for this.  */
 #define TARGET_POWER5  ((rs6000_arch_flags & ARCH_MASK_POWER5)  != 0)
+#define TARGET_POWER5X ((rs6000_arch_flags & ARCH_MASK_POWER5X) != 0)
 #define TARGET_POWER8  ((rs6000_arch_flags & ARCH_MASK_POWER8)  != 0)
 #define TARGET_POWER10 ((rs6000_arch_flags & ARCH_MASK_POWER10) != 0)
 
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 4fe6e34412aa..1a28406d8b65 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5136,7 +5136,7 @@
(use (match_operand:SFDF 1 "gpc_reg_operand"))
(use (match_operand:SFDF 2 "gpc_reg_operand"))]
   "TARGET_HARD_FLOAT
-   && TARGET_FPRND
+   && TARGET_POWER5X
&& flag_unsafe_math_optimizations"
 {
   rtx div = gen_reg_rtx (mode);
@@ -5154,7 +5154,7 @@
(use (match_operand:SFDF 1 "gpc_reg_operand"))
(use (match_operand:SFDF 2 "gpc_reg_operand"))]
   "TARGET_HARD_FLOAT
-   && TARGET_FPRND
+   && TARGET_POWER5X
&& flag_unsafe_math_optimizations"
 {
   rtx div = gen_reg_rtx (mode);
@@ -6652,7 +6652,7 @@
 (define_insn "*friz"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
(float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,wa"]
-  "TARGET_HARD_FLOAT && TARGET_FPRND
+  "TARGET_HARD_FLOAT && TARGET_POWER5X
&& flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ"
   "@
friz %0,%1
@@ -6780,7 +6780,7 @@
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 UNSPEC_FRIZ))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "@
friz %0,%1
xsrdpiz %x0,%x1"
@@ -6790,7 +6790,7 @@
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 UNSPEC_FRIP))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "@
frip %0,%1
xsrdpip %x0,%x1"
@@ -6800,7 +6800,7 @@
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 UNSPEC_FRIM))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "@
frim %0,%1
xsrdpim %x0,%x1"
@@ -6811,7 +6811,7 @@
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
 UNSPEC_FRIN))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "frin %0,%1"
   [(set_attr "type" "fp")])

[gcc(refs/users/meissner/heads/work174)] Change TARGET_CMPB to TARGET_POWER6

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:388bdfe7883afed1a6decc18c484fea0da7930b8

commit 388bdfe7883afed1a6decc18c484fea0da7930b8
Author: Michael Meissner 
Date:   Wed Jul 31 23:27:25 2024 -0400

Change TARGET_CMPB to TARGET_POWER6

As part of the architecture flags patches, this patch changes the use of
TARGET_FPRND to TARGET_POWER5X.  The FPRND instruction was added in power6 
(ISA
2.05).

2024-07-31  Michael Meissner  

* config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
TARGET_POWER6 instead of TARGET_CMPB.
* config/rs6000/rs6000.h (TARGET_FCFID): Likewise.
(TARGET_LFIWAX): Likewise.
(TARGET_POWER6): New macro.
(TARGET_EXTRA_BUILTINS): Use TARGET_POWER6 instead of TARGET_CMPB.
* config/rs6000/rs6000.md (enabled attribute): Likewise.
(parity2_cmp): Likewise.
(copysign3): Likewise.
(copysign3_fcpsgn): Likewise.
(cmpstrns): Likewise.
(cmpstrsi): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc |  4 ++--
 gcc/config/rs6000/rs6000.h  |  7 +++
 gcc/config/rs6000/rs6000.md | 16 
 3 files changed, 13 insertions(+), 14 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index ba2eba15378e..ddf744cd988a 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -157,9 +157,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P5:
   return TARGET_POWER5;
 case ENB_P6:
-  return TARGET_CMPB;
+  return TARGET_POWER6;
 case ENB_P6_64:
-  return TARGET_CMPB && TARGET_POWERPC64;
+  return TARGET_POWER6 && TARGET_POWERPC64;
 case ENB_P7:
   return TARGET_POPCNTD;
 case ENB_P7_64:
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 727167f4288f..19f6b155d38a 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -449,12 +449,12 @@ extern int rs6000_vector_align[];
 #define TARGET_FCFID   (TARGET_POWERPC64   \
 || TARGET_PPC_GPOPT/* 970/power4 */\
 || TARGET_POPCNTB  /* ISA 2.02 */  \
-|| TARGET_CMPB /* ISA 2.05 */  \
+|| TARGET_POWER6   /* ISA 2.05 */  \
 || TARGET_POPCNTD) /* ISA 2.06 */
 
 #define TARGET_FCTIDZ  TARGET_FCFID
 #define TARGET_STFIWX  TARGET_PPC_GFXOPT
-#define TARGET_LFIWAX  TARGET_CMPB
+#define TARGET_LFIWAX  TARGET_POWER6
 #define TARGET_LFIWZX  TARGET_POPCNTD
 #define TARGET_FCFIDS  TARGET_POPCNTD
 #define TARGET_FCFIDU  TARGET_POPCNTD
@@ -526,6 +526,7 @@ extern int rs6000_vector_align[];
we use architecture flags for this.  */
 #define TARGET_POWER5  ((rs6000_arch_flags & ARCH_MASK_POWER5)  != 0)
 #define TARGET_POWER5X ((rs6000_arch_flags & ARCH_MASK_POWER5X) != 0)
+#define TARGET_POWER6  ((rs6000_arch_flags & ARCH_MASK_POWER6)  != 0)
 #define TARGET_POWER8  ((rs6000_arch_flags & ARCH_MASK_POWER8)  != 0)
 #define TARGET_POWER10 ((rs6000_arch_flags & ARCH_MASK_POWER10) != 0)
 
@@ -537,8 +538,6 @@ extern int rs6000_vector_align[];
 #define TARGET_EXTRA_BUILTINS  (TARGET_POWERPC64\
 || TARGET_PPC_GPOPT /* 970/power4 */\
 || TARGET_POWER5/* ISA 2.02 */  \
-|| TARGET_CMPB  /* ISA 2.05 */  \
-|| TARGET_POPCNTD   /* ISA 2.06 */  \
 || TARGET_ALTIVEC   \
 || TARGET_VSX   \
 || TARGET_HARD_FLOAT)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 1a28406d8b65..bec73f3eb8da 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -369,7 +369,7 @@
  (const_int 1)
 
  (and (eq_attr "isa" "p6")
- (match_test "TARGET_CMPB"))
+ (match_test "TARGET_POWER6"))
  (const_int 1)
 
  (and (eq_attr "isa" "p7")
@@ -2509,7 +2509,7 @@
 (define_insn "parity2_cmpb"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] 
UNSPEC_PARITY))]
-  "TARGET_CMPB"
+  "TARGET_POWER6"
   "prty %0,%1"
   [(set_attr "type" "popcnt")])
 
@@ -2562,7 +2562,7 @@
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")
 (match_operand:GPR 2 "gpc_reg_operand" "r")] UNSPEC_CMPB))]
-  "TARGET_CMPB"
+  "TARGET_POWER6"
   "cmpb %0,%1,%2"
   [(set_attr "type" "cmp")])
 
@@ -5366,7 +5366,7 @@
&& ((TARGET_PPC_GFXOPT
 && !HONOR_NANS (mode)
 && !HONOR

[gcc(refs/users/meissner/heads/work174)] Change TARGET_POPCNTD to TARGET_POWER7

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:388e62da108b43277742f4b089b653d27fc7764b

commit 388e62da108b43277742f4b089b653d27fc7764b
Author: Michael Meissner 
Date:   Wed Jul 31 23:43:33 2024 -0400

Change TARGET_POPCNTD to TARGET_POWER7

As part of the architecture flags patches, this patch changes the use of
TARGET_POPCNTD to TARGET_POWER7.  The FPRND instruction was added in power6 
(ISA
2.05).

2024-07-31  Michael Meissner  

* config/rs6000/dfp.md (floatdidd2): Change TARGET_POPCNTD to
TARGET_POWER7.
* config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
Likewise.
* config/rs6000/rs6000-string.cc (expand_block_compare_gpr): 
Likewise.
* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached):
Likewise.
(rs6000_rtx_costs): Likewise.
(rs6000_emit_popcount): Likewise.
* config/rs6000/rs6000.h (TARGET_FCFID): Likewise.
(TARGET_LFIWZX): Likewise.
(TARGET_FCFIDS): Likewise.
(TARGET_FCFIDU): Likewise.
(TARGET_FCFIDUS): Likewise.
(TARGET_FCTIDUZ): Likewise.
(TARGET_FCTIWUZ): Likewise.
(TARGET_POWER7): New macro.
(CTZ_DEFINED_VALUE_AT_ZERO): Change TARGET_POPCNTD to TARGET_POWER7.
* config/rs6000/rs6000.md (enabled attribute): Likewise.
(ctz2): Likewise.
(popcntd2): Likewise.
(lrintsi2): Likewise.
(lrintsi): Likewise.
(lrintsi_di): Likewise.
(cmpmemsi): Likewise.
(bpermd_"): Likewise.
(addg6s): Likewise.
(cdtbcd): Likewise.
(cbcdtd): Likewise.
(div_): Likewise.

Diff:
---
 gcc/config/rs6000/dfp.md|  2 +-
 gcc/config/rs6000/rs6000-builtin.cc |  4 ++--
 gcc/config/rs6000/rs6000-string.cc  |  4 ++--
 gcc/config/rs6000/rs6000.cc |  6 +++---
 gcc/config/rs6000/rs6000.h  | 19 ++-
 gcc/config/rs6000/rs6000.md | 24 
 6 files changed, 30 insertions(+), 29 deletions(-)

diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index fa9d7dd45dd3..b8189390d410 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -214,7 +214,7 @@
 (define_insn "floatdidd2"
   [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
(float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))]
-  "TARGET_DFP && TARGET_POPCNTD"
+  "TARGET_DFP && TARGET_POWER7"
   "dcffix %0,%1"
   [(set_attr "type" "dfp")])
 
diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index ddf744cd988a..140422170a10 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -161,9 +161,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P6_64:
   return TARGET_POWER6 && TARGET_POWERPC64;
 case ENB_P7:
-  return TARGET_POPCNTD;
+  return TARGET_POWER7;
 case ENB_P7_64:
-  return TARGET_POPCNTD && TARGET_POWERPC64;
+  return TARGET_POWER7 && TARGET_POWERPC64;
 case ENB_P8:
   return TARGET_POWER8;
 case ENB_P8V:
diff --git a/gcc/config/rs6000/rs6000-string.cc 
b/gcc/config/rs6000/rs6000-string.cc
index 55b4133b1a34..3674c4bd9847 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -1948,8 +1948,8 @@ expand_block_compare_gpr(unsigned HOST_WIDE_INT bytes, 
unsigned int base_align,
 bool
 expand_block_compare (rtx operands[])
 {
-  /* TARGET_POPCNTD is already guarded at expand cmpmemsi.  */
-  gcc_assert (TARGET_POPCNTD);
+  /* TARGET_POWER7 is already guarded at expand cmpmemsi.  */
+  gcc_assert (TARGET_POWER7);
 
   /* For P8, this case is complicated to handle because the subtract
  with carry instructions do not generate the 64-bit carry and so
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 7d50fd97ad87..12d9b11de006 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1998,7 +1998,7 @@ rs6000_hard_regno_mode_ok_uncached (int regno, 
machine_mode mode)
  if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
return 1;
 
- if (TARGET_POPCNTD && mode == SImode)
+ if (TARGET_POWER7 && mode == SImode)
return 1;
 
  if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
@@ -22476,7 +22476,7 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int 
outer_code,
   return false;
 
 case POPCOUNT:
-  *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6);
+  *total = COSTS_N_INSNS (TARGET_POWER7 ? 1 : 6);
   return false;
 
 case PARITY:
@@ -23263,7 +23263,7 @@ rs6000_emit_popcount (rtx dst, rtx src)
   rtx tmp1, tmp2;
 
   /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can.  */
-  if (TARGET_POPCNTD)
+  if (TARGET_POWER7)
 {
   if (mode == SImode)
emit_insn (gen_popcntdsi2 (dst

[gcc(refs/users/meissner/heads/work174)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:135ff7d313d1e6105518f445e3f27dc7d62b1f2a

commit 135ff7d313d1e6105518f445e3f27dc7d62b1f2a
Author: Michael Meissner 
Date:   Wed Jul 31 23:45:36 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 111 +
 1 file changed, 111 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 8e1fc5989cc9..84c2de03f070 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,114 @@
+ Branch work174, patch #43 
+
+Change TARGET_POPCNTD to TARGET_POWER7
+
+As part of the architecture flags patches, this patch changes the use of
+TARGET_POPCNTD to TARGET_POWER7.  The FPRND instruction was added in power6 
(ISA
+2.05).
+
+2024-07-31  Michael Meissner  
+
+   * config/rs6000/dfp.md (floatdidd2): Change TARGET_POPCNTD to
+   TARGET_POWER7.
+   * config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
+   Likewise.
+   * config/rs6000/rs6000-string.cc (expand_block_compare_gpr): Likewise.
+   * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached):
+   Likewise.
+   (rs6000_rtx_costs): Likewise.
+   (rs6000_emit_popcount): Likewise.
+   * config/rs6000/rs6000.h (TARGET_FCFID): Likewise.
+   (TARGET_LFIWZX): Likewise.
+   (TARGET_FCFIDS): Likewise.
+   (TARGET_FCFIDU): Likewise.
+   (TARGET_FCFIDUS): Likewise.
+   (TARGET_FCTIDUZ): Likewise.
+   (TARGET_FCTIWUZ): Likewise.
+   (TARGET_POWER7): New macro.
+   (CTZ_DEFINED_VALUE_AT_ZERO): Change TARGET_POPCNTD to TARGET_POWER7.
+   * config/rs6000/rs6000.md (enabled attribute): Likewise.
+   (ctz2): Likewise.
+   (popcntd2): Likewise.
+   (lrintsi2): Likewise.
+   (lrintsi): Likewise.
+   (lrintsi_di): Likewise.
+   (cmpmemsi): Likewise.
+   (bpermd_"): Likewise.
+   (addg6s): Likewise.
+   (cdtbcd): Likewise.
+   (cbcdtd): Likewise.
+   (div_): Likewise.
+
+ Branch work174, patch #42 
+
+Change TARGET_CMPB to TARGET_POWER6
+
+As part of the architecture flags patches, this patch changes the use of
+TARGET_FPRND to TARGET_POWER6.  The CMPB instruction was added in power6 (ISA
+2.05).
+
+2024-07-31  Michael Meissner  
+
+   * config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
+   TARGET_POWER6 instead of TARGET_CMPB.
+   * config/rs6000/rs6000.h (TARGET_FCFID): Likewise.
+   (TARGET_LFIWAX): Likewise.
+   (TARGET_POWER6): New macro.
+   (TARGET_EXTRA_BUILTINS): Use TARGET_POWER6 instead of TARGET_CMPB.
+   * config/rs6000/rs6000.md (enabled attribute): Likewise.
+   (parity2_cmp): Likewise.
+   (copysign3): Likewise.
+   (copysign3_fcpsgn): Likewise.
+   (cmpstrns): Likewise.
+   (cmpstrsi): Likewise.
+
+ Branch work174, patch #41 
+
+Change TARGET_FPRND to TARGET_POWER5X
+
+As part of the architecture flags patches, this patch changes the use of
+TARGET_FPRND to TARGET_POWER5X.  The FPRND instruction was added in power5+.
+
+2024-07-31  Michael Meissner  
+
+   * config/rs6000/rs6000.cc (report_architecture_mismatch): Use
+   TARGET_POWER5X instead of TARGET_FPRND.
+   * config/rs6000/rs6000.h (TARGET_POWER5X): New macro.
+   * config/rs6000/rs6000.md (fmod3): Use TARGET_POWER5X instead of
+   TARGET_FPRND.
+   (remainder3): Likewise.
+   (fctiwuz_): Likewise.
+   (btrunc2): Likewise.
+   (ceil2): Likewise.
+   (floor2): Likewise.
+   (round): Likewise.
+
+ Branch work174, patch #40 
+
+Change TARGET_POPCNTB to TARGET_POWER5
+
+As part of the architecture flags patches, this patch changes the use of
+TARGET_POPCNTB to TARGET_POWER5.  The POPCNTB instruction was added in ISA 2.02
+(power5).
+
+2024-07-31  Michael Meissner  
+
+   * config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
+   TARGET_POWER5 instead of TARGET_POPCNTB.
+   * config/rs6000/rs6000.h (TARGET_POWER5): New macro.
+   (TARGET_EXTRA_BUILTINS): Use TARGET_POWER5 instead of TARGET_POPCNTB.
+   (TARGET_FRE): Likewise.
+   (TARGET_FRSQRTES): Likewise.
+   * config/rs6000/rs6000.md (enabled attribute): Likewise.
+   (popcount): Use TARGET_POWER5 instead of TARGET_POPCNTB.  Drop
+   test for TARGET_POPCNTD (i.e power7), since TARGET_POPCNTB will always
+   be set if TARGET_POPCNTD is set.
+   (popcntb2): Use TARGET_POWER5 instead of TARGET_POPCNTB.
+   (parity2): Likewise.
+   (parity2_cmpb): Remove TARGET_POPCNTB test, since it will always
+   be true when TARGET_CMPB (i.e. power6) is set.
+
+
  Branch work174, patch #35 
 
 Update tests to work with architecture flags changes.

[gcc(refs/users/meissner/heads/work174)] Change TARGET_MODULO to TARGET_POWER9

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:1c7379153ae97154c7eba2e780ffbf02e663c0ef

commit 1c7379153ae97154c7eba2e780ffbf02e663c0ef
Author: Michael Meissner 
Date:   Thu Aug 1 01:42:41 2024 -0400

Change TARGET_MODULO to TARGET_POWER9

As part of the architecture flags patches, this patch changes the use of
TARGET_POPCNTD to TARGET_POWER7.  The modulo instructions were added in 
power9 (ISA
3.0).  Note, I did not change the uses of TARGET_MODULO where it was 
explicitly
generating different code if the machine had a modulo instruction.

2024-08-01  Michael Meissner  

* config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
TARGET_POWER9 instead of TARGET_MODULO.
* config/rs6000/rs6000.h (TARGET_CTZ): Likewise.
(TARGET_EXTSWSLI): Likewise.
(TARGET_MADDLD): Likewise.
(TARGET_POWER9): New macro.
* config/rs6000/rs6000.md (enabled attribute): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-builtin.cc | 4 ++--
 gcc/config/rs6000/rs6000.h  | 7 ---
 gcc/config/rs6000/rs6000.md | 2 +-
 3 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc 
b/gcc/config/rs6000/rs6000-builtin.cc
index 140422170a10..1f808f69e8f9 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -169,9 +169,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins 
fncode)
 case ENB_P8V:
   return TARGET_P8_VECTOR;
 case ENB_P9:
-  return TARGET_MODULO;
+  return TARGET_POWER9;
 case ENB_P9_64:
-  return TARGET_MODULO && TARGET_POWERPC64;
+  return TARGET_POWER9 && TARGET_POWERPC64;
 case ENB_P9V:
   return TARGET_P9_VECTOR;
 case ENB_P10:
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 23c256b3a5ff..5bdda4e6ce29 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -463,9 +463,9 @@ extern int rs6000_vector_align[];
 #define TARGET_FCTIWUZ TARGET_POWER7
 /* Only powerpc64 and powerpc476 support fctid.  */
 #define TARGET_FCTID   (TARGET_POWERPC64 || rs6000_cpu == PROCESSOR_PPC476)
-#define TARGET_CTZ TARGET_MODULO
-#define TARGET_EXTSWSLI(TARGET_MODULO && TARGET_POWERPC64)
-#define TARGET_MADDLD  TARGET_MODULO
+#define TARGET_CTZ TARGET_POWER9
+#define TARGET_EXTSWSLI(TARGET_POWER9 && TARGET_POWERPC64)
+#define TARGET_MADDLD  TARGET_POWER9
 
 /* TARGET_DIRECT_MOVE is redundant to TARGET_P8_VECTOR, so alias it to that.  
*/
 #define TARGET_DIRECT_MOVE TARGET_P8_VECTOR
@@ -529,6 +529,7 @@ extern int rs6000_vector_align[];
 #define TARGET_POWER6  ((rs6000_arch_flags & ARCH_MASK_POWER6)  != 0)
 #define TARGET_POWER7  ((rs6000_arch_flags & ARCH_MASK_POWER7)  != 0)
 #define TARGET_POWER8  ((rs6000_arch_flags & ARCH_MASK_POWER8)  != 0)
+#define TARGET_POWER9  ((rs6000_arch_flags & ARCH_MASK_POWER9)  != 0)
 #define TARGET_POWER10 ((rs6000_arch_flags & ARCH_MASK_POWER10) != 0)
 
 /* For power systems, we want to enable Altivec and VSX builtins even if the
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 04657a2a8e61..c285f5028e60 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -389,7 +389,7 @@
  (const_int 1)
 
  (and (eq_attr "isa" "p9")
- (match_test "TARGET_MODULO"))
+ (match_test "TARGET_POWER9"))
  (const_int 1)
 
  (and (eq_attr "isa" "p9v")

[gcc(refs/users/meissner/heads/work174)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:5dae57e91e5421a6af6378b2afc8c83b1badddef

commit 5dae57e91e5421a6af6378b2afc8c83b1badddef
Author: Michael Meissner 
Date:   Thu Aug 1 01:44:47 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 84c2de03f070..c68d828220ae 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,22 @@
+ Branch work174, patch #44 
+
+Change TARGET_MODULO to TARGET_POWER9
+
+As part of the architecture flags patches, this patch changes the use of
+TARGET_POPCNTD to TARGET_POWER7.  The modulo instructions were added in power9 
(ISA
+3.0).  Note, I did not change the uses of TARGET_MODULO where it was explicitly
+generating different code if the machine had a modulo instruction.
+
+2024-08-01  Michael Meissner  
+
+   * config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
+   TARGET_POWER9 instead of TARGET_MODULO.
+   * config/rs6000/rs6000.h (TARGET_CTZ): Likewise.
+   (TARGET_EXTSWSLI): Likewise.
+   (TARGET_MADDLD): Likewise.
+   (TARGET_POWER9): New macro.
+   * config/rs6000/rs6000.md (enabled attribute): Likewise.
+
  Branch work174, patch #43 
 
 Change TARGET_POPCNTD to TARGET_POWER7