[gcc(refs/users/meissner/heads/work174)] Update tests to work with architecture flags changes.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:99e205eb7b5a43789691a29e59d7f7fdffb3b199

commit 99e205eb7b5a43789691a29e59d7f7fdffb3b199
Author: Michael Meissner <meiss...@linux.ibm.com>
Date:   Wed Jul 31 13:51:08 2024 -0400

    Update tests to work with architecture flags changes.
    
    Two tests used -mvsx to raise the processor level to at least power7.  These
    tests were rewritten to add cpu=power7 support.
    
    2024-07-31  Michael Meissner  <meiss...@linux.ibm.com>
    
    gcc/testsuite/
    
            * gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add 
cpu=power7
            when we need to add VSX support.  Add test for adding cpu=power7 
no-vsx
            to generate only Altivec instructions.
            * gcc.target/powerpc/pr115688.c: Add cpu=power7 when requesting VSX
            instructions.
            * gcc.target/powerpc/vsx-cpu-mismatch.c: New test.

Diff:
---
 gcc/testsuite/gcc.target/powerpc/ppc-target-4.c    | 40 ++++++++++++++++------
 gcc/testsuite/gcc.target/powerpc/pr115688.c        |  3 +-
 .../gcc.target/powerpc/vsx-cpu-mismatch.c          |  8 +++++
 3 files changed, 40 insertions(+), 11 deletions(-)

diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c 
b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
index db9ba500e0e1..42f5aa354d0a 100644
--- a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
@@ -1,8 +1,8 @@
 /* { dg-do compile { target { powerpc*-*-* } } } */
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -ffast-math -mdejagnu-cpu=power5 -mno-altivec 
-mabi=altivec -fno-unroll-loops" } */
-/* { dg-final { scan-assembler-times "vaddfp" 1 } } */
+/* { dg-options "-O3 -ffast-math -mdejagnu-cpu=power5 -mno-altivec 
-mabi=altivec -fno-unroll-loops" } */
+/* { dg-final { scan-assembler-times "vaddfp" 2 } } */
 /* { dg-final { scan-assembler-times "xvaddsp" 1 } } */
 /* { dg-final { scan-assembler-times "fadds" 1 } } */
 
@@ -18,10 +18,6 @@
 #error "__VSX__ should not be defined."
 #endif
 
-#pragma GCC target("altivec,vsx")
-#include <altivec.h>
-#pragma GCC reset_options
-
 #pragma GCC push_options
 #pragma GCC target("altivec,no-vsx")
 
@@ -33,6 +29,7 @@
 #error "__VSX__ should not be defined."
 #endif
 
+/* Altivec build, generate vaddfp.  */
 void
 av_add (vector float *a, vector float *b, vector float *c)
 {
@@ -40,10 +37,11 @@ av_add (vector float *a, vector float *b, vector float *c)
   unsigned long n = SIZE / 4;
 
   for (i = 0; i < n; i++)
-    a[i] = vec_add (b[i], c[i]);
+    a[i] = b[i] + c[i];
 }
 
-#pragma GCC target("vsx")
+/* cpu=power7 must be used to enable VSX.  */
+#pragma GCC target("cpu=power7,vsx")
 
 #ifndef __ALTIVEC__
 #error "__ALTIVEC__ should be defined."
@@ -53,6 +51,7 @@ av_add (vector float *a, vector float *b, vector float *c)
 #error "__VSX__ should be defined."
 #endif
 
+/* VSX build on power7, generate xsaddsp.  */
 void
 vsx_add (vector float *a, vector float *b, vector float *c)
 {
@@ -60,11 +59,31 @@ vsx_add (vector float *a, vector float *b, vector float *c)
   unsigned long n = SIZE / 4;
 
   for (i = 0; i < n; i++)
-    a[i] = vec_add (b[i], c[i]);
+    a[i] = b[i] + c[i];
+}
+
+#pragma GCC target("cpu=power7,no-vsx")
+
+#ifndef __ALTIVEC__
+#error "__ALTIVEC__ should be defined."
+#endif
+
+#ifdef __VSX__
+#error "__VSX__ should not be defined."
+#endif
+
+/* Altivec build on power7 with no VSX, generate vaddfp.  */
+void
+av2_add (vector float *a, vector float *b, vector float *c)
+{
+  unsigned long i;
+  unsigned long n = SIZE / 4;
+
+  for (i = 0; i < n; i++)
+    a[i] = b[i] + c[i];
 }
 
 #pragma GCC pop_options
-#pragma GCC target("no-vsx,no-altivec")
 
 #ifdef __ALTIVEC__
 #error "__ALTIVEC__ should not be defined."
@@ -74,6 +93,7 @@ vsx_add (vector float *a, vector float *b, vector float *c)
 #error "__VSX__ should not be defined."
 #endif
 
+/* Default power5 build, generate scalar fadds.  */
 void
 norm_add (float *a, float *b, float *c)
 {
diff --git a/gcc/testsuite/gcc.target/powerpc/pr115688.c 
b/gcc/testsuite/gcc.target/powerpc/pr115688.c
index 5222e66ef170..00c7c301436a 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr115688.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr115688.c
@@ -7,7 +7,8 @@
 
 /* Verify there is no ICE under 32 bit env.  */
 
-__attribute__((target("vsx")))
+/* cpu=power7 must be used to enable VSX.  */
+__attribute__((target("cpu=power7,vsx")))
 int test (void)
 {
   return 0;
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-cpu-mismatch.c 
b/gcc/testsuite/gcc.target/powerpc/vsx-cpu-mismatch.c
new file mode 100644
index 000000000000..ff1efd622523
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-cpu-mismatch.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx } */
+/* { dg-options "-O2 -mdejagnu-cpu=power5 -mvsx" } */
+/* { dg-error "‘vsx’ needs at least ‘-mcpu=power7’" } */
+
+/* Make sure -mcpu=power5 -mvsx gives an error if the cpu is not capable of VSX
+   support.  */
+int x;