https://gcc.gnu.org/g:388bdfe7883afed1a6decc18c484fea0da7930b8
commit 388bdfe7883afed1a6decc18c484fea0da7930b8
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Wed Jul 31 23:27:25 2024 -0400
Change TARGET_CMPB to TARGET_POWER6
As part of the architecture flags patches, this patch changes the use of
TARGET_FPRND to TARGET_POWER5X. The FPRND instruction was added in power6
(ISA
2.05).
2024-07-31 Michael Meissner <meiss...@linux.ibm.com>
* config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
TARGET_POWER6 instead of TARGET_CMPB.
* config/rs6000/rs6000.h (TARGET_FCFID): Likewise.
(TARGET_LFIWAX): Likewise.
(TARGET_POWER6): New macro.
(TARGET_EXTRA_BUILTINS): Use TARGET_POWER6 instead of TARGET_CMPB.
* config/rs6000/rs6000.md (enabled attribute): Likewise.
(parity<mode>2_cmp): Likewise.
(copysign<mode>3): Likewise.
(copysign<mode>3_fcpsgn): Likewise.
(cmpstrns): Likewise.
(cmpstrsi): Likewise.
Diff:
---
gcc/config/rs6000/rs6000-builtin.cc | 4 ++--
gcc/config/rs6000/rs6000.h | 7 +++----
gcc/config/rs6000/rs6000.md | 16 ++++++++--------
3 files changed, 13 insertions(+), 14 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index ba2eba15378e..ddf744cd988a 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -157,9 +157,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins
fncode)
case ENB_P5:
return TARGET_POWER5;
case ENB_P6:
- return TARGET_CMPB;
+ return TARGET_POWER6;
case ENB_P6_64:
- return TARGET_CMPB && TARGET_POWERPC64;
+ return TARGET_POWER6 && TARGET_POWERPC64;
case ENB_P7:
return TARGET_POPCNTD;
case ENB_P7_64:
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 727167f4288f..19f6b155d38a 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -449,12 +449,12 @@ extern int rs6000_vector_align[];
#define TARGET_FCFID (TARGET_POWERPC64 \
|| TARGET_PPC_GPOPT /* 970/power4 */ \
|| TARGET_POPCNTB /* ISA 2.02 */ \
- || TARGET_CMPB /* ISA 2.05 */ \
+ || TARGET_POWER6 /* ISA 2.05 */ \
|| TARGET_POPCNTD) /* ISA 2.06 */
#define TARGET_FCTIDZ TARGET_FCFID
#define TARGET_STFIWX TARGET_PPC_GFXOPT
-#define TARGET_LFIWAX TARGET_CMPB
+#define TARGET_LFIWAX TARGET_POWER6
#define TARGET_LFIWZX TARGET_POPCNTD
#define TARGET_FCFIDS TARGET_POPCNTD
#define TARGET_FCFIDU TARGET_POPCNTD
@@ -526,6 +526,7 @@ extern int rs6000_vector_align[];
we use architecture flags for this. */
#define TARGET_POWER5 ((rs6000_arch_flags & ARCH_MASK_POWER5) != 0)
#define TARGET_POWER5X ((rs6000_arch_flags & ARCH_MASK_POWER5X) != 0)
+#define TARGET_POWER6 ((rs6000_arch_flags & ARCH_MASK_POWER6) != 0)
#define TARGET_POWER8 ((rs6000_arch_flags & ARCH_MASK_POWER8) != 0)
#define TARGET_POWER10 ((rs6000_arch_flags & ARCH_MASK_POWER10) != 0)
@@ -537,8 +538,6 @@ extern int rs6000_vector_align[];
#define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \
|| TARGET_PPC_GPOPT /* 970/power4 */ \
|| TARGET_POWER5 /* ISA 2.02 */ \
- || TARGET_CMPB /* ISA 2.05 */ \
- || TARGET_POPCNTD /* ISA 2.06 */ \
|| TARGET_ALTIVEC \
|| TARGET_VSX \
|| TARGET_HARD_FLOAT)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 1a28406d8b65..bec73f3eb8da 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -369,7 +369,7 @@
(const_int 1)
(and (eq_attr "isa" "p6")
- (match_test "TARGET_CMPB"))
+ (match_test "TARGET_POWER6"))
(const_int 1)
(and (eq_attr "isa" "p7")
@@ -2509,7 +2509,7 @@
(define_insn "parity<mode>2_cmpb"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
UNSPEC_PARITY))]
- "TARGET_CMPB"
+ "TARGET_POWER6"
"prty<wd> %0,%1"
[(set_attr "type" "popcnt")])
@@ -2562,7 +2562,7 @@
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")
(match_operand:GPR 2 "gpc_reg_operand" "r")] UNSPEC_CMPB))]
- "TARGET_CMPB"
+ "TARGET_POWER6"
"cmpb %0,%1,%2"
[(set_attr "type" "cmp")])
@@ -5366,7 +5366,7 @@
&& ((TARGET_PPC_GFXOPT
&& !HONOR_NANS (<MODE>mode)
&& !HONOR_SIGNED_ZEROS (<MODE>mode))
- || TARGET_CMPB
+ || TARGET_POWER6
|| VECTOR_UNIT_VSX_P (<MODE>mode))"
{
/* Middle-end canonicalizes -fabs (x) to copysign (x, -1),
@@ -5387,7 +5387,7 @@
if (!gpc_reg_operand (operands[2], <MODE>mode))
operands[2] = copy_to_mode_reg (<MODE>mode, operands[2]);
- if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
+ if (TARGET_POWER6 || VECTOR_UNIT_VSX_P (<MODE>mode))
{
emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
operands[2]));
@@ -5403,7 +5403,7 @@
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
(copysign:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")
(match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))]
- "TARGET_HARD_FLOAT && (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))"
+ "TARGET_HARD_FLOAT && (TARGET_POWER6 || VECTOR_UNIT_VSX_P (<MODE>mode))"
"@
fcpsgn %0,%2,%1
xscpsgndp %x0,%x2,%x1"
@@ -10081,7 +10081,7 @@
(match_operand:BLK 2)))
(use (match_operand:SI 3))
(use (match_operand:SI 4))])]
- "TARGET_CMPB && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
+ "TARGET_POWER6 && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
{
if (optimize_insn_for_size_p ())
FAIL;
@@ -10103,7 +10103,7 @@
(compare:SI (match_operand:BLK 1)
(match_operand:BLK 2)))
(use (match_operand:SI 3))])]
- "TARGET_CMPB && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
+ "TARGET_POWER6 && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
{
if (optimize_insn_for_size_p ())
FAIL;
