https://gcc.gnu.org/g:1c7379153ae97154c7eba2e780ffbf02e663c0ef
commit 1c7379153ae97154c7eba2e780ffbf02e663c0ef
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Thu Aug 1 01:42:41 2024 -0400
Change TARGET_MODULO to TARGET_POWER9
As part of the architecture flags patches, this patch changes the use of
TARGET_POPCNTD to TARGET_POWER7. The modulo instructions were added in
power9 (ISA
3.0). Note, I did not change the uses of TARGET_MODULO where it was
explicitly
generating different code if the machine had a modulo instruction.
2024-08-01 Michael Meissner <meiss...@linux.ibm.com>
* config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
TARGET_POWER9 instead of TARGET_MODULO.
* config/rs6000/rs6000.h (TARGET_CTZ): Likewise.
(TARGET_EXTSWSLI): Likewise.
(TARGET_MADDLD): Likewise.
(TARGET_POWER9): New macro.
* config/rs6000/rs6000.md (enabled attribute): Likewise.
Diff:
---
gcc/config/rs6000/rs6000-builtin.cc | 4 ++--
gcc/config/rs6000/rs6000.h | 7 ++++---
gcc/config/rs6000/rs6000.md | 2 +-
3 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index 140422170a10..1f808f69e8f9 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -169,9 +169,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins
fncode)
case ENB_P8V:
return TARGET_P8_VECTOR;
case ENB_P9:
- return TARGET_MODULO;
+ return TARGET_POWER9;
case ENB_P9_64:
- return TARGET_MODULO && TARGET_POWERPC64;
+ return TARGET_POWER9 && TARGET_POWERPC64;
case ENB_P9V:
return TARGET_P9_VECTOR;
case ENB_P10:
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 23c256b3a5ff..5bdda4e6ce29 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -463,9 +463,9 @@ extern int rs6000_vector_align[];
#define TARGET_FCTIWUZ TARGET_POWER7
/* Only powerpc64 and powerpc476 support fctid. */
#define TARGET_FCTID (TARGET_POWERPC64 || rs6000_cpu == PROCESSOR_PPC476)
-#define TARGET_CTZ TARGET_MODULO
-#define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64)
-#define TARGET_MADDLD TARGET_MODULO
+#define TARGET_CTZ TARGET_POWER9
+#define TARGET_EXTSWSLI (TARGET_POWER9 && TARGET_POWERPC64)
+#define TARGET_MADDLD TARGET_POWER9
/* TARGET_DIRECT_MOVE is redundant to TARGET_P8_VECTOR, so alias it to that.
*/
#define TARGET_DIRECT_MOVE TARGET_P8_VECTOR
@@ -529,6 +529,7 @@ extern int rs6000_vector_align[];
#define TARGET_POWER6 ((rs6000_arch_flags & ARCH_MASK_POWER6) != 0)
#define TARGET_POWER7 ((rs6000_arch_flags & ARCH_MASK_POWER7) != 0)
#define TARGET_POWER8 ((rs6000_arch_flags & ARCH_MASK_POWER8) != 0)
+#define TARGET_POWER9 ((rs6000_arch_flags & ARCH_MASK_POWER9) != 0)
#define TARGET_POWER10 ((rs6000_arch_flags & ARCH_MASK_POWER10) != 0)
/* For power systems, we want to enable Altivec and VSX builtins even if the
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 04657a2a8e61..c285f5028e60 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -389,7 +389,7 @@
(const_int 1)
(and (eq_attr "isa" "p9")
- (match_test "TARGET_MODULO"))
+ (match_test "TARGET_POWER9"))
(const_int 1)
(and (eq_attr "isa" "p9v")
