[gcc(refs/users/meissner/heads/work174)] Add power5+ to arch flags.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:d964bf62dfeeb413f2af87994b677c85aef6408d

commit d964bf62dfeeb413f2af87994b677c85aef6408d
Author: Michael Meissner <meiss...@linux.ibm.com>
Date:   Wed Jul 31 12:23:55 2024 -0400

    Add power5+ to arch flags.
    
    2024-07-31  Michael Meissner  <meiss...@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/rs6000-arch.def (ARCH_MASK_POWER5X): Add power5+
            support.
            * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use arch
            masks for power4, power5, power5+, and power6.
            * config/rs6000/rs6000.cc (get_arch_flags): Add support for setting 
arch
            flags for non power* processors.  Add support for power5+.
            (report_architecture_mismatch): Improve error message.

Diff:
---
 gcc/config/rs6000/rs6000-arch.def |  1 +
 gcc/config/rs6000/rs6000-c.cc     |  8 ++++----
 gcc/config/rs6000/rs6000.cc       | 20 +++++++++++++++++---
 3 files changed, 22 insertions(+), 7 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-arch.def 
b/gcc/config/rs6000/rs6000-arch.def
index 6725736076da..e5b6e9581331 100644
--- a/gcc/config/rs6000/rs6000-arch.def
+++ b/gcc/config/rs6000/rs6000-arch.def
@@ -39,6 +39,7 @@
 
 ARCH_EXPAND(POWER4,  "power4")
 ARCH_EXPAND(POWER5,  "power5")
+ARCH_EXPAND(POWER5X, "power5+")
 ARCH_EXPAND(POWER6,  "power6")
 ARCH_EXPAND(POWER7,  "power7")
 ARCH_EXPAND(POWER8,  "power8")
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index a8a6a956874f..d7b1625f0867 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -420,13 +420,13 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT 
flags,
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
   if ((flags & OPTION_MASK_POWERPC64) != 0)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
-  if ((flags & OPTION_MASK_MFCRF) != 0)
+  if ((arch_flags & ARCH_MASK_POWER4) != 0)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
-  if ((flags & OPTION_MASK_POPCNTB) != 0)
+  if ((arch_flags & ARCH_MASK_POWER5) != 0)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
-  if ((flags & OPTION_MASK_FPRND) != 0)
+  if ((arch_flags & ARCH_MASK_POWER5X) != 0)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
-  if ((flags & OPTION_MASK_CMPB) != 0)
+  if ((arch_flags & ARCH_MASK_POWER6) != 0)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
   if ((arch_flags & ARCH_MASK_POWER7) != 0)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 19adc66cc801..ec1cf85de12f 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1856,6 +1856,8 @@ get_arch_flags (int cpu_index)
 
       case PROCESSOR_POWER5:
        ret |= ARCH_MASK_POWER5;
+       if (TARGET_FPRND)
+         ret |= ARCH_MASK_POWER5X;
        /* fall through.  */
 
       case PROCESSOR_POWER4:
@@ -1863,6 +1865,18 @@ get_arch_flags (int cpu_index)
        break;
 
       default:
+       /* For other processors, set the arch flags based on the ISA bits.  */
+       if (TARGET_MFCRF)
+         ret |= ARCH_MASK_POWER4;
+
+       if (TARGET_POPCNTB)
+         ret |= ARCH_MASK_POWER5;
+
+       if (TARGET_FPRND)
+         ret |= ARCH_MASK_POWER5X;
+
+       if (TARGET_CMPB)
+         ret |= ARCH_MASK_POWER6;
        break;
       }
 
@@ -25359,19 +25373,19 @@ report_architecture_mismatch (void)
       OPTION_MASK_P9_VECTOR | OPTION_MASK_P9_MISC | OPTION_MASK_P9_MINMAX
       | OPTION_MASK_MODULO,
       ARCH_MASK_POWER9,
-      "cpu=power9"
+      "-mcpu=power9"
     },
 
     {
       OPTION_MASK_P8_VECTOR | OPTION_MASK_CRYPTO,
       ARCH_MASK_POWER8,
-      "cpu=power8"
+      "-mcpu=power8"
     },
 
     {
       OPTION_MASK_VSX | OPTION_MASK_POPCNTD,
       ARCH_MASK_POWER7,
-      "cpu=power7"
+      "-mcpu=power7"
     },
   };