dentation in platform driver struct are beautified a little.
>
> Signed-off-by: Vladimir Zapolskiy
> ---
> Changes from v1 to v2:
> * a kernel for iMX boards is always built with multiplatform support,
> thus CONFIG_OF guards were removed, thanks to Kim Phillips for review,
Tha
On Tue, 27 Feb 2018 18:53:08 +0200
Vladimir Zapolskiy wrote:
> On 02/27/2018 05:49 PM, Kim Phillips wrote:
> > On Mon, 26 Feb 2018 20:38:49 +0200
> > Vladimir Zapolskiy wrote:
> >
> >> +#ifdef CONFIG_OF
> >> +static const struct of_device_id mxc_rnga_of_m
On Mon, 26 Feb 2018 20:38:49 +0200
Vladimir Zapolskiy wrote:
> +#ifdef CONFIG_OF
> +static const struct of_device_id mxc_rnga_of_match[] = {
> + { .compatible = "fsl,imx31-rnga", },
> + { /* sentinel */ },
> +};
> +MODULE_DEVICE_TABLE(of, mxc_rnga_of_match);
> +#endif
> +
> static struct
On Mon, 13 Nov 2017 09:44:06 +
Radu Andrei Alexe wrote:
> On 11/10/2017 6:44 PM, Kim Phillips wrote:
> > On Fri, 10 Nov 2017 08:02:01 +
> > Radu Andrei Alexe wrote:
> >
> >> On 11/9/2017 6:34 PM, Kim Phillips wrote:
> >>> On Thu, 9 Nov 2017 11:
On Mon, 13 Nov 2017 08:32:24 +
Horia Geantă wrote:
> On 11/10/2017 6:44 PM, Kim Phillips wrote:
> > On Fri, 10 Nov 2017 08:02:01 +
> > Radu Andrei Alexe wrote:
> [snip]>> 2. I wanted this driver to be tracked by the dma engine team.
> They have
> >
On Fri, 10 Nov 2017 08:02:01 +
Radu Andrei Alexe wrote:
> On 11/9/2017 6:34 PM, Kim Phillips wrote:
> > On Thu, 9 Nov 2017 11:54:13 +
> > Radu Andrei Alexe wrote:
> >> The next patch version will create the platform device dynamically at
> >> run time.
On Thu, 9 Nov 2017 11:54:13 +
Radu Andrei Alexe wrote:
> On 10/30/2017 4:24 PM, Kim Phillips wrote:
> > On Mon, 30 Oct 2017 15:46:51 +0200
> > Horia Geantă wrote:
> >
> >> +=
> >> +CA
On Mon, 30 Oct 2017 15:46:51 +0200
Horia Geantă wrote:
> +=
> +CAAM DMA Node
> +
> +Child node of the crypto node that enables the use of the DMA
> capabilities
> +of the CAAM by a stand-alone driver. The only required p
On Thu, 28 Apr 2016 17:15:30 +0300
Alexandru Ardelean wrote:
> From: Alexandru Ardelean
>
> Crypto hash algorithms must provide the statesize sometime
> from kernel 4.2 onwards.
> Since commit 8996eafdcbad149ac0f772fb1649fbb75c482a6a
>
> Signed-off-by: Alexandru Ardelean
> ---
This should alre
On Thu, 21 Apr 2016 13:31:47 +
Horia Ioan Geanta Neag wrote:
> On 4/20/2016 3:04 PM, Christophe Leroy wrote:
> > What's the best way to implement the selection of the proper descriptor
> > type ?
> > * We can duplicate the templates but it means that when both types are
> > supported the driv
On Thu, 21 Apr 2016 13:31:47 +
Horia Ioan Geanta Neag wrote:
> On 4/20/2016 3:04 PM, Christophe Leroy wrote:
> > Today, in Talitos driver crypto alg registration is based on predefined
> > templates with a predefined descriptor type and verification against the
> > descriptors supported by th
On Thu, 19 Mar 2015 17:56:57 +0200
Horia Geantă wrote:
> On 3/18/2015 12:03 AM, Kim Phillips wrote:
> > On Tue, 17 Mar 2015 19:58:55 +0200
> > Horia Geantă wrote:
> >
> >> On 3/17/2015 2:19 AM, Kim Phillips wrote:
> >>> On Mon, 16 Mar 201
On Tue, 17 Mar 2015 19:58:55 +0200
Horia Geantă wrote:
> On 3/17/2015 2:19 AM, Kim Phillips wrote:
> > On Mon, 16 Mar 2015 12:02:51 +0200
> > Horia Geantă wrote:
> >
> >> On 3/4/2015 2:23 AM, Kim Phillips wrote:
> >>> Only potential problem is
On Mon, 16 Mar 2015 12:02:51 +0200
Horia Geantă wrote:
> On 3/4/2015 2:23 AM, Kim Phillips wrote:
> > Only potential problem is getting the crypto API to set the GFP_DMA
> > flag in the allocation request, but presumably a
> > CRYPTO_TFM_REQ_DMA crt_flag can be made to ha
On Fri, 6 Mar 2015 17:42:26 +0100
Christophe Leroy wrote:
> This patch adds talitos1.c and talitos1.h with all specificities needed
> to handle the SEC1 security engine found in MPC885 and MPC8272.
>
> The SEC1 has several differences with its younger brother SEC2:
> * Several bits in registers
On Fri, 6 Mar 2015 11:49:43 -0500
Martin Hicks wrote:
> On Thu, Mar 5, 2015 at 7:16 PM, Kim Phillips
> wrote:
> > On Fri, 20 Feb 2015 12:00:10 -0500
> > Martin Hicks wrote:
> >
> >> The newer talitos hardware has support for AES in XTS mode.
> >
> >
38388 48546ed9 6000 <0fe0> 3c62ff8f 38637fc8 48546ec5
> ---[ end trace e43fd1734d6600df ]---
>
> Signed-off-by: Yanjiang Jin
> ---
Acked-by: Kim Phillips
Thanks,
Kim
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pc/crypto' failed
Move the two sha1 spe files under crypto/, and whilst there, rename
other powerpc crypto files with underscores to use dashes for
consistency.
Cc: Markus Stockhausen
Signed-off-by: Kim Phillips
---
applies to today's cryptodev-2.6.
arch/powerpc/crypto
/0x700
> [effcbfe0] [c00455d8] irq_exit+0x108/0x120
> [effcbff0] [c000f520] call_do_irq+0x24/0x3c
> [e95a3e20] [c00059b8] do_IRQ+0xc8/0x170
> [e95a3e50] [c0011bc8] ret_from_except+0x0/0x18
>
> Signed-off-by: Yanjiang Jin
> ---
Acked-by: Kim Phillips
Thanks,
Kim
-
On Thu, 5 Mar 2015 09:12:13 +0200
Cristian Stoica wrote:
> On 03/04/2015 08:34 PM, Kim Phillips wrote:
>
> > I don't see how, e.g., for one, dma_map_sg is I/O TLB
> > implementation-dependent.
>
> I'll need some remedial classes on this topic, but for the mom
On Thu, 5 Mar 2015 11:35:23 +0200
Horia Geantă wrote:
> On 3/4/2015 2:23 AM, Kim Phillips wrote:
> > On Tue, 3 Mar 2015 08:21:37 -0500
> > Martin Hicks wrote:
> >
> >> @@ -1170,6 +1237,8 @@ static struct talitos_edesc
> >>
On Thu, 5 Mar 2015 10:52:37 +0800
yjin wrote:
> On 2015年03月05日 02:36, Kim Phillips wrote:
> > On Wed, 4 Mar 2015 13:33:22 +0800
> > yjin wrote:
> >
> >> On 2015年03月04日 03:31, Kim Phillips wrote:
> >>> On Tue, 3 Mar 2015 14:50:52 +0800
> >>>
On Thu, 5 Mar 2015 17:46:05 +0100
Christophe Leroy wrote:
> [15/17] crypto: talitos - Implementation of SEC1
...
> [16/17] crypto: talitos - SEC1 bugs on 0 data hash
> [17/17] crypto: talitos - Update DT bindings with SEC1
This patchseries doesn't apply, at least on top of Herbert's
cryptodev-
On Fri, 20 Feb 2015 12:00:10 -0500
Martin Hicks wrote:
> The newer talitos hardware has support for AES in XTS mode.
Assuming it's the same thing, AES-XCBC gets added with SEC v3.0
h/w. Assuming hw_supports() doesn't already support this algorithm
combination (technically via the mode bit), thi
On Tue, 3 Mar 2015 08:21:33 -0500
Martin Hicks wrote:
> There were multiple loops in a row, for each separate step of the
> initialization of the channels. Simplify to a single loop.
>
> Signed-off-by: Martin Hicks
> ---
Acked-by: Kim Phillips
Kim
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On Tue, 3 Mar 2015 08:21:34 -0500
Martin Hicks wrote:
> This is properly defined in the md5 header file.
>
> Signed-off-by: Martin Hicks
> ---
Acked-by: Kim Phillips
Kim
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On Wed, 4 Mar 2015 20:28:26 +0200
Nicolae Rosia wrote:
> On Wed, Mar 4, 2015 at 7:13 PM, Nicolae Rosia wrote:
> > I'm trying to understand why icv_truncbits is set to 96 for
> > hmac(sha256) in xfrm_algo.c because
> > RFC4868 [1] says that the truncation length for HMAC-SHA256 should be 128.
Se
On Wed, 4 Mar 2015 13:33:22 +0800
yjin wrote:
> On 2015年03月04日 03:31, Kim Phillips wrote:
> > On Tue, 3 Mar 2015 14:50:52 +0800
> > wrote:
> >
> >> - dma_unmap_single(jrdev, ctx->sh_desc_dma, DESC_RNG_LEN,
> >>
On Wed, 4 Mar 2015 11:03:28 +0200
Cristian Stoica wrote:
> On 03/04/2015 06:57 AM, yjin wrote:
> > An alternative is moving the definitions to a ".c" file, but I don't
> > think it will be fundamental different.
> > I know I am fixing a potential error which doesn't exist now, it seems
> > useles
On Tue, 3 Mar 2015 08:21:35 -0500
Martin Hicks wrote:
> The submission count was off by one.
>
> Signed-off-by: Martin Hicks
> ---
sadly, this directly contradicts:
commit 4b24ea971a93f5d0bec34bf7bfd0939f70cfaae6
Author: Vishnu Suresh
Date: Mon Oct 20 21:06:18 2008 +0800
crypto: talit
On Tue, 3 Mar 2015 08:21:37 -0500
Martin Hicks wrote:
> @@ -1170,6 +1237,8 @@ static struct talitos_edesc *talitos_edesc_alloc(struct
> device *dev,
>edesc->dma_len,
>DMA_BIDIRECTIONAL);
>
On Tue, 3 Mar 2015 14:50:51 +0800
wrote:
> This commit is to avoid the below warnings:
>
> drivers/crypto/caam/sg_sw_sec4.h:88:12: warning:
> 'dma_map_sg_chained' defined but not used [-Wunused-function]
> static int dma_map_sg_chained(struct device *dev, struct scatterlist *sg,
> ^
On Tue, 3 Mar 2015 14:50:52 +0800
wrote:
> - dma_unmap_single(jrdev, ctx->sh_desc_dma, DESC_RNG_LEN,
> - DMA_TO_DEVICE);
> + dma_unmap_single(jrdev, ctx->sh_desc_dma,
> + desc_bytes(ctx->sh_desc), DMA_TO_DEVICE);
al
ICV check failures are part of normal operation;
leave user notification up to the higher levels,
as is done in s/w algorithm implementations.
Signed-off-by: Kim Phillips
---
drivers/crypto/caam/error.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers
On Thu, 4 Dec 2014 18:22:45 -0600
Kim Phillips wrote:
> On Thu, 6 Nov 2014 23:17:14 +0800
> Herbert Xu wrote:
>
> > On Thu, Oct 30, 2014 at 06:55:07PM +0200, Tudor Ambarus wrote:
> > > Add AES-GMAC as an IPSec ESP mechanism to provide
> > > data origin authen
On Thu, 6 Nov 2014 23:17:14 +0800
Herbert Xu wrote:
> On Thu, Oct 30, 2014 at 06:55:07PM +0200, Tudor Ambarus wrote:
> > Add AES-GMAC as an IPSec ESP mechanism to provide
> > data origin authentication, but not confidentiality.
> > This method is referred as ENCR_NULL_AUTH_AES_GMAC.
> >
> > Sign
arly circular buffer documentation, and
left it in for the benefit of the doubt. Now it looks to me it's not
necessary, given both sw_idx and tail are just being computed within
a lock, and removing both barriers doesn't affect the compiler
output, so:
Reviewed-by: Kim Phillips
Thanks,
Kim
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On Wed, 5 Nov 2014 11:21:24 +0200
Cristian Stoica wrote:
> The error code returned by hardware is four bits wide with an expected
> zero MSB. A hardware error condition where the error code can get between
> 0x8 and 0xf will trigger an out of bound array access on the error
> message table.
> Thi
On Tue, 4 Nov 2014 10:57:57 +0200
Cristian Stoica wrote:
> Hi Kim,
>
> >> Actually, our static code analyzer did not see this one.
> >
> > ok, so the patch technically isn't fixing anything broken, then.
>
> Are you saying the code isn't broken _because_ a static tool analyser
> did not see an
On Mon, 3 Nov 2014 11:18:36 +0200
Cristian Stoica wrote:
> On 10/31/2014 08:22 PM, Kim Phillips wrote:
> > On Fri, 31 Oct 2014 18:57:33 +0200
> > Cristian Stoica wrote:
> >
> > If this issue was brought up by h/w, the appropriate new error codes
> > should be b
On Fri, 31 Oct 2014 18:57:33 +0200
Cristian Stoica wrote:
> The error code returned by hardware is four bits wide with an expected
> zero MSB. A hardware error condition where the error code can get between
> 0x8 and 0xf will trigger an out of bound array access on the error
> message table.
If
On Fri, 10 Oct 2014 03:47:18 -0500
Ambarus Tudor-Dan-B38632 wrote:
> On Thu, 9 Oct 2014 17:54:09 +0300
> Tudor Ambarus wrote:
> > + /* Galois Counter Mode */
> > + {
> > + .name = "gcm(aes)",
> > + .driver_name = "gcm-aes-caam",
> > + .blocksize = 1,
> > +
On Fri, 10 Oct 2014 05:10:55 -0500
Ambarus Tudor-Dan-B38632 wrote:
> On Thu, 9 Oct 2014 17:54:10 +0300
> Tudor Ambarus wrote:
> > +static int rfc4106_setauthsize(struct crypto_aead *authenc,
> > + unsigned int authsize)
> > +{
> > + struct caam_ctx *ctx = crypto_aead_c
On Thu, 9 Oct 2014 17:54:10 +0300
Tudor Ambarus wrote:
> +static int rfc4106_set_sh_desc(struct crypto_aead *aead)
...
> + /*
> + * Job Descriptor and Shared Descriptors
> + * must all fit into the 64-word Descriptor h/w Buffer
> + */
> + if (DESC_RFC4106_DEC_LEN + DESC_JOB
On Thu, 9 Oct 2014 17:54:09 +0300
Tudor Ambarus wrote:
> + /*
> + * Job Descriptor and Shared Descriptors
> + * must all fit into the 64-word Descriptor h/w Buffer
> + */
> + if (DESC_GCM_DEC_LEN + DESC_JOB_IO_LEN +
> + ctx->enckeylen <= CAAM_DESC_BYTES_MAX)
> +
[adding Sandeep, Horia and netdev]
On Fri, 12 Sep 2014 09:39:12 +0200
Helmut Schaa wrote:
> On Fri, Sep 12, 2014 at 2:49 AM, Kim Phillips
> wrote:
> > On Wed, 10 Sep 2014 10:34:47 +0200
> > Helmut Schaa wrote:
> >
> >> The talitos driver can cause starvat
On Wed, 10 Sep 2014 10:34:47 +0200
Helmut Schaa wrote:
> The talitos driver can cause starvation of other softirqs and as such
> it can also cause rcu stalls like:
...
> Work around this by processing a maximum amount of 16 finished requests
> and rescheduling the done-tasklet if any work is left
On Wed, 3 Sep 2014 12:59:34 +0300
Horia Geantă wrote:
> On 8/16/2014 2:16 PM, Kim Phillips wrote:
> > On Thu, 14 Aug 2014 15:54:22 +0300
> > Horia Geanta wrote:
> >
> >> This patch set adds Run Time Assembler (RTA) SEC descriptor library.
> >> RTA is a r
On Thu, 14 Aug 2014 15:54:22 +0300
Horia Geanta wrote:
> This patch set adds Run Time Assembler (RTA) SEC descriptor library.
> RTA is a replacement for incumbent "inline append".
>
> The library is intended to be a single code base for SEC descriptors creation
> for all Freescale products. This
t; -#define MAX_KEYLEN 56
> +#define MAX_KEYLEN 160
> #define MAX_IVLEN32
this change could use a blurb in the commit message.
Other than that, this series gets my:
Acked-by: Kim Phillips
Thanks!
Kim
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---
> Only compile-tested.
> Ruchika / Kim, please review / test.
Acked-by: Kim Phillips
fwiw, it would be nice if virt_en were a bool...can you also please
start using get_maintainer.pl?
Thanks,
Kim
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On Mon, 21 Jul 2014 10:47:49 +0300
Horia Geantă wrote:
> On 7/19/2014 4:23 AM, Kim Phillips wrote:
> > On Sat, 19 Jul 2014 02:51:30 +0300
> > Horia Geantă wrote:
> >
> >> On 7/19/2014 1:13 AM, Kim Phillips wrote:
> >>> On Fri, 18 Jul 201
On Sat, 19 Jul 2014 02:51:30 +0300
Horia Geantă wrote:
> On 7/19/2014 1:13 AM, Kim Phillips wrote:
> > On Fri, 18 Jul 2014 19:37:17 +0300
> > Horia Geanta wrote:
> >
> >> This patch set adds Run Time Assembler (RTA) SEC descriptor library.
> >>
>
On Fri, 11 Jul 2014 15:34:45 +0300
Horia Geanta wrote:
Hi Horia,
> Enabling DMA-API debugging reveals quite a lot of problems in CAAM module.
> Patches below fix them - tested on P3041DS QorIQ platform. Please apply.
In an attempt to try and test these patches on a t4240qds, I get:
caam ffe300
On Fri, 18 Jul 2014 19:37:17 +0300
Horia Geanta wrote:
> This patch set adds Run Time Assembler (RTA) SEC descriptor library.
>
> The main reason of replacing incumbent "inline append" is
> to have a single code base both for user space and kernel space.
that's orthogonal to what this patchseri
On Thu, 3 Jul 2014 15:07:50 +0300
Cristian Stoica wrote:
> This patch fixes a memory leak that appears when caam_jr module is unloaded.
>
> Cc: # 3.13+
> Signed-off-by: Cristian Stoica
> ---
> drivers/crypto/caam/jr.c | 6 ++
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --g
On Mon, 9 Jun 2014 18:19:41 +0300
Dan Carpenter wrote:
> The FIFOST_CONT_MASK define is cut and pasted twice so we can delete the
> second instance.
>
> Signed-off-by: Dan Carpenter
Acked-by: Kim Phillips
Thanks,
Kim
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On Thu, 12 Jun 2014 04:56:14 -0500
Gupta Ruchika-R66431 wrote:
> > From: Kim Phillips [mailto:kim.phill...@freescale.com]
> > Sent: Thursday, June 12, 2014 4:23 AM
> > > /* Check to see if QI present. If so, enable */
> > > - ctrlpriv->qi_present = !!(rd_reg64(
On Thu, 12 Jun 2014 23:52:06 +0530
Ruchika Gupta wrote:
> Some registers like SECVID, CHAVID, CHA Revision Number,
> CTPR were defined as 64 bit resgisters. The IP provides
> a DWT bit(Double word Transpose) to transpose the two words when
> a double word register is accessed. However setting th
On Tue, 29 Apr 2014 15:34:37 +0530
Ruchika Gupta wrote:
> Few read only registers like CHAVID, CTPR etc were wrongly defined
> as 64 bit registers. This functioned properly on the powerpc platforms.
> However ARM SoC's wouldn't function correctly if these registers
> are defined as 64 bit. So cor
From: Vakul Garg
Re-initialize keys_fit_inline to avoid using its stale encrypt() shared
descriptor value prior to building descriptors for the decrypt() and
givencrypt() cases.
Signed-off-by: Vakul Garg
[reworded commit text, enhanced code readability]
Signed-off-by: Kim Phillips
On Tue, 6 May 2014 23:09:15 -0500
Gupta Ruchika-R66431 wrote:
> Hi Kim,
Hi Ruchika,
> > From: Kim Phillips [mailto:kim.phill...@freescale.com]
> > Sent: Wednesday, May 07, 2014 2:02 AM
> >
> > On Tue, 6 May 2014 05:11:23 -0500
> > Gupta Ruchika-R66431 wrote
On Tue, 6 May 2014 05:11:23 -0500
Gupta Ruchika-R66431 wrote:
> > From: Kim Phillips [mailto:kim.phill...@freescale.com]
> > Sent: Friday, May 02, 2014 2:15 AM
> >
> > On Tue, 29 Apr 2014 15:34:37 +0530
> > Ruchika Gupta wrote:
> >
> > > Few r
On Mon, 5 May 2014 22:39:09 -0500
Garg Vakul-B16394 wrote:
> Hi Kim
Hi Vakul,
> > From: Kim Phillips [mailto:kim.phill...@freescale.com]
> > Sent: Tuesday, May 06, 2014 12:07 AM
> >
> > On Sat, 3 May 2014 06:44:39 -0500
> > Garg Vakul-B16394 wrote
On Sat, 3 May 2014 06:44:39 -0500
Garg Vakul-B16394 wrote:
> > From: Kim Phillips [mailto:kim.phill...@freescale.com]
> > Sent: Saturday, May 03, 2014 5:40 AM
> >
> > On Sun, 27 Apr 2014 11:26:14 -0400
> > Vakul Garg wrote:
> >
> > > @@ -220,6 +220
On Sun, 27 Apr 2014 11:26:14 -0400
Vakul Garg wrote:
> The variable 'keys_fit_inline' is initialised correctly to avoid using
> its stale value while creating shared descriptor for decryption and
> given-iv-encryption.
you mean givencrypt? That's "generate an IV and encrypt".
> @@ -220,6 +220,
On Tue, 29 Apr 2014 15:41:39 +0530
Ruchika Gupta wrote:
> The kernel defines setbits32() and clrbits32() macros only for
> Power-based architectures. This patch modifies the Freescale CAAM
> driver to add macros for use on ARM architectures.
>
> Signed-off-by: Victoria Milhoan
> Signed-off-by:
On Tue, 29 Apr 2014 15:34:37 +0530
Ruchika Gupta wrote:
> Few read only registers like CHAVID, CTPR etc were wrongly defined
> as 64 bit registers. This functioned properly on the powerpc platforms.
> However ARM SoC's wouldn't function correctly if these registers
> are defined as 64 bit.
why
On Wed, 23 Apr 2014 10:20:16 +0200
leroy christophe wrote:
> I'm altering the Freescale Talitos Driver in order to support the SEC1
> security engine, and I have a big issue with the DES test vectors in
> testmgr.h:
>
> The Sec Engine reports key parity error.
>
> Looking at the keys defined
On Tue, 1 Apr 2014 18:12:19 +0200
christophe leroy wrote:
> Le 1 avr. 2014 00:55, "Kim Phillips" a écrit :
> >
> > On Sat, 29 Mar 2014 17:07:43 +
> > christophe leroy wrote:
> >
> > > Hi
> > > Does the talitos driver support mpc 8272 o
On Sat, 29 Mar 2014 17:07:43 +
christophe leroy wrote:
> Hi
> Does the talitos driver support mpc 8272 or does any other driver do ?
none upstream that I know of.
> i see that CONFIG_CRYPTO_DEV_TALITOS is not set in mpc8272ads config, and
> mpc8272ads dts does includeba compatible for fsl,s
would crash immediately.
>
> Signed-off-by: Dan Carpenter
> ---
Meanwhile:
Acked-by: Kim Phillips
Kim
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On Thu, 6 Feb 2014 11:41:28 +0200
Horia Geantă wrote:
> On 2/6/2014 10:27 AM, Alex Porosanu wrote:
> > Signed-off-by: Alex Porosanu
> > ---
> > drivers/crypto/caam/ctrl.c | 36 ++--
> > drivers/crypto/caam/ctrl.h | 2 +-
> > 2 files changed, 11 insertions(+),
On Sat, 21 Sep 2013 14:26:35 +0530
Yashpal Dutta wrote:
> KMap the buffers before copying trailing bytes during hmac into a session
> temporary buffer. This is required if pinned buffer from user-space is send
> during hmac and is safe even if hmac request is generated from within kernel.
it may
>
>
>
> commit 5228f0f79e983c2b39c202c75af901ceb0003fc1
> Author: Kim Phillips
> Date: Fri Jul 15 11:21:38 2011 +0800
>
> crypto: talitos - ensure request ordering within a single tfm
>
> Assign single target channel per tfm in talitos_cra_init
On Thu, 4 Apr 2013 14:38:41 +
"Hsieh, Che-Min" wrote:
> If a driver supports multiple instances of HW crypto engines, the order of
> the request completion from HW can be different from the order of requests
> submitted to different HW. The 2nd request sent out to the 2nd HW instance
> ma
checkstack reports report_deco_status(), report_ccb_status() as
particularly excessive stack users. Move their lookup tables
off the stack and put them in .rodata.
Signed-off-by: Kim Phillips
---
v1 posted here:
http://article.gmane.org/gmane.linux.kernel.cryptoapi/7571
v2: made cha_id_list
commit 2af8f4a "crypto: caam - coccicheck fixes" added error
return values yet neglected to change the type from unsigned.
Signed-off-by: Kim Phillips
---
v1 posted here:
http://article.gmane.org/gmane.linux.kernel.cryptoapi/7664
v2: updated commit text with 'coccicheck f
> ICV is generated by hashing the sequence
> SPI, SeqNum-High, SeqNum-Low, IV, Payload
> instead of
> SPI, SeqNum-Low, IV, Payload, SeqNum-High.
>
> Cc: # 3.8, 3.7
> Reported-by: Chaoxing Lin
> Signed-off-by: Horia Geanta
> ---
Reviewed-by: Kim Phillips
Kim
--
> ICV is generated by hashing the sequence
> SPI, SeqNum-High, SeqNum-Low, IV, Payload
> instead of
> SPI, SeqNum-Low, IV, Payload, SeqNum-High.
>
> Cc: # 3.8, 3.7
> Reported-by: Chaoxing Lin
> Signed-off-by: Horia Geanta
> ---
Reviewed-by: Kim Phillips
Kim
--
On Thu, 14 Mar 2013 12:21:20 +0200
Horia Geantă wrote:
> On 3/12/2013 10:57 PM, Chaoxing Lin wrote:
> > The freescale crypto engine is still capable of doing AES-CBC + HMAC-SHAxxx
> > in one shot.
> > "DESC_HDR_TYPE_IPSEC_ESP" may not able to achieve authencesn.
>
> Correct. And that's why I th
t; drivers do. That would apparently (indirectly) select CRYPTO_HASH2,
> which would enable the ahash functionality this driver uses.
>
> Signed-off-by: Paul Bolle
> ---
Reviewed-by: Kim Phillips
Kim
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On Wed, 6 Feb 2013 17:17:46 +0530
Vakul Garg wrote:
> This change is required for post SEC-5.0 devices which have RNG4. Setting RDB
wrap your commit message text to 75 chars
> in security configuration register allows CAAM to use the "Random Data Buffer"
> to be filled by a single request. The
cc'ing devicetree-discuss. Start using scripts/get_maintainers.pl.
On Wed, 23 Jan 2013 11:04:55 +0530
Vakul Garg wrote:
> +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
> @@ -54,8 +54,13 @@ PROPERTIES
> - compatible
>Usage: required
>Value type:
> - Defini
On Thu, 10 Jan 2013 00:49:23 -0600
Garg Vakul-B16394 wrote:
> > From: Phillips Kim-R1AAHA
> > Sent: Thursday, January 10, 2013 3:16 AM
> > On Sat, 5 Jan 2013 17:14:13 +
> > Garg Vakul-B16394 wrote:
> > > > From: Jussi Kivilinna [mailto:jussi.kivili...@mbnet.fi]
> > > > Sent: Saturday, Januar
authenc(hmac(sha384),cbc(des3_ede))
> (e) authenc(hmac(sha224),cbc(des))
> (f) authenc(hmac(sha384),cbc(des))
>
> Signed-off-by: Vakul Garg
> ---
Reviewed-by: Kim Phillips
Kim
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On Sat, 5 Jan 2013 17:14:13 +
Garg Vakul-B16394 wrote:
> > From: Jussi Kivilinna [mailto:jussi.kivili...@mbnet.fi]
> > Sent: Saturday, January 05, 2013 9:56 PM
> >
> > Quoting Vakul Garg :
> >
> > > This allows to test & run multiple parallel crypto ahash contexts.
> > > Each of the test ve
On Fri, 23 Nov 2012 14:51:08 +0100
leroy christophe wrote:
> Le 26/09/2012 02:47, Kim Phillips a écrit :
> > On Tue, 25 Sep 2012 10:45:17 +0200
> > leroy christophe wrote:
> >
> >> I'm trying to use the Talitos crypto driver with the MPC885
> >> mic
gt;
> > I have some more questions/observations below
> >
> > Le 26/09/2012 02:47, Kim Phillips a écrit :
> >> On Tue, 25 Sep 2012 10:45:17 +0200
> >> leroy christophe wrote:
> >>
> >>> I'm trying to use the Talitos crypto driver with t
On Tue, 25 Sep 2012 10:45:17 +0200
leroy christophe wrote:
> I'm trying to use the Talitos crypto driver with the MPC885
> microcontroller. For the time being, it doesn't work.
yes, they're not exactly compatible...
> The kernel startup blocks at the test of the DES function.
>
> I have added
missing patch version
On Wed, 19 Sep 2012 14:15:11 +0530
Vakul Garg wrote:
> CAAM era retrieval api caam_get_era() currently supports devices upto ERA-4.
> The CAAM era is looked up from a table mapping SECVID register to an ERA
> number.
> Post ERA-6, era can be directly read from register CCB
we need to configure the TRNG to use more clocks per sample
to handle the two back-to-back 64KiB random descriptor requests
on higher frequency P5040s.
Signed-off-by: Kim Phillips
---
fixes booting on the p5040, but since p5040 support isn't in
3.6, this can wait for 3.7.
Also, Herbert,
The 'coccicheck fixes' commit added error return values yet
neglected to change the type from unsigned.
Signed-off-by: Kim Phillips
---
drivers/crypto/caam/caamhash.c | 4 ++--
drivers/crypto/caam/key_gen.c | 2 +-
drivers/crypto/caam/key_gen.h | 2 +-
3 files changed, 4 insert
/caamalg.ko] undefined!
>
> Signed-off-by: Ben Collins
> Cc: Herbert Xu
> Cc: Yuan Kang
Acked-by: Kim Phillips
Kim
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use true/false for bool, fix code alignment, and fix two allocs with
no test.
Signed-off-by: Kim Phillips
---
drivers/crypto/caam/caamalg.c | 16
drivers/crypto/caam/caamhash.c | 4
drivers/crypto/caam/key_gen.c | 4
3 files changed, 16 insertions(+), 8 deletions
checkstack reports report_deco_status(), report_ccb_status() as
particularly excessive stack users. Move error lookup tables
off the stack and put them in .rodata.
Signed-off-by: Kim Phillips
---
drivers/crypto/caam/error.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff
On Mon, 30 Jul 2012 15:56:04 +0800
Herbert Xu wrote:
> On Fri, Jul 13, 2012 at 06:04:23PM -0500, Kim Phillips wrote:
> > commit "crypto: caam - use non-irq versions of spinlocks for job rings"
> > made two bad assumptions:
> >
> > (a) The caam_jr_enque
the entry points and geniv definitions for all aead,
ablkcipher, and hash algorithms are all common; move them to a
single assignment in talitos_alg_alloc().
This assumes it's ok to assign a setkey() on non-hmac algs.
Signed-off-by: Kim Phillips
---
drivers/crypto/talitos.c
lighten driver_algs[] by moving them to talitos_alg_alloc().
Signed-off-by: Kim Phillips
---
these two patches apply on top of all remaining talitos patches -
including XOR support - currently on linux-crypto (i.e., that
haven't been applied to the cryptodev tree).
drivers/crypto/tali
On Wed, 8 Aug 2012 18:46:45 +0300
Horia Geanta wrote:
> Support for ESNs (extended sequence numbers).
> Tested with strongswan on a P2020RDB back-to-back setup.
> Extracted from /etc/ipsec.conf:
> esp=aes-sha1-esn-modp4096!
>
> Signed-off-by: Horia Geanta
> ---
seri
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