On Thu, 12 Jun 2014 23:52:06 +0530 Ruchika Gupta <ruchika.gu...@freescale.com> wrote:
> Some registers like SECVID, CHAVID, CHA Revision Number, > CTPR were defined as 64 bit resgisters. The IP provides > a DWT bit(Double word Transpose) to transpose the two words when > a double word register is accessed. However setting this bit > would also affect the operation of job descriptors as well as > other registers which are truly double word in nature. > So, for the IP to work correctly on big-endian as well as > little-endian SoC's, change is required to access all 32 bit > registers as 32 bit quantities. > > Signed-off-by: Ruchika Gupta <ruchika.gu...@freescale.com> > --- > Changed in v2: > 1. Review comments incorporated only 2 out of 3...see previous version's thread. Also, please start using scripts/get_maintainer.pl. Thanks, Kim -- To unsubscribe from this list: send the line "unsubscribe linux-crypto" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
