[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 4

https://gcc.gnu.org/g:2372ebbb3417b446dfb76bd6390f3a510a357934 commit 2372ebbb3417b446dfb76bd6390f3a510a357934 Author: Pan Li Date: Sun Jun 30 16:48:19 2024 +0800 RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 4 This patch would like to add test cases for the unsigned

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix asm check failure for truncated after SAT_SUB

https://gcc.gnu.org/g:9de4cfd56a65e70bf5f4fa50ed2326a632befef4 commit 9de4cfd56a65e70bf5f4fa50ed2326a632befef4 Author: Pan Li Date: Wed Jul 3 13:17:16 2024 +0800 RISC-V: Fix asm check failure for truncated after SAT_SUB It seems that the asm check is incorrect for truncated after

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add support for Zabha extension

https://gcc.gnu.org/g:0d3084a47182fc04b2cb1fdf4ce240074a953534 commit 0d3084a47182fc04b2cb1fdf4ce240074a953534 Author: Gianluca Guida Date: Tue Jul 2 18:05:14 2024 -0700 RISC-V: Add support for Zabha extension The Zabha extension adds support for subword Zaamo ops. Extens

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1

https://gcc.gnu.org/g:8ab0fc4d6a5a5d458f74e7d58ead9f07aa3444fc commit 8ab0fc4d6a5a5d458f74e7d58ead9f07aa3444fc Author: Pan Li Date: Sun Jun 30 16:03:41 2024 +0800 RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1 This patch would like to add test cases for the unsigned

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Describe -march behavior for dependent extensions

https://gcc.gnu.org/g:db238f5ae70cb461f0f9d7309208c6b36616b547 commit db238f5ae70cb461f0f9d7309208c6b36616b547 Author: Palmer Dabbelt Date: Tue Jul 2 18:20:39 2024 -0700 RISC-V: Describe -march behavior for dependent extensions gcc/ChangeLog: * doc/invoke.texi: De

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed][RISC-V] Fix test expectations after recent late-combine changes

https://gcc.gnu.org/g:cb9f4cb1077bf480b1bb766cde024207f406d69a commit cb9f4cb1077bf480b1bb766cde024207f406d69a Author: Jeff Law Date: Thu Jul 4 09:25:20 2024 -0600 [committed][RISC-V] Fix test expectations after recent late-combine changes With the recent DCE related adjustment to

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed][v3][RISC-V] Handle bit manipulation of SImode values

https://gcc.gnu.org/g:49d192288ec101216cd22b0f701b04f6d99c3821 commit 49d192288ec101216cd22b0f701b04f6d99c3821 Author: Jeff Law Date: Sat Jul 6 12:57:59 2024 -0600 [to-be-committed][v3][RISC-V] Handle bit manipulation of SImode values Last patch in this round of bitmanip work...

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement .SAT_TRUNC for vector unsigned int

https://gcc.gnu.org/g:34f337a787ebcefc68b18734ae0ab72a1a8d0a22 commit 34f337a787ebcefc68b18734ae0ab72a1a8d0a22 Author: Pan Li Date: Fri Jul 5 09:02:47 2024 +0800 RISC-V: Implement .SAT_TRUNC for vector unsigned int This patch would like to implement the .SAT_TRUNC for the RISC-V

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed][RISC-V][V3] DCE analysis for extension elimination

https://gcc.gnu.org/g:3837405f64cef75f61c383df6c57c9442e71402c commit 3837405f64cef75f61c383df6c57c9442e71402c Author: Jeff Law Date: Mon Jul 8 17:06:55 2024 -0600 [to-be-committed][RISC-V][V3] DCE analysis for extension elimination The pre-commit testing showed that making ext-dc

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 1

https://gcc.gnu.org/g:c75ea600c62ad1b735f7baa8fcef3d96a4615fec commit c75ea600c62ad1b735f7baa8fcef3d96a4615fec Author: Pan Li Date: Mon Jul 8 20:31:31 2024 +0800 RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 1 After the middle-end supported the vector mode of .SAT_AD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 2

https://gcc.gnu.org/g:6add49f7ac9bca9e04f04a66d4e46db43618ef71 commit 6add49f7ac9bca9e04f04a66d4e46db43618ef71 Author: Pan Li Date: Mon Jul 8 21:58:59 2024 +0800 RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 2 After the middle-end supported the vector mode of .SAT_AD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add support for B standard extension

https://gcc.gnu.org/g:03d27d8b26649675e4258248db98b58f493a6d0d commit 03d27d8b26649675e4258248db98b58f493a6d0d Author: Edwin Lu Date: Wed Jul 10 09:44:48 2024 -0700 RISC-V: Add support for B standard extension This patch adds support for recognizing the B standard extension to be

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Update testsuite to use b

https://gcc.gnu.org/g:bcb9efbd9bb2e90115f65348f47ea2721ff53855 commit bcb9efbd9bb2e90115f65348f47ea2721ff53855 Author: Edwin Lu Date: Wed Jul 3 17:17:27 2024 -0700 RISC-V: Update testsuite to use b Update all instances of zba_zbb_zbs in the testsuite to use b instead gcc/

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: c implies zca, and conditionally zcf & zcd

https://gcc.gnu.org/g:921baffaadbe71518d881da39f9d1bbcdcc31509 commit 921baffaadbe71518d881da39f9d1bbcdcc31509 Author: Fei Gao Date: Wed Jul 10 10:12:02 2024 + RISC-V: c implies zca, and conditionally zcf & zcd According to Zc-1.0.4-3.pdf from https://github.com/riscvarch

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for vector .SAT_SUB in zip benchmark

https://gcc.gnu.org/g:9996d074b720b565e043792070cefe84a4572ef1 commit 9996d074b720b565e043792070cefe84a4572ef1 Author: Pan Li Date: Thu Jul 11 15:54:32 2024 +0800 RISC-V: Add testcases for vector .SAT_SUB in zip benchmark This patch would like to add the test cases for the vector

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Eliminate unnecessary sign extension after inlined str[n]cmp

https://gcc.gnu.org/g:2360e1573b25467a62ed84a478f33e488230ad07 commit 2360e1573b25467a62ed84a478f33e488230ad07 Author: Jeff Law Date: Thu Jul 11 12:05:56 2024 -0600 [to-be-committed,RISC-V] Eliminate unnecessary sign extension after inlined str[n]cmp This patch eliminates an unne

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add SiFive extensions, xsfvcp and xsfcease

https://gcc.gnu.org/g:dd3171eebd56f22cf06afbc9fbe992709d41965e commit dd3171eebd56f22cf06afbc9fbe992709d41965e Author: Kito Cheng Date: Tue Jul 9 15:50:57 2024 +0800 RISC-V: Add SiFive extensions, xsfvcp and xsfcease We have already upstreamed these extensions into binutils, and n

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Disable misaligned vector access in hook riscv_slow_unaligned_access[PR115862]

https://gcc.gnu.org/g:493983818e91105cf1b48cc30865ff218a73223d commit 493983818e91105cf1b48cc30865ff218a73223d Author: xuli Date: Thu Jul 11 04:29:11 2024 + RISC-V: Disable misaligned vector access in hook riscv_slow_unaligned_access[PR115862] The reason is that in the follow

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V] Avoid unnecessary sign extension after memcmp

https://gcc.gnu.org/g:587dbc1ee0c2bc56dd1edfc4b3a1f8dc9abf2760 commit 587dbc1ee0c2bc56dd1edfc4b3a1f8dc9abf2760 Author: Jeff Law Date: Fri Jul 12 07:53:41 2024 -0600 [RISC-V] Avoid unnecessary sign extension after memcmp Similar to the str[n]cmp work, this adjusts the block compare

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PR rtl-optimization/115876] Fix one of two ubsan reported issues in new ext-dce.cc code

https://gcc.gnu.org/g:d38da39f34be9914f25b0db1e8054a74a8f7abe0 commit d38da39f34be9914f25b0db1e8054a74a8f7abe0 Author: Jeff Law Date: Fri Jul 12 13:11:33 2024 -0600 [PR rtl-optimization/115876] Fix one of two ubsan reported issues in new ext-dce.cc code David Binderman did a boot

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add vector type of BFloat16 format

https://gcc.gnu.org/g:27cd96d5b1f12955f01f3a104d6701cb48bb20f9 commit 27cd96d5b1f12955f01f3a104d6701cb48bb20f9 Author: Feng Wang Date: Thu Jun 13 00:32:14 2024 + RISC-V: Add vector type of BFloat16 format v3: Rebase v2: Rebase The vector type of BFloat16 format is adde

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add Zvfbfmin and Zvfbfwma intrinsic

https://gcc.gnu.org/g:21c85f996289427e61ae22eec8061620cc562d8c commit 21c85f996289427e61ae22eec8061620cc562d8c Author: Feng Wang Date: Mon Jun 17 01:59:57 2024 + RISC-V: Add Zvfbfmin and Zvfbfwma intrinsic v3: Modify warning message in riscv.cc v2: Rebase Accroding to

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add md files for vector BFloat16

https://gcc.gnu.org/g:ae8af3ab0ae12793d35d37d9744f3cd0ceaa98b3 commit ae8af3ab0ae12793d35d37d9744f3cd0ceaa98b3 Author: Feng Wang Date: Tue Jun 18 06:13:35 2024 + RISC-V: Add md files for vector BFloat16 V3: Add Bfloat16 vector insn in generic-vector-ooo.md v2: Rebase A

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement locality for __builtin_prefetch

https://gcc.gnu.org/g:5975c3c8d167f4e0f41893ed90334a1aaef91441 commit 5975c3c8d167f4e0f41893ed90334a1aaef91441 Author: Monk Chiang Date: Thu Jul 6 14:05:17 2023 +0800 RISC-V: Implement locality for __builtin_prefetch The patch add the Zihintntl instructions in the prefetch pattern

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix testcase for vector .SAT_SUB in zip benchmark

https://gcc.gnu.org/g:25e37abccfcdd4604e5d917d98d537aa33a53a82 commit 25e37abccfcdd4604e5d917d98d537aa33a53a82 Author: Edwin Lu Date: Fri Jul 12 11:31:16 2024 -0700 RISC-V: Fix testcase for vector .SAT_SUB in zip benchmark The following testcase was not properly testing anything d

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Attribute parser: Use alloca() instead of new + std::unique_ptr

https://gcc.gnu.org/g:894c444b23ca83d8333cc0a475545099c2ffa8d4 commit 894c444b23ca83d8333cc0a475545099c2ffa8d4 Author: Christoph Müllner Date: Fri Jul 5 04:48:15 2024 +0200 RISC-V: Attribute parser: Use alloca() instead of new + std::unique_ptr Allocating an object on the heap wit

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Rewrite target attribute handling

https://gcc.gnu.org/g:9fb79576bb1a0a31e31a50436e99a9507021aed4 commit 9fb79576bb1a0a31e31a50436e99a9507021aed4 Author: Christoph Müllner Date: Sat Jun 22 21:59:04 2024 +0200 RISC-V: Rewrite target attribute handling The target-arch attribute handling in RISC-V is only a few months

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Allow adding enabled extension via target arch attributes

https://gcc.gnu.org/g:0315d0f04f07ff89c6af32212f9f6bdc0a94d21d commit 0315d0f04f07ff89c6af32212f9f6bdc0a94d21d Author: Christoph Müllner Date: Sat Jul 6 17:03:18 2024 +0200 RISC-V: Allow adding enabled extension via target arch attributes The set of enabled extensions can be exten

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Revert "RISC-V: Attribute parser: Use alloca() instead of new + std::unique_ptr"

https://gcc.gnu.org/g:820041b0a5f4e6c3ecc8cabf16a409fe37a4b29d commit 820041b0a5f4e6c3ecc8cabf16a409fe37a4b29d Author: Christoph Müllner Date: Mon Jul 15 23:42:39 2024 +0200 Revert "RISC-V: Attribute parser: Use alloca() instead of new + std::unique_ptr" This reverts commit 5040c

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Fix liveness computation for shift/rotate counts in ext-dce

https://gcc.gnu.org/g:6e008e50050b6bcb0706f9f9e305fa17c4265142 commit 6e008e50050b6bcb0706f9f9e305fa17c4265142 Author: Jeff Law Date: Mon Jul 15 18:15:33 2024 -0600 Fix liveness computation for shift/rotate counts in ext-dce So as I've noted before I believe the control flow in ex

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Add debug counter for ext_dce

https://gcc.gnu.org/g:0af6332920c401a77feee16dcad16015b4f8e065 commit 0af6332920c401a77feee16dcad16015b4f8e065 Author: Andrew Pinski Date: Tue Jul 16 09:53:20 2024 -0700 Add debug counter for ext_dce Like r15-1610-gb6215065a5b143 (which adds one for late_combine), adding one f

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix testcase missing arch attribute

https://gcc.gnu.org/g:f2048cdfc401782a93585cf2ae9383941b8bb67b commit f2048cdfc401782a93585cf2ae9383941b8bb67b Author: Edwin Lu Date: Tue Jul 16 17:43:45 2024 -0700 RISC-V: Fix testcase missing arch attribute The C + F extention implies the zcf extension on rv32. Add missing zcf

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PR rtl-optimization/115877] Fix livein computation for ext-dce

https://gcc.gnu.org/g:16ec69161c3a3537076cea467e3622bb4a2550d0 commit 16ec69161c3a3537076cea467e3622bb4a2550d0 Author: Jeff Law Date: Sun Jul 21 07:36:37 2024 -0600 [PR rtl-optimization/115877] Fix livein computation for ext-dce So I'm not yet sure how I'm going to break everythin

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PR rtl-optimization/115877][2/n] Improve liveness computation for constant initialization

https://gcc.gnu.org/g:1a05bff037dd32f73e1135d4ba2737167104c528 commit 1a05bff037dd32f73e1135d4ba2737167104c528 Author: Jeff Law Date: Sun Jul 21 08:41:28 2024 -0600 [PR rtl-optimization/115877][2/n] Improve liveness computation for constant initialization While debugging pr115877

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Rearrange the test helper files for vector .SAT_*

https://gcc.gnu.org/g:cb6bdd5811aed672c32b92263e8c2c3cd24bd880 commit cb6bdd5811aed672c32b92263e8c2c3cd24bd880 Author: Pan Li Date: Sat Jul 20 10:43:44 2024 +0800 RISC-V: Rearrange the test helper files for vector .SAT_* Rearrange the test help header files, as well as align the

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [NFC][PR rtl-optimization/115877] Avoid setting irrelevant bit groups as live in ext-dce

https://gcc.gnu.org/g:7c7b6fda23363220c874786ea0800b24a76fcd10 commit 7c7b6fda23363220c874786ea0800b24a76fcd10 Author: Jeff Law Date: Mon Jul 22 08:45:10 2024 -0600 [NFC][PR rtl-optimization/115877] Avoid setting irrelevant bit groups as live in ext-dce Another patch to refine li

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [4/n][PR rtl-optimization/115877] Correct SUBREG handling in a destination

https://gcc.gnu.org/g:0d84f3d3150a72632293b3de0e2b97531615bd00 commit 0d84f3d3150a72632293b3de0e2b97531615bd00 Author: Jeff Law Date: Mon Jul 22 10:11:57 2024 -0600 [4/n][PR rtl-optimization/115877] Correct SUBREG handling in a destination If we encounter something during SET hand

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement the .SAT_TRUNC for scalar

https://gcc.gnu.org/g:eb6ee8d59d7000e2083a6be84ed2d34fd5b60e3d commit eb6ee8d59d7000e2083a6be84ed2d34fd5b60e3d Author: Pan Li Date: Mon Jul 1 16:36:35 2024 +0800 RISC-V: Implement the .SAT_TRUNC for scalar This patch would like to implement the simple .SAT_TRUNC pattern in the

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [5/n][PR rtl-optimization/115877] Fix handling of input/output operands

https://gcc.gnu.org/g:bb7633d7de5bd5a0227cae624a7ee1a97a89c28a commit bb7633d7de5bd5a0227cae624a7ee1a97a89c28a Author: Jeff Law Date: Mon Jul 22 21:48:28 2024 -0600 [5/n][PR rtl-optimization/115877] Fix handling of input/output operands So in this patch we're correcting a failure

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix snafu in SI mode splitters patch

https://gcc.gnu.org/g:bb13ddff10923828389cf21cdb4643aa6225b37c commit bb13ddff10923828389cf21cdb4643aa6225b37c Author: Vineet Gupta Date: Tue Jul 23 15:12:11 2024 -0700 RISC-V: Fix snafu in SI mode splitters patch SPEC2017 perlbench for RISC-V was broke as runtime output mismatch

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PR rtl-optimization/115877][6/n] Add testcase from pr115877

https://gcc.gnu.org/g:b95ba68bf28a28ec50c3fa96b1587cc9a97af4b9 commit b95ba68bf28a28ec50c3fa96b1587cc9a97af4b9 Author: Jeff Law Date: Tue Jul 23 19:11:04 2024 -0600 [PR rtl-optimization/115877][6/n] Add testcase from pr115877 This just adds the testcase from pr115877. It's workin

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [rtl-optimization/116037] Explicitly track if a destination was skipped in ext-dce

https://gcc.gnu.org/g:ecbda5a53e691ce963e82aff354f1a43df30d762 commit ecbda5a53e691ce963e82aff354f1a43df30d762 Author: Jeff Law Date: Wed Jul 24 11:16:26 2024 -0600 [rtl-optimization/116037] Explicitly track if a destination was skipped in ext-dce So this has been in the hopper s

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Allow LICM hoist POLY_INT configuration code sequence

https://gcc.gnu.org/g:78e0cd7d2e7f3a09d3ce08a407d91d16e9877246 commit 78e0cd7d2e7f3a09d3ce08a407d91d16e9877246 Author: Juzhe-Zhong Date: Thu Feb 1 23:45:50 2024 +0800 RISC-V: Allow LICM hoist POLY_INT configuration code sequence Realize in recent benchmark evaluation (coremark-pro

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Error early with V and no M extension.

https://gcc.gnu.org/g:13370bdcaf62a62b59845f9c07c942df7c3a8bd3 commit 13370bdcaf62a62b59845f9c07c942df7c3a8bd3 Author: Robin Dapp Date: Wed Jul 24 09:08:00 2024 +0200 RISC-V: Error early with V and no M extension. For calculating the value of a poly_int at runtime we use a mul

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] Trivial testcase adjustment

https://gcc.gnu.org/g:16d1997090340cd587c85450983bf545245dc5bf commit 16d1997090340cd587c85450983bf545245dc5bf Author: Jeff Law Date: Thu Jul 25 08:42:04 2024 -0600 [committed] Trivial testcase adjustment I made pr116037.c dependent on int32 just based on the constants used witho

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PR rtl-optimization/116039] Fix life computation for promoted subregs

https://gcc.gnu.org/g:7d226394382ff284f8c24cbbf6a677023b72111d commit 7d226394382ff284f8c24cbbf6a677023b72111d Author: Jeff Law Date: Thu Jul 25 12:32:28 2024 -0600 [PR rtl-optimization/116039] Fix life computation for promoted subregs So this turned out to be a neat little test a

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Work around bare apostrophe in error string.

https://gcc.gnu.org/g:37cbd2160d01bea81623f1ca506b731ac0f36bbd commit 37cbd2160d01bea81623f1ca506b731ac0f36bbd Author: Robin Dapp Date: Fri Jul 26 12:58:38 2024 +0200 RISC-V: Work around bare apostrophe in error string. An unquoted apostrophe slipped through when testing the recen

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V][target/116085] Fix rv64 minmax extension avoidance splitter

https://gcc.gnu.org/g:ed6d11c16d69b1cf388bfa6dbc00fa3b34ade969 commit ed6d11c16d69b1cf388bfa6dbc00fa3b34ade969 Author: Jeff Law Date: Fri Jul 26 17:30:08 2024 -0600 [RISC-V][target/116085] Fix rv64 minmax extension avoidance splitter A patch introduced a pattern to avoid unnecessa

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [target/116104] Fix test guarding UINTVAL to extract shift count

https://gcc.gnu.org/g:6ca3dabccff3d3cb8ea1a67be38373eebca521c4 commit 6ca3dabccff3d3cb8ea1a67be38373eebca521c4 Author: Jeff Law Date: Mon Jul 29 16:17:25 2024 -0600 [target/116104] Fix test guarding UINTVAL to extract shift count Minor oversight in the ext-dce bits. If the shift

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Remove configure check for zabha

https://gcc.gnu.org/g:b2df229aa9c1b5a9fb77c23456903cf911c5f838 commit b2df229aa9c1b5a9fb77c23456903cf911c5f838 Author: Patrick O'Neill Date: Mon Jul 29 19:52:02 2024 -0700 RISC-V: Remove configure check for zabha This patch removes the zabha configure check since it's not a breaki

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Take Xmode instead of Pmode for ussub expanding

https://gcc.gnu.org/g:6bf3d45cb3d7f54412fd17b7f9452e7ec52d7adf commit 6bf3d45cb3d7f54412fd17b7f9452e7ec52d7adf Author: Pan Li Date: Tue Jul 30 13:56:40 2024 +0800 RISC-V: Take Xmode instead of Pmode for ussub expanding The Pmode is designed for pointer, thus leverage the Xmode in

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add basic support for the Zacas extension

https://gcc.gnu.org/g:cbaa7b2663e48ec9fafcad634a8e06c2aa1a32d0 commit cbaa7b2663e48ec9fafcad634a8e06c2aa1a32d0 Author: Gianluca Guida Date: Mon Jul 29 15:13:46 2024 -0700 RISC-V: Add basic support for the Zacas extension This patch adds support for amocas.{b|h|w|d}. Support for am

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add configure check for B extention support

https://gcc.gnu.org/g:463bd569ca686a364c0c3442b623759353d84d2f commit 463bd569ca686a364c0c3442b623759353d84d2f Author: Edwin Lu Date: Wed Jul 24 16:37:18 2024 -0700 RISC-V: Add configure check for B extention support Binutils 2.42 and before don't recognize the b extension in the

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PR rtl-optimization/116136] Fix previously latent SUBREG simplification bug

https://gcc.gnu.org/g:0476f5316e781a1ea0d7ef91ed654358f4bccd80 commit 0476f5316e781a1ea0d7ef91ed654358f4bccd80 Author: Jeff Law Date: Wed Jul 31 10:15:01 2024 -0600 [PR rtl-optimization/116136] Fix previously latent SUBREG simplification bug This fixes a testsuite regression seen

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [target/116104] Fix more rtl-checking failures in ext-dce

https://gcc.gnu.org/g:9bdf6995bf4069c2e317b0490c9afa6302e8a037 commit 9bdf6995bf4069c2e317b0490c9afa6302e8a037 Author: Jeff Law Date: Wed Jul 31 11:30:27 2024 -0600 [target/116104] Fix more rtl-checking failures in ext-dce More enable-rtl-checking fixes for ext-dce. Very similar

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: NFC: Do not use zicond for pr105314 testcases

https://gcc.gnu.org/g:b6a1ecda25fc90724585f94eb618e7578722ea83 commit b6a1ecda25fc90724585f94eb618e7578722ea83 Author: Xiao Zeng Date: Thu Jul 25 09:50:03 2024 +0800 RISC-V: NFC: Do not use zicond for pr105314 testcases gcc/testsuite/ChangeLog: * gcc.target/riscv/

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Correct mode_idx attribute for viwalu wx variants [PR116149].

https://gcc.gnu.org/g:b870cb81038f703c970ce4eb7c70991f544405b0 commit b870cb81038f703c970ce4eb7c70991f544405b0 Author: Robin Dapp Date: Wed Jul 31 16:54:03 2024 +0200 RISC-V: Correct mode_idx attribute for viwalu wx variants [PR116149]. In PR116149 we choose a wrong vector length

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Improve length attributes for atomic insn sequences

https://gcc.gnu.org/g:11967b054b91d58e8555886664ae91603032c14d commit 11967b054b91d58e8555886664ae91603032c14d Author: Patrick O'Neill Date: Thu Aug 1 20:27:52 2024 -0700 RISC-V: Improve length attributes for atomic insn sequences gcc/ChangeLog: * config/riscv/syn

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] testsuite: Add RISC-V to targets not xfailing gcc.dg/attr-alloc_size-11.c:50, 51.

https://gcc.gnu.org/g:b9820a4a0d683a9b57ab72f7f4e60deb0976513e commit b9820a4a0d683a9b57ab72f7f4e60deb0976513e Author: Jiawei Date: Mon Aug 5 20:15:59 2024 +0800 testsuite: Add RISC-V to targets not xfailing gcc.dg/attr-alloc_size-11.c:50,51. The test has been observed to pass on

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Reject 'd' extension with ILP32E ABI

https://gcc.gnu.org/g:5e106d5552f11a16a83f8e48852dc3803b010c11 commit 5e106d5552f11a16a83f8e48852dc3803b010c11 Author: Patrick O'Neill Date: Tue Jul 30 14:28:23 2024 -0700 RISC-V: Reject 'd' extension with ILP32E ABI Also add a testcase for -mabi=lp64d where 'd' is required.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add deprecation warning to LP64E abi

https://gcc.gnu.org/g:6c244049d986b95658006b265b79ac014b325cbc commit 6c244049d986b95658006b265b79ac014b325cbc Author: Patrick O'Neill Date: Tue Jul 30 17:32:09 2024 -0700 RISC-V: Add deprecation warning to LP64E abi gcc/ChangeLog: PR target/116152 * c

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix format-diag warning from improperly formatted url

https://gcc.gnu.org/g:a20c435f8158401e56339bbdfe4c2b5d60ebed96 commit a20c435f8158401e56339bbdfe4c2b5d60ebed96 Author: Patrick O'Neill Date: Tue Aug 6 08:16:26 2024 -0700 RISC-V: Fix format-diag warning from improperly formatted url gcc/ChangeLog: PR target/116152

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix comment typos

https://gcc.gnu.org/g:69ce456669e1f1549705197cca46e4fd47f509fa commit 69ce456669e1f1549705197cca46e4fd47f509fa Author: Patrick O'Neill Date: Mon Aug 5 14:13:12 2024 -0700 RISC-V: Fix comment typos This fixes most of the typos I found when reading various parts of the RISC-V b

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix typos in code

https://gcc.gnu.org/g:f8512afeda441a4469002db034bbe6dfaf25a5ce commit f8512afeda441a4469002db034bbe6dfaf25a5ce Author: Patrick O'Neill Date: Mon Aug 5 14:19:58 2024 -0700 RISC-V: Fix typos in code This fixes typos in function names and executed code. gcc/ChangeLog:

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Update .SAT_TRUNC dump check due to middle-end change

https://gcc.gnu.org/g:7982b3fb96a0187466024f4ae22f5eb60106b2ee commit 7982b3fb96a0187466024f4ae22f5eb60106b2ee Author: Pan Li Date: Mon Aug 5 16:01:11 2024 +0800 RISC-V: Update .SAT_TRUNC dump check due to middle-end change Due to recent middle-end change, update the .SAT_TRUNC ex

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Minimal support for Zimop extension.

https://gcc.gnu.org/g:16a39f8b7f4192ddeff4efd2b9131adb6352b071 commit 16a39f8b7f4192ddeff4efd2b9131adb6352b071 Author: Jiawei Date: Fri Aug 2 23:23:14 2024 +0800 RISC-V: Minimal support for Zimop extension. This patch support Zimop and Zcmop extension[1].To enable GCC to recognize

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Fix Wstringop-overflow-47.c warning in RISC-V target.

https://gcc.gnu.org/g:d18d1a744832cb6deda2271c6ea9ce39d7b7f672 commit d18d1a744832cb6deda2271c6ea9ce39d7b7f672 Author: Jiawei Date: Tue Jul 16 08:06:25 2024 +0800 Fix Wstringop-overflow-47.c warning in RISC-V target. Update warning test info for RISC-V target, compared on godbolt:

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Rearrange SLP nodes with duplicate statements [PR98138]

https://gcc.gnu.org/g:184712c1c6bd5d46c37bba76996e1f3f6b343389 commit 184712c1c6bd5d46c37bba76996e1f3f6b343389 Author: Manolis Tsamis Date: Tue Jun 25 08:00:04 2024 -0700 Rearrange SLP nodes with duplicate statements [PR98138] This change checks when a two_operators SLP node has m

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Delete duplicate '#define RISCV_DWARF_VLENB'

https://gcc.gnu.org/g:05611fbd80acad68fca9ce7f951977699b27d20b commit 05611fbd80acad68fca9ce7f951977699b27d20b Author: Jin Ma Date: Thu Aug 8 07:49:51 2024 -0600 RISC-V: Delete duplicate '#define RISCV_DWARF_VLENB' gcc/ChangeLog: * config/riscv/riscv.h (RISCV_DWAR

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V][PR target/116240] Ensure object is a comparison before extracting arguments

https://gcc.gnu.org/g:616f63ee647e61d3cfb25ecf68c50ecbef364828 commit 616f63ee647e61d3cfb25ecf68c50ecbef364828 Author: Jeff Law Date: Thu Aug 8 07:42:26 2024 -0600 [RISC-V][PR target/116240] Ensure object is a comparison before extracting arguments This was supposed to go out the

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: testsuite: xtheadfmemidx: Rename test and add similar Zfa test

https://gcc.gnu.org/g:fef123664d31ed2ccb29693a8345a72e209da6c4 commit fef123664d31ed2ccb29693a8345a72e209da6c4 Author: Christoph Müllner Date: Tue Aug 6 07:24:07 2024 +0200 RISC-V: testsuite: xtheadfmemidx: Rename test and add similar Zfa test Test file xtheadfmemidx-medany.c has

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: xthead(f)memidx: Eliminate optimization patterns

https://gcc.gnu.org/g:c2fbe69dbc0c7ef43ad3d99122f0998be89fcb33 commit c2fbe69dbc0c7ef43ad3d99122f0998be89fcb33 Author: Christoph Müllner Date: Tue Jul 30 13:10:59 2024 +0200 RISC-V: xthead(f)memidx: Eliminate optimization patterns We have a huge amount of optimization patterns (in

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: rv32/DF: Prevent 2 SImode loads using XTheadMemIdx

https://gcc.gnu.org/g:a9e84ce68bf3779e5bbc643cfab457803f7b5ad7 commit a9e84ce68bf3779e5bbc643cfab457803f7b5ad7 Author: Christoph Müllner Date: Tue Aug 6 06:48:59 2024 +0200 RISC-V: rv32/DF: Prevent 2 SImode loads using XTheadMemIdx When enabling XTheadFmv/Zfa and XThead(F)MemIdx,

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Small stack tie changes

https://gcc.gnu.org/g:49000f578de1ac20872083e19f709cf41b4a81a7 commit 49000f578de1ac20872083e19f709cf41b4a81a7 Author: Raphael Moreira Zinsly Date: Mon Jul 22 11:23:12 2024 -0300 RISC-V: Small stack tie changes Enable the register used by riscv_emit_stack_tie () to be passed as

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Move riscv_v_adjust_scalable_frame

https://gcc.gnu.org/g:fec211cf435acc4f3ebc32c59314c2816291ea96 commit fec211cf435acc4f3ebc32c59314c2816291ea96 Author: Raphael Moreira Zinsly Date: Mon Jul 22 11:23:17 2024 -0300 RISC-V: Move riscv_v_adjust_scalable_frame Move riscv_v_adjust_scalable_frame () in preparation for th

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Stack-clash protection implemention

https://gcc.gnu.org/g:7f6b6a5710258a720d2d35d14c30877b729b4833 commit 7f6b6a5710258a720d2d35d14c30877b729b4833 Author: Raphael Moreira Zinsly Date: Mon Jul 22 11:23:20 2024 -0300 RISC-V: Stack-clash protection implemention This implements stack-clash protection for riscv, with

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add support to vector stack-clash protection

https://gcc.gnu.org/g:9673f136d09980bbc7be4e3e82fec1ef37652ea0 commit 9673f136d09980bbc7be4e3e82fec1ef37652ea0 Author: Raphael Moreira Zinsly Date: Mon Jul 22 11:23:23 2024 -0300 RISC-V: Add support to vector stack-clash protection Adds basic support to vector stack-clash protecti

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Enable stack clash in alloca

https://gcc.gnu.org/g:8eced564ddf62282cd2737a7b3487088fc32eff4 commit 8eced564ddf62282cd2737a7b3487088fc32eff4 Author: Raphael Moreira Zinsly Date: Mon Jul 22 11:23:27 2024 -0300 RISC-V: Enable stack clash in alloca Add the TARGET_STACK_CLASH_PROTECTION_ALLOCA_PROBE_RANGE to riscv

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V][PR target/116283] Fix split code for recent Zbs improvements with masked bit positions

https://gcc.gnu.org/g:d0d826c509e0cccadba399eaa57f8d63a51178c5 commit d0d826c509e0cccadba399eaa57f8d63a51178c5 Author: Jeff Law Date: Fri Aug 9 17:46:01 2024 -0600 [RISC-V][PR target/116283] Fix split code for recent Zbs improvements with masked bit positions So Patrick's fuzzer

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix non-obvious comment typos

https://gcc.gnu.org/g:983da7ad96ff0920ceb3c439a29fdbcf4512fbae commit 983da7ad96ff0920ceb3c439a29fdbcf4512fbae Author: Patrick O'Neill Date: Mon Aug 5 15:29:33 2024 -0700 RISC-V: Fix non-obvious comment typos This fixes the remainder of the typos I found when reading various parts

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] genoutput: Accelerate the place_operands function.

https://gcc.gnu.org/g:5433bd714737a9b18b54f3579806af2c1f98656d commit 5433bd714737a9b18b54f3579806af2c1f98656d Author: Xianmiao Qu Date: Wed May 22 15:25:16 2024 +0800 genoutput: Accelerate the place_operands function. With the increase in the number of modes and patterns for some

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: use fclass insns to implement isfinite, isnormal and isinf builtins

https://gcc.gnu.org/g:7192fa62bb919ca72168af1c31a95ebb6cbcfff6 commit 7192fa62bb919ca72168af1c31a95ebb6cbcfff6 Author: Vineet Gupta Date: Thu Aug 15 09:24:27 2024 -0700 RISC-V: use fclass insns to implement isfinite,isnormal and isinf builtins Currently these builtins use float co

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Partial: Just the testsuite bits...

https://gcc.gnu.org/g:84684236ca332f9d4732c9d6c8a892ea058d61a1 commit 84684236ca332f9d4732c9d6c8a892ea058d61a1 Author: Pan Li Date: Tue Aug 6 20:59:37 2024 +0800 Partial: Just the testsuite bits... Vect: Make sure the lhs type of .SAT_TRUNC has its mode precision [PR116202]

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Restrict pr116202-run-1.c test to riscv_v target

https://gcc.gnu.org/g:aa312daf3cf0333d369f9a9abaf5b356881cad0e commit aa312daf3cf0333d369f9a9abaf5b356881cad0e Author: Mark Wielaard Date: Mon Aug 12 22:25:42 2024 +0200 Restrict pr116202-run-1.c test to riscv_v target The testcase uses -march=rv64gcv and dg-do run, so should be

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix missing abi arg in test

https://gcc.gnu.org/g:48816efb27d1ed055eebc41fac543d183784f85e commit 48816efb27d1ed055eebc41fac543d183784f85e Author: Edwin Lu Date: Wed Aug 7 10:34:10 2024 -0700 RISC-V: Fix missing abi arg in test The following test was failing when building on 32 bit targets due to not ove

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] testsuite: fix dg-add-options vs. dg-options ordering

https://gcc.gnu.org/g:d9c50df2fcbf50b078a31c0d876a68b25b0f4d4a commit d9c50df2fcbf50b078a31c0d876a68b25b0f4d4a Author: Sam James Date: Sat Jul 27 00:31:54 2024 +0100 testsuite: fix dg-add-options vs. dg-options ordering Per gccint, dg-add-options must be placed after all dg-option

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Manual application of riscv specific changes from:

https://gcc.gnu.org/g:0c66fc473a560e3cf87b07568044aec60dfad0a4 commit 0c66fc473a560e3cf87b07568044aec60dfad0a4 Author: Jeff Law Date: Fri Aug 16 13:24:27 2024 -0600 Manual application of riscv specific changes from: commit 2e662dedf84aa23fdff7bceca040432bf9f1ab72 Author: Sam J

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Manual applicatoin of riscv specific changes from:

https://gcc.gnu.org/g:e6b322cc9a99caf4805952efc3ee1a4a6d0f8988 commit e6b322cc9a99caf4805952efc3ee1a4a6d0f8988 Author: Jeff Law Date: Fri Aug 16 13:27:37 2024 -0600 Manual applicatoin of riscv specific changes from: commit acc70606c59e3f14072cc8a164362e728d8df5d6 Author: Sam J

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Drop accidental hunk.

https://gcc.gnu.org/g:0a279dfd56e5e38bf3c23257b92bab1ccfcd0747 commit 0a279dfd56e5e38bf3c23257b92bab1ccfcd0747 Author: Jeff Law Date: Fri Aug 16 13:52:44 2024 -0600 Drop accidental hunk. Not worth the effort to find the patch where it got incorrectly introduced (duplicate). D

[gcc r15-2957] Fix maybe-uninitialized CodeView LF_INDEX warning

https://gcc.gnu.org/g:2e2a1cae88522b1966ec01db4c5fda4dbb5949ef commit r15-2957-g2e2a1cae88522b1966ec01db4c5fda4dbb5949ef Author: Mark Harmstone Date: Mon Aug 12 23:19:55 2024 +0100 Fix maybe-uninitialized CodeView LF_INDEX warning Initialize last_type to 0 to silence two spurious

[gcc r15-2958] Write CodeView information about local static variables

https://gcc.gnu.org/g:85e0d6723e7e056c079787486837bfb4f2fa6b8d commit r15-2958-g85e0d6723e7e056c079787486837bfb4f2fa6b8d Author: Mark Harmstone Date: Sat Jul 13 21:32:40 2024 +0100 Write CodeView information about local static variables Outputs CodeView S_LDATA32 symbols, for stat

[gcc r15-2959] Write CodeView information about enregistered variables

https://gcc.gnu.org/g:af61fc99f7a98efd6446692cc61d9fa43f6173a4 commit r15-2959-gaf61fc99f7a98efd6446692cc61d9fa43f6173a4 Author: Mark Harmstone Date: Thu Aug 8 02:36:41 2024 +0100 Write CodeView information about enregistered variables Outputs CodeView S_REGISTER symbols, represen

[gcc r15-2960] Write CodeView information about stack variables

https://gcc.gnu.org/g:1e7dabbbe271bee0a9610dfdb0d62647c04a6194 commit r15-2960-g1e7dabbbe271bee0a9610dfdb0d62647c04a6194 Author: Mark Harmstone Date: Thu Aug 8 02:38:54 2024 +0100 Write CodeView information about stack variables Outputs CodeView S_REGREL32 symbols for unoptimized

[gcc] Created branch 'meissner/heads/work176' in namespace 'refs/users'

The branch 'meissner/heads/work176' was created in namespace 'refs/users' pointing to: 1e7dabbbe27... Write CodeView information about stack variables

[gcc(refs/users/meissner/heads/work176)] Add ChangeLog.meissner and REVISION.

https://gcc.gnu.org/g:9bd8691e25ca16ebbe2385182d8f7d5bc16bd32c commit 9bd8691e25ca16ebbe2385182d8f7d5bc16bd32c Author: Michael Meissner Date: Fri Aug 16 20:00:35 2024 -0400 Add ChangeLog.meissner and REVISION. 2024-08-16 Michael Meissner gcc/ * REVISIO

[gcc] Created branch 'meissner/heads/work176-dmf' in namespace 'refs/users'

The branch 'meissner/heads/work176-dmf' was created in namespace 'refs/users' pointing to: 9bd8691e25c... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work176-dmf)] Add ChangeLog.dmf and update REVISION.

https://gcc.gnu.org/g:2f5f585dae78be0166b9367c752dcd6f6054808f commit 2f5f585dae78be0166b9367c752dcd6f6054808f Author: Michael Meissner Date: Fri Aug 16 20:01:40 2024 -0400 Add ChangeLog.dmf and update REVISION. 2024-08-16 Michael Meissner gcc/ * Chang

[gcc] Created branch 'meissner/heads/work176-vpair' in namespace 'refs/users'

The branch 'meissner/heads/work176-vpair' was created in namespace 'refs/users' pointing to: 9bd8691e25c... Add ChangeLog.meissner and REVISION.

[gcc(refs/users/meissner/heads/work176-vpair)] Add ChangeLog.vpair and update REVISION.

https://gcc.gnu.org/g:217eac978ad1f41265f54228db31152de2f94b70 commit 217eac978ad1f41265f54228db31152de2f94b70 Author: Michael Meissner Date: Fri Aug 16 20:02:38 2024 -0400 Add ChangeLog.vpair and update REVISION. 2024-08-16 Michael Meissner gcc/ * Cha

[gcc] Created branch 'meissner/heads/work176-tar' in namespace 'refs/users'

The branch 'meissner/heads/work176-tar' was created in namespace 'refs/users' pointing to: 9bd8691e25c... Add ChangeLog.meissner and REVISION.

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