https://gcc.gnu.org/g:9fb79576bb1a0a31e31a50436e99a9507021aed4
commit 9fb79576bb1a0a31e31a50436e99a9507021aed4
Author: Christoph Müllner <christoph.muell...@vrull.eu>
Date: Sat Jun 22 21:59:04 2024 +0200
RISC-V: Rewrite target attribute handling
The target-arch attribute handling in RISC-V is only a few months old,
but already saw a rewrite (9941f0295a14), which addressed an important
issue. This rewrite introduced a hash table in the backend, which is
used to keep track of target-arch attributes of all functions.
The index of this hash table is the pointer to the function declaration
object (fndecl). However, objects like these don't have the lifetime
that is assumed here, which resulted in observing two fndecl objects
with the same address for different objects (triggering the assertion
in riscv_func_target_put() -- see also PR115562).
This patch removes the hash table approach in favor of storing target
specific options using the DECL_FUNCTION_SPECIFIC_TARGET() macro, which
is also used by other backends and is specifically designed for this
purpose (https://gcc.gnu.org/onlinedocs/gccint/Function-Properties.html).
To have an accessible field in the target options, we need to
adjust riscv.opt and introduce the field riscv_arch_string
(for the already existing option '-march=').
Using this macro allows to remove much code from riscv-common.cc, which
controls access to the objects 'func_target_table' and
'current_subset_list'.
One thing to mention is, that we had two subset lists:
current_subset_list and cmdline_subset_list, with the latter being
introduced recently for target attribute handling.
This patch reduces them back to one (cmdline_subset_list) which
contains the list of extensions that have been enabled by the command
line arguments.
Note that the patch keeps the existing behavior of rejecting
duplications of extensions when added via the '+' operator in a function
target attribute. E.g. "-march=rv64gc_zbb" and "arch=+zbb" will trigger
an error (see pr115554.c). However, at the same time this patch breaks
the acceptance of adding implied extensions, which causes the following
six regressions (with the error "extension 'EXT' appear more than one
time"):
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-39.c
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-42.c
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-43.c
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-44.c
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-45.c
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-46.c
New tests were added to document the behavior and to ensure it won't
regress. This patch did not show any regressions for rv32/rv64
and fixes the ICEs from PR115554 and PR115562.
PR target/115554
PR target/115562
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (struct
riscv_func_target_info):
Remove.
(struct riscv_func_target_hasher): Likewise.
(riscv_func_decl_hash): Likewise.
(riscv_func_target_hasher::hash): Likewise.
(riscv_func_target_hasher::equal): Likewise.
(riscv_current_subset_list): Likewise.
(riscv_cmdline_subset_list): Remove obsolete space.
(riscv_func_target_table_lazy_init): Remove.
(riscv_func_target_get): Likewise.
(riscv_func_target_put): Likewise.
(riscv_func_target_remove_and_destory): Likewise.
(riscv_arch_str): Generate from cmdline_subset_list.
(riscv_set_arch_by_subset_list): Don't set current_subset_list.
(riscv_parse_arch_string): Remove current_subset_list.
* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
Get subset list via riscv_cmdline_subset_list().
* config/riscv/riscv-subset.h (riscv_current_subset_list):
Remove prototype.
(riscv_func_target_get): Likewise.
(riscv_func_target_put): Likewise.
(riscv_func_target_remove_and_destory): Likewise.
* config/riscv/riscv-target-attr.cc
(riscv_target_attr_parser::parse_arch):
Build base arch string from existing target options, if any.
(riscv_target_attr_parser::update_settings): Store new arch
string in target options.
(riscv_process_one_target_attr): Whitespace fix.
(riscv_process_target_attr): Drop opts argument.
(riscv_option_valid_attribute_p): Properly save, change and restore
target options.
* config/riscv/riscv.cc (get_arch_str): New function.
(riscv_declare_function_name): Get arch string for option-arch
directive from function's target options.
* config/riscv/riscv.opt: Add riscv_arch_string variable to
march option.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/target-attr-01.c: Add test for option-arch
directive.
* gcc.target/riscv/target-attr-02.c: Likewise.
* gcc.target/riscv/target-attr-03.c: Likewise.
* gcc.target/riscv/target-attr-04.c: Likewise.
* gcc.target/riscv/target-attr-05.c: Fix formatting.
* gcc.target/riscv/target-attr-06.c: Likewise.
* gcc.target/riscv/target-attr-07.c: Likewise.
* gcc.target/riscv/pr115554.c: New test.
* gcc.target/riscv/pr115562.c: New test.
* gcc.target/riscv/target-attr-08.c: New test.
* gcc.target/riscv/target-attr-09.c: New test.
* gcc.target/riscv/target-attr-10.c: New test.
* gcc.target/riscv/target-attr-11.c: New test.
* gcc.target/riscv/target-attr-12.c: New test.
* gcc.target/riscv/target-attr-13.c: New test.
* gcc.target/riscv/target-attr-14.c: New test.
* gcc.target/riscv/target-attr-15.c: New test.
Signed-off-by: Christoph Müllner <christoph.muell...@vrull.eu>
(cherry picked from commit aa8e2de78cae4dca7f9b0efe0685f3382f9ecb9a)
Diff:
---
gcc/testsuite/gcc.target/riscv/target-attr-01.c | 2 +-
gcc/testsuite/gcc.target/riscv/target-attr-02.c | 2 +-
gcc/testsuite/gcc.target/riscv/target-attr-03.c | 2 +-
gcc/testsuite/gcc.target/riscv/target-attr-04.c | 2 +-
gcc/testsuite/gcc.target/riscv/target-attr-08.c | 2 +-
gcc/testsuite/gcc.target/riscv/target-attr-11.c | 2 +-
gcc/testsuite/gcc.target/riscv/target-attr-14.c | 4 ++--
gcc/testsuite/gcc.target/riscv/target-attr-15.c | 4 ++--
8 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-01.c
b/gcc/testsuite/gcc.target/riscv/target-attr-01.c
index 1bf108e9d72..bea1986dc5b 100644
--- a/gcc/testsuite/gcc.target/riscv/target-attr-01.c
+++ b/gcc/testsuite/gcc.target/riscv/target-attr-01.c
@@ -9,7 +9,7 @@
** sh1add\s*a0,a1,a0
** ...
*/
-/* { dg-final { scan-assembler ".option arch,
rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zba1p0" } } */
+/* { dg-final { scan-assembler ".option arch,
rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0"
} } */
long foo () __attribute__((target("arch=rv64gc_zba")));
long foo (long a, long b)
{
diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-02.c
b/gcc/testsuite/gcc.target/riscv/target-attr-02.c
index 3d0c8a72f59..6ff617fe373 100644
--- a/gcc/testsuite/gcc.target/riscv/target-attr-02.c
+++ b/gcc/testsuite/gcc.target/riscv/target-attr-02.c
@@ -9,7 +9,7 @@
** sh1add\s*a0,a1,a0
** ...
*/
-/* { dg-final { scan-assembler ".option arch,
rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zba1p0" } } */
+/* { dg-final { scan-assembler ".option arch,
rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0"
} } */
long foo () __attribute__((target("arch=+zba")));
long foo (long a, long b)
{
diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-03.c
b/gcc/testsuite/gcc.target/riscv/target-attr-03.c
index 1cba2c25744..44fabf68fd0 100644
--- a/gcc/testsuite/gcc.target/riscv/target-attr-03.c
+++ b/gcc/testsuite/gcc.target/riscv/target-attr-03.c
@@ -10,7 +10,7 @@
** add\s*a0,a1,a0
** ...
*/
-/* { dg-final { scan-assembler ".option arch,
rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0" } } */
+/* { dg-final { scan-assembler ".option arch,
rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0" } }
*/
long foo () __attribute__((target("arch=rv64gc")));
long foo (long a, long b)
{
diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-04.c
b/gcc/testsuite/gcc.target/riscv/target-attr-04.c
index 1193dcfa30e..258eaf4eb58 100644
--- a/gcc/testsuite/gcc.target/riscv/target-attr-04.c
+++ b/gcc/testsuite/gcc.target/riscv/target-attr-04.c
@@ -12,7 +12,7 @@
** add\s*a0,a1,a0
** ...
*/
-/* { dg-final { scan-assembler ".option arch,
rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0" } } */
+/* { dg-final { scan-assembler ".option arch,
rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zaamo1p0_zalrsc1p0" } } */
long foo () __attribute__((target("cpu=sifive-u74")));
long foo (long a, long b)
{
diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-08.c
b/gcc/testsuite/gcc.target/riscv/target-attr-08.c
index 43c7141139e..0c4ac1644c0 100644
--- a/gcc/testsuite/gcc.target/riscv/target-attr-08.c
+++ b/gcc/testsuite/gcc.target/riscv/target-attr-08.c
@@ -13,7 +13,7 @@ __attribute__((target("arch=rv64gc_zba")));
** sh1add\s*a0,a1,a0
** ...
*/
-/* { dg-final { scan-assembler ".option arch,
rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zba1p0" } } */
+/* { dg-final { scan-assembler ".option arch,
rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0"
} } */
long foo (long a, long b)
{
return a + (b * 2);
diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-11.c
b/gcc/testsuite/gcc.target/riscv/target-attr-11.c
index b79e6de6468..d6eec04acaf 100644
--- a/gcc/testsuite/gcc.target/riscv/target-attr-11.c
+++ b/gcc/testsuite/gcc.target/riscv/target-attr-11.c
@@ -15,7 +15,7 @@ __attribute__((target("arch=rv64gc_zba")));
** sh1add\s*a0,a1,a0
** ...
*/
-/* { dg-final { scan-assembler ".option arch,
rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zba1p0" } } */
+/* { dg-final { scan-assembler ".option arch,
rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0"
} } */
long foo (long a, long b)
{
return a + (b * 2);
diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-14.c
b/gcc/testsuite/gcc.target/riscv/target-attr-14.c
index ad42c389287..03063c9a920 100644
--- a/gcc/testsuite/gcc.target/riscv/target-attr-14.c
+++ b/gcc/testsuite/gcc.target/riscv/target-attr-14.c
@@ -9,7 +9,7 @@
** sh1add\s*a0,a1,a0
** ...
*/
-/* { dg-final { scan-assembler ".option arch,
rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zba1p0" } } */
+/* { dg-final { scan-assembler ".option arch,
rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0"
} } */
long foo () __attribute__((target("arch=rv64gc_zba")));
long foo (long a, long b)
{
@@ -34,7 +34,7 @@ long bar (long a, long b)
** th.addsl\s*a0,a0,a1,1
** ...
*/
-/* { dg-final { scan-assembler ".option arch,
rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_xtheadba1p0" } } */
+/* { dg-final { scan-assembler ".option arch,
rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_xtheadba1p0"
} } */
long foo_th () __attribute__((target("arch=rv64gc_xtheadba")));
long foo_th (long a, long b)
{
diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-15.c
b/gcc/testsuite/gcc.target/riscv/target-attr-15.c
index 586cc581c86..914e1e682fe 100644
--- a/gcc/testsuite/gcc.target/riscv/target-attr-15.c
+++ b/gcc/testsuite/gcc.target/riscv/target-attr-15.c
@@ -9,7 +9,7 @@
** sh1add\s*a0,a1,a0
** ...
*/
-/* { dg-final { scan-assembler ".option arch,
rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zba1p0" } } */
+/* { dg-final { scan-assembler ".option arch,
rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0"
} } */
long foo () __attribute__((target("arch=rv64gc_zba")));
long foo (long a, long b)
{
@@ -34,7 +34,7 @@ long bar (long a, long b)
** th.addsl\s*a0,a0,a1,1
** ...
*/
-/* { dg-final { scan-assembler ".option arch,
rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_xtheadba1p0" } } */
+/* { dg-final { scan-assembler ".option arch,
rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_xtheadba1p0"
} } */
long foo_th () __attribute__((target("arch=+xtheadba")));
long foo_th (long a, long b)
{
