[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Partial: Just the testsuite bits...

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:84684236ca332f9d4732c9d6c8a892ea058d61a1

commit 84684236ca332f9d4732c9d6c8a892ea058d61a1
Author: Pan Li <pan2...@intel.com>
Date:   Tue Aug 6 20:59:37 2024 +0800

    Partial: Just the testsuite bits...
    
    Vect: Make sure the lhs type of .SAT_TRUNC has its mode precision [PR116202]
    
    The .SAT_TRUNC vect pattern recog is valid when the lhs type has
    its mode precision.  For example as below, QImode with 1 bit precision
    like _Bool is invalid here.
    
    g_12 = (long unsigned int) _2;
    _13 = MIN_EXPR <g_12, 1>;
    _3 = (_Bool) _13;
    
    The above pattern cannot be recog as .SAT_TRUNC (g_12) because the dest
    only has 1 bit precision with QImode mode.  Aka the type doesn't have
    the mode precision.
    
    The below tests are passed for this patch.
    1. The rv64gcv fully regression tests.
    2. The x86 bootstrap tests.
    3. The x86 fully regression tests.
    
            PR target/116202
    
    gcc/ChangeLog:
    
            * tree-vect-patterns.cc (vect_recog_sat_trunc_pattern): Add the
            type_has_mode_precision_p check for the lhs type.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/base/pr116202-run-1.c: New test.
    
    Signed-off-by: Pan Li <pan2...@intel.com>
    (cherry picked from commit 06d3f31384a89039c510531cf8012caed05b2ffd)

Diff:
---
 .../gcc.target/riscv/rvv/base/pr116202-run-1.c     | 24 ++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c
new file mode 100644
index 00000000000..d150f20b5d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116202-run-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -march=rv64gcv_zvl256b -fdump-rtl-expand-details" } */
+
+int b[24];
+_Bool c[24];
+
+int main() {
+  for (int f = 0; f < 4; ++f)
+    b[f] = 6;
+
+  for (int f = 0; f < 24; f += 4)
+    c[f] = ({
+      int g = ({
+        unsigned long g = -b[f];
+        1 < g ? 1 : g;
+      });
+      g;
+    });
+
+  if (c[0] != 1)
+    __builtin_abort ();
+}
+
+/* { dg-final { scan-rtl-dump-not ".SAT_TRUNC " "expand" } } */