https://gcc.gnu.org/g:e6b322cc9a99caf4805952efc3ee1a4a6d0f8988

commit e6b322cc9a99caf4805952efc3ee1a4a6d0f8988
Author: Jeff Law <j...@ventanamicro.com>
Date:   Fri Aug 16 13:27:37 2024 -0600

    Manual applicatoin of riscv specific changes from:
    
    commit acc70606c59e3f14072cc8a164362e728d8df5d6
    Author: Sam James <s...@gentoo.org>
    Date:   Tue Jul 30 20:04:40 2024 +0100
    
        testsuite: fix 'dg-compile' typos
    
        'dg-compile' is not a thing, replace it with 'dg-do compile'.
    
                PR target/68015
                PR c++/83979
                * c-c++-common/goacc/loop-shape.c: Fix 'dg-compile' typo.
                * g++.dg/pr83979.C: Likewise.
                * g++.target/aarch64/sve/acle/general-c++/attributes_2.C: 
Likewise.
                * gcc.dg/tree-ssa/builtin-sprintf-7.c: Likewise.
                * gcc.dg/tree-ssa/builtin-sprintf-8.c: Likewise.
                * gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c: Likewise.
                * gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c: 
Likewise.
                * gcc.target/s390/20181024-1.c: Likewise.
                * gcc.target/s390/addr-constraints-1.c: Likewise.
                * gcc.target/s390/arch12/aghsghmgh-1.c: Likewise.
                * gcc.target/s390/arch12/mul-1.c: Likewise.
                * gcc.target/s390/arch13/bitops-1.c: Likewise.
                * gcc.target/s390/arch13/bitops-2.c: Likewise.
                * gcc.target/s390/arch13/fp-signedint-convert-1.c: Likewise.
                * gcc.target/s390/arch13/fp-unsignedint-convert-1.c: Likewise.
                * gcc.target/s390/arch13/popcount-1.c: Likewise.
                * gcc.target/s390/pr68015.c: Likewise.
                * gcc.target/s390/vector/fp-signedint-convert-1.c: Likewise.
                * gcc.target/s390/vector/fp-unsignedint-convert-1.c: Likewise.
                * gcc.target/s390/vector/reverse-elements-1.c: Likewise.
                * gcc.target/s390/vector/reverse-elements-2.c: Likewise.
                * gcc.target/s390/vector/reverse-elements-3.c: Likewise.
                * gcc.target/s390/vector/reverse-elements-4.c: Likewise.
                * gcc.target/s390/vector/reverse-elements-5.c: Likewise.
                * gcc.target/s390/vector/reverse-elements-6.c: Likewise.
                * gcc.target/s390/vector/reverse-elements-7.c: Likewise.
                * gnat.dg/alignment15.adb: Likewise.
                * gnat.dg/debug4.adb: Likewise.
                * gnat.dg/inline21.adb: Likewise.
                * gnat.dg/inline22.adb: Likewise.
                * gnat.dg/opt37.adb: Likewise.
                * gnat.dg/warn13.adb: Likewise.

Diff:
---
 gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c 
b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c
index 85841fd7036..58211207186 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c
@@ -1,5 +1,5 @@
 /* Test __atomic routines for existence on 2 byte values with each valid 
memory model.  */
-/* { dg-compile } */
+/* { dg-do compile } */
 /* { dg-options "-Wno-address-of-packed-member" } */
 /* { dg-add-options riscv_zabha } */
 /* { dg-remove-options riscv_ztso } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c 
b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c
index edc0a2c8f8e..c846ca48d72 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c
@@ -1,5 +1,5 @@
 /* Test __atomic routines for existence on 2 byte values with each valid 
memory model.  */
-/* { dg-compile } */
+/* { dg-do compile } */
 /* { dg-options "-Wno-address-of-packed-member" } */
 /* { dg-add-options riscv_zabha } */
 /* { dg-remove-options riscv_ztso } */

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