[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add SiFive extensions, xsfvcp and xsfcease

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:dd3171eebd56f22cf06afbc9fbe992709d41965e

commit dd3171eebd56f22cf06afbc9fbe992709d41965e
Author: Kito Cheng <kito.ch...@sifive.com>
Date:   Tue Jul 9 15:50:57 2024 +0800

    RISC-V: Add SiFive extensions, xsfvcp and xsfcease
    
    We have already upstreamed these extensions into binutils, and now we need 
GCC
    to recognize these extensions and pass them to binutils as well. We also 
plan
    to upstream intrinsics in the near future. :)
    
    gcc/ChangeLog:
    
            * common/config/riscv/riscv-common.cc (riscv_implied_info): Add 
xsfvcp.
            (riscv_ext_version_table): Add xsfvcp, xsfcease.
            (riscv_ext_flag_table): Ditto.
            * config/riscv/riscv.opt (riscv_sifive_subext): New.
            (XSFVCP): New.
            (XSFCEASE): New.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/predef-sf-1.c: New.
            * gcc.target/riscv/predef-sf-2.c: New.
    
    (cherry picked from commit 3ea47ea1fcab95fd1b80acc724fdbb27fc436985)

Diff:
---
 gcc/common/config/riscv/riscv-common.cc      |  8 ++++++++
 gcc/config/riscv/riscv.opt                   |  7 +++++++
 gcc/testsuite/gcc.target/riscv/predef-sf-1.c | 19 +++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/predef-sf-2.c | 14 ++++++++++++++
 4 files changed, 48 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index e682b0f5c67..682826c0e34 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -216,6 +216,8 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"ssstateen", "zicsr"},
   {"sstc", "zicsr"},
 
+  {"xsfvcp", "zve32x"},
+
   {NULL, NULL}
 };
 
@@ -415,6 +417,9 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
 
   {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"xsfvcp",   ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xsfcease", ISA_SPEC_CLASS_NONE, 1, 0},
+
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
@@ -1730,6 +1735,9 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
 
   {"xventanacondops", &gcc_options::x_riscv_xventana_subext, 
MASK_XVENTANACONDOPS},
 
+  {"xsfvcp",   &gcc_options::x_riscv_sifive_subext, MASK_XSFVCP},
+  {"xsfcease", &gcc_options::x_riscv_sifive_subext, MASK_XSFCEASE},
+
   {NULL, NULL, 0}
 };
 
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index e882caa8b7f..edf1c6d85f3 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -507,6 +507,13 @@ int riscv_xventana_subext
 
 Mask(XVENTANACONDOPS) Var(riscv_xventana_subext)
 
+TargetVariable
+int riscv_sifive_subext
+
+Mask(XSFVCP) Var(riscv_sifive_subext)
+
+Mask(XSFCEASE) Var(riscv_sifive_subext)
+
 Enum
 Name(isa_spec_class) Type(enum riscv_isa_spec_class)
 Supported ISA specs (for use with the -misa-spec= option):
diff --git a/gcc/testsuite/gcc.target/riscv/predef-sf-1.c 
b/gcc/testsuite/gcc.target/riscv/predef-sf-1.c
new file mode 100644
index 00000000000..d6c07e7d920
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-sf-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_xsfvcp -mabi=lp64" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if !defined(__riscv_zve32x)
+#error "__riscv_zve32x"
+#endif
+
+
+#if !defined(__riscv_xsfvcp)
+#error "__riscv_xsfvcp"
+#endif
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-sf-2.c 
b/gcc/testsuite/gcc.target/riscv/predef-sf-2.c
new file mode 100644
index 00000000000..dcb746bcd26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-sf-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_xsfcease -mabi=lp64" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if !defined(__riscv_xsfcease)
+#error "__riscv_xsfvcp"
+#endif
+
+  return 0;
+}