[gcc r16-1047] RISC-V: Adjust build rule for gen-riscv-ext-opt and gen-riscv-ext-texi

https://gcc.gnu.org/g:b0dc2324980bbb600ab178dacfe5455365a52645 commit r16-1047-gb0dc2324980bbb600ab178dacfe5455365a52645 Author: Kito Cheng Date: Wed May 28 17:59:11 2025 +0800 RISC-V: Adjust build rule for gen-riscv-ext-opt and gen-riscv-ext-texi Separate the build rules to compi

[gcc r16-1046] c++tools: Don't check --enable-default-pie.

https://gcc.gnu.org/g:3f1f99ef82a65d66e3aaa429bf4fb746b93da0db commit r16-1046-g3f1f99ef82a65d66e3aaa429bf4fb746b93da0db Author: Kito Cheng Date: Tue May 27 10:10:15 2025 +0800 c++tools: Don't check --enable-default-pie. `--enable-default-pie` is an option to specify whether to en

[gcc r16-1045] RISC-V: Implement full-featured iterator for riscv_subset_list [NFC]

https://gcc.gnu.org/g:54e9cb8ec2633764b59746101883f9c3397125e5 commit r16-1045-g54e9cb8ec2633764b59746101883f9c3397125e5 Author: Kito Cheng Date: Mon May 26 14:43:47 2025 +0800 RISC-V: Implement full-featured iterator for riscv_subset_list [NFC] This commit implements a full-featu

[gcc r16-949] RISC-V: Add minimal support of double trap extension 1.0

https://gcc.gnu.org/g:077cdc9dc0ff7f5c9d12829bfed220d1e63b1525 commit r16-949-g077cdc9dc0ff7f5c9d12829bfed220d1e63b1525 Author: Jerry Zhang Jian Date: Wed May 28 10:17:36 2025 +0800 RISC-V: Add minimal support of double trap extension 1.0 Add support of double trap extension [1],

[gcc r16-889] driver: Fix multilib_os_dir and multiarch_dir for those target use TARGET_COMPUTE_MULTILIB

https://gcc.gnu.org/g:447156e4d143d7f513c488dd0b44037524a01fba commit r16-889-g447156e4d143d7f513c488dd0b44037524a01fba Author: Kito Cheng Date: Mon Mar 10 16:26:04 2025 +0800 driver: Fix multilib_os_dir and multiarch_dir for those target use TARGET_COMPUTE_MULTILIB This patch fi

[gcc r16-729] RISC-V: Rename conflicting variables in gen-riscv-ext-texi.cc

https://gcc.gnu.org/g:11936041970a45e5cf9a75110f365398451be6b5 commit r16-729-g11936041970a45e5cf9a75110f365398451be6b5 Author: zhusonghe Date: Mon May 19 10:43:48 2025 +0800 RISC-V: Rename conflicting variables in gen-riscv-ext-texi.cc The variables `major` and `minor` in `gen-ri

[gcc r16-730] RISC-V: Fix the warning of temporary object dangling references.

https://gcc.gnu.org/g:7fabbf3562812f648bb49d0a7ea6b74e88defd4b commit r16-730-g7fabbf3562812f648bb49d0a7ea6b74e88defd4b Author: Dongyan Chen Date: Mon May 19 15:17:12 2025 +0800 RISC-V: Fix the warning of temporary object dangling references. During the GCC compilation, some warni

[gcc r16-728] RISC-V: Support Zilsd code gen

https://gcc.gnu.org/g:a3e78dda4d51bc37adcfa088237e2b8567e76da2 commit r16-728-ga3e78dda4d51bc37adcfa088237e2b8567e76da2 Author: Kito Cheng Date: Mon May 12 02:38:39 2025 -0700 RISC-V: Support Zilsd code gen This commit adds the code gen support for Zilsd, which is a newly adde

[gcc r16-726] RISC-V: Add new operand constraint: cR

https://gcc.gnu.org/g:c9eb473fb9946f642506d24f4131d7c83855fd78 commit r16-726-gc9eb473fb9946f642506d24f4131d7c83855fd78 Author: Kito Cheng Date: Mon May 12 14:36:07 2025 +0800 RISC-V: Add new operand constraint: cR This commit introduces a new operand constraint `cR` for the RISC-

[gcc r16-632] RISC-V: Add augmented hypervisor series extensions.

https://gcc.gnu.org/g:0cbace3b142c087335e245245e97f6605a6cd1f7 commit r16-632-g0cbace3b142c087335e245245e97f6605a6cd1f7 Author: Jiawei Date: Tue May 13 15:23:39 2025 +0800 RISC-V: Add augmented hypervisor series extensions. The augmented hypervisor series extensions 'sha'[1] is a

[gcc r16-633] RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup issue

https://gcc.gnu.org/g:991adf8b18c3fa03eff6cfbf396d9a15ef17f93c commit r16-633-g991adf8b18c3fa03eff6cfbf396d9a15ef17f93c Author: Kito Cheng Date: Tue May 13 10:34:34 2025 +0800 RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup issue We forgot to initialize m_allow_adding_dup

[gcc r16-630] RISC-V: Regen riscv-ext.opt.urls

https://gcc.gnu.org/g:f05586727dfafd1af9fa303e5a99afdd94770373 commit r16-630-gf05586727dfafd1af9fa303e5a99afdd94770373 Author: Kito Cheng Date: Wed May 14 23:19:17 2025 +0800 RISC-V: Regen riscv-ext.opt.urls gcc/ChangeLog: * config/riscv/riscv-ext.opt.urls: Regen

[gcc r16-631] RISC-V: Drop duplicate build rule for riscv-ext.opt [NFC]

https://gcc.gnu.org/g:eedaf969f4d24dad368de63ea40b1e694fd57c40 commit r16-631-geedaf969f4d24dad368de63ea40b1e694fd57c40 Author: Kito Cheng Date: Wed May 14 23:19:38 2025 +0800 RISC-V: Drop duplicate build rule for riscv-ext.opt [NFC] gcc/ChangeLog: * config/riscv/

[gcc r16-585] RISC-V: Drop riscv_implied_info and riscv_combine_info in favor of riscv_ext_info_t data

https://gcc.gnu.org/g:8aa02f1729b0b8d39d3a93c3e0f36139f80ec0cd commit r16-585-g8aa02f1729b0b8d39d3a93c3e0f36139f80ec0cd Author: Kito Cheng Date: Wed May 7 21:21:01 2025 +0800 RISC-V: Drop riscv_implied_info and riscv_combine_info in favor of riscv_ext_info_t data Consolidate impl

[gcc r16-580] RISC-V: Introduce riscv-ext*.def to define extensions

https://gcc.gnu.org/g:48180266da19b0ad08e64fa9f1ade897f9b2ef58 commit r16-580-g48180266da19b0ad08e64fa9f1ade897f9b2ef58 Author: Kito Cheng Date: Wed May 7 18:02:10 2025 +0800 RISC-V: Introduce riscv-ext*.def to define extensions Adding a new ISA extension to RISC-V GCC requires mo

[gcc r16-581] RISC-V: Use riscv-ext.def to generate target options and variables

https://gcc.gnu.org/g:ea6154919a6416c2f75dcf025125f6926d06 commit r16-581-gea6154919a6416c2f75dcf025125f6926d06 Author: Kito Cheng Date: Wed May 7 18:28:18 2025 +0800 RISC-V: Use riscv-ext.def to generate target options and variables Leverage the centralized riscv-ext.def

[gcc r16-583] RISC-V: Adjust riscv_can_inline_p

https://gcc.gnu.org/g:590701c97748cd7f99f15fbd0d75076dd75bea3d commit r16-583-g590701c97748cd7f99f15fbd0d75076dd75bea3d Author: Kito Cheng Date: Wed May 7 18:30:34 2025 +0800 RISC-V: Adjust riscv_can_inline_p We don't hold any extenison flags in `target_flags`, so no need to g

[gcc r16-587] RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_info_t data

https://gcc.gnu.org/g:90c6ccebd762ae920690fce20cd3f2b8e24357a7 commit r16-587-g90c6ccebd762ae920690fce20cd3f2b8e24357a7 Author: Kito Cheng Date: Wed May 7 21:27:20 2025 +0800 RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_info_t data Refactor extension flag handling by re

[gcc r16-582] RISC-V: Generate extension table in documentation from riscv-ext.def

https://gcc.gnu.org/g:124cbbbed5b8f7454f93f9a87e57fd4f3f2f78d2 commit r16-582-g124cbbbed5b8f7454f93f9a87e57fd4f3f2f78d2 Author: Kito Cheng Date: Wed May 7 21:10:53 2025 +0800 RISC-V: Generate extension table in documentation from riscv-ext.def Automatically build the ISA extension

[gcc r16-586] RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_info_t data

https://gcc.gnu.org/g:897bb6d4347469e378aad9e00fc4b5c6fcb1e9ce commit r16-586-g897bb6d4347469e378aad9e00fc4b5c6fcb1e9ce Author: Kito Cheng Date: Thu May 8 16:23:29 2025 +0800 RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_info_t data This commit drops the riscv_ext_ver

[gcc r16-584] RISC-V: Introduce riscv_ext_info_t to hold extension metadata

https://gcc.gnu.org/g:312c407aac772f3535ff952ebc5ebff1057a593c commit r16-584-g312c407aac772f3535ff952ebc5ebff1057a593c Author: Kito Cheng Date: Wed May 7 20:59:15 2025 +0800 RISC-V: Introduce riscv_ext_info_t to hold extension metadata Define a new riscv_ext_info_t struct to aggr

[gcc r16-560] RISC-V: Support for zilsd and zclsd extensions.

https://gcc.gnu.org/g:d42f7244289ad8be1d3f7320528240bb849979e4 commit r16-560-gd42f7244289ad8be1d3f7320528240bb849979e4 Author: Dongyan Chen Date: Mon Mar 17 22:23:18 2025 +0800 RISC-V: Support for zilsd and zclsd extensions. This patch support zilsd and zclsd[1] extensions. T

[gcc r16-561] RISC-V: Minimal support for ssnpm, smnpm and smmpm extensions.

https://gcc.gnu.org/g:7e5f5fd101f8686d34532f7afab9314f252e71cd commit r16-561-g7e5f5fd101f8686d34532f7afab9314f252e71cd Author: Dongyan Chen Date: Mon May 12 17:19:24 2025 +0800 RISC-V: Minimal support for ssnpm, smnpm and smmpm extensions. This patch support ssnpm, smnpm, smmpm,

[gcc r16-390] RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054]

https://gcc.gnu.org/g:fcc74146e3e0bfd30f9ccc12359991d73fe928f9 commit r16-390-gfcc74146e3e0bfd30f9ccc12359991d73fe928f9 Author: Kito Cheng Date: Mon May 5 10:08:22 2025 +0800 RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054] gcc/testsuite/ChangeLog: PR target/12

[gcc r16-380] RISC-V: Apply clang-format to genrvv-type-indexer.cc [NFC]

https://gcc.gnu.org/g:d3651f07bbf56837f019e366b75d01f197dab2f1 commit r16-380-gd3651f07bbf56837f019e366b75d01f197dab2f1 Author: Kito Cheng Date: Mon May 5 10:16:14 2025 +0800 RISC-V: Apply clang-format to genrvv-type-indexer.cc [NFC] Tweak the formatting of the genrvv-type-indexer

[gcc r16-299] RISC-V: Fix missing implied Zicsr from Zve32x

https://gcc.gnu.org/g:a992164c2899735525a7a267654473b7e527ef0d commit r16-299-ga992164c2899735525a7a267654473b7e527ef0d Author: Jerry Zhang Jian Date: Wed Apr 30 15:34:07 2025 +0800 RISC-V: Fix missing implied Zicsr from Zve32x The Zve32x extension depends on the Zicsr extension.

[gcc r16-300] RISC-V: Allow different dynamic floating point mode to be merged [PR119832]

https://gcc.gnu.org/g:e5d1f538bb7d2c7a7a4acf4a4516fa8933dc2888 commit r16-300-ge5d1f538bb7d2c7a7a4acf4a4516fa8933dc2888 Author: Kito Cheng Date: Tue Apr 29 11:35:00 2025 +0800 RISC-V: Allow different dynamic floating point mode to be merged [PR119832] Although we already try to se

[gcc r16-297] RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.

https://gcc.gnu.org/g:cc8b8c0b69200ab816a2626e29d91ac995f7438f commit r16-297-gcc8b8c0b69200ab816a2626e29d91ac995f7438f Author: yulong Date: Tue Apr 29 21:12:03 2025 +0800 RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions. This commit adds testcases for Xsfvcp.

[gcc r16-296] RISC-V: Add intrinsics support for SiFive Xsfvcp extensions.

https://gcc.gnu.org/g:37a6fbe652220dbb8aa38afd20443639a97bbd2f commit r16-296-g37a6fbe652220dbb8aa38afd20443639a97bbd2f Author: yulong Date: Tue Apr 29 21:12:02 2025 +0800 RISC-V: Add intrinsics support for SiFive Xsfvcp extensions. This version is same as v5, but rebase to trunk,

[gcc r14-11701] RISC-V: vsetvl: elide abnormal edges from LCM computations [PR119533]

https://gcc.gnu.org/g:e363940e1cef7f6face970414ffaa565daf413bd commit r14-11701-ge363940e1cef7f6face970414ffaa565daf413bd Author: Vineet Gupta Date: Tue Apr 15 09:29:08 2025 -0700 RISC-V: vsetvl: elide abnormal edges from LCM computations [PR119533] vsetvl phase4 uses LCM guided i

[gcc r14-11700] RISC-V: Do not lift up vsetvl into non-transparent blocks [PR119547].

https://gcc.gnu.org/g:ae6ce4cd33d00b8acc9503b0d4883fa92c1a696d commit r14-11700-gae6ce4cd33d00b8acc9503b0d4883fa92c1a696d Author: Robin Dapp Date: Fri Apr 4 17:06:44 2025 +0200 RISC-V: Do not lift up vsetvl into non-transparent blocks [PR119547]. When lifting up a vsetvl into a bl

[gcc r16-283] RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS

https://gcc.gnu.org/g:102eccaf8e2f914d3afbf7acfcee19bc5b240eca commit r16-283-g102eccaf8e2f914d3afbf7acfcee19bc5b240eca Author: Zhijin Zeng Date: Mon Apr 28 09:24:16 2025 +0800 RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS SIBCALL_REGS/JALR_REGS are also subset of GR_R

[gcc r14-11640] RISC-V: Put jump table in text for large code model

https://gcc.gnu.org/g:b61acf546e189f619ce93a223b7a2171b3e6baf3 commit r14-11640-gb61acf546e189f619ce93a223b7a2171b3e6baf3 Author: Kito Cheng Date: Mon Apr 14 16:03:07 2025 +0800 RISC-V: Put jump table in text for large code model Large code model assume the data or rodata may put

[gcc r14-11639] RISC-V: Fix vec_duplicate[bimode] expander [PR119572].

https://gcc.gnu.org/g:52c1f60bea3f2ec589a694c3a0bf4f1c4666fa5b commit r14-11639-g52c1f60bea3f2ec589a694c3a0bf4f1c4666fa5b Author: Robin Dapp Date: Tue Apr 1 21:17:54 2025 +0200 RISC-V: Fix vec_duplicate[bimode] expander [PR119572]. Since r15-9062-g70391e3958db79 we perform vector

[gcc r15-9514] RISC-V: Put jump table in text for large code model

https://gcc.gnu.org/g:1d9e02bb7e0af4f3d3eaaa1a0f4961970aba5560 commit r15-9514-g1d9e02bb7e0af4f3d3eaaa1a0f4961970aba5560 Author: Kito Cheng Date: Mon Apr 14 16:03:07 2025 +0800 RISC-V: Put jump table in text for large code model Large code model assume the data or rodata may put f

[gcc r15-9515] riscv: Fix incorrect gnu property alignment on rv32

https://gcc.gnu.org/g:fc4099a4842805f1eb59a666e18f84e309df8cb1 commit r15-9515-gfc4099a4842805f1eb59a666e18f84e309df8cb1 Author: Jesse Huang Date: Thu Apr 10 21:25:21 2025 -0700 riscv: Fix incorrect gnu property alignment on rv32 Codegen is incorrectly emitting a ".p2align 3" that

[gcc r14-11546] [RISC-V][PR target/116256] Fix incorrect return value for predicate

https://gcc.gnu.org/g:47b509fef536455d59aeb7b8e97851099c6b29a5 commit r14-11546-g47b509fef536455d59aeb7b8e97851099c6b29a5 Author: Jeff Law Date: Tue Jan 21 06:56:27 2025 -0700 [RISC-V][PR target/116256] Fix incorrect return value for predicate Another bug found while chasing paths

[gcc r14-11580] RISC-V: Fix the behavior for multilib-generator with --cmodel=large on rv32

https://gcc.gnu.org/g:fb0653a0e54203eeb9ff399aee93ed904030b4bd commit r14-11580-gfb0653a0e54203eeb9ff399aee93ed904030b4bd Author: Kito Cheng Date: Thu Apr 10 16:58:49 2025 +0800 RISC-V: Fix the behavior for multilib-generator with --cmodel=large on rv32 Large code model is only su

[gcc r15-9354] RISC-V: Fix the behavior for multilib-generator with --cmodel=large on rv32

https://gcc.gnu.org/g:72dff34bcdd6f05b64bbf07739ab815e673b5946 commit r15-9354-g72dff34bcdd6f05b64bbf07739ab815e673b5946 Author: Kito Cheng Date: Thu Apr 10 16:58:49 2025 +0800 RISC-V: Fix the behavior for multilib-generator with --cmodel=large on rv32 Large code model is only sup

[gcc r15-9353] RISC-V: Include local riscv_vector.h in testsuite

https://gcc.gnu.org/g:9e48698228dbf1bbebba3a52d7ae2f47fee89624 commit r15-9353-g9e48698228dbf1bbebba3a52d7ae2f47fee89624 Author: Kito Cheng Date: Wed Apr 9 21:58:23 2025 +0800 RISC-V: Include local riscv_vector.h in testsuite That could prevent us including stdint.h from glibc, an

[gcc r14-11575] RISC-V:Bugfix for vlmul_ext and vlmul_trunc with NULL return value[pr117286]

https://gcc.gnu.org/g:4bd63c709de82bfecde8cf99145974b349918d5d commit r14-11575-g4bd63c709de82bfecde8cf99145974b349918d5d Author: xuli Date: Mon Oct 28 04:41:09 2024 + RISC-V:Bugfix for vlmul_ext and vlmul_trunc with NULL return value[pr117286] This patch fixes following ICE:

[gcc r14-11564] [PATCH v4] [target/116592] RISC-V: Fix illegal operands "th.vsetvli zero, 0, e32, m8" for XTheadVector

https://gcc.gnu.org/g:4f41d8fa5a73e2703d417b0e44bce48aa35bfd91 commit r14-11564-g4f41d8fa5a73e2703d417b0e44bce48aa35bfd91 Author: Jin Ma Date: Sat Sep 7 10:29:02 2024 -0600 [PATCH v4] [target/116592] RISC-V: Fix illegal operands "th.vsetvli zero,0,e32,m8" for XTheadVector Since t

[gcc r14-11561] [PATCH] RISC-V: Allow zero operand for DI variants of vssubu.vx

https://gcc.gnu.org/g:d0663c143071331bd3bff7e396bc0e761dd98939 commit r14-11561-gd0663c143071331bd3bff7e396bc0e761dd98939 Author: Bohan Lei Date: Wed Sep 18 07:20:23 2024 -0600 [PATCH] RISC-V: Allow zero operand for DI variants of vssubu.vx The RISC-V vector machine description re

[gcc r14-11547] [RISC-V][PR target/116308] Fix generation of initial RTL for atomics

https://gcc.gnu.org/g:f3ac41f84249d10a1685c73d67e5d071902fcc4c commit r14-11547-gf3ac41f84249d10a1685c73d67e5d071902fcc4c Author: Jeff Law Date: Sat Jan 18 13:44:33 2025 -0700 [RISC-V][PR target/116308] Fix generation of initial RTL for atomics While this wasn't originally marked

[gcc r14-11568] RISC-V: Delete duplicate '#define RISCV_DWARF_VLENB'

https://gcc.gnu.org/g:28fe2b087baea05759aa7386fb8c3862aecf51ef commit r14-11568-g28fe2b087baea05759aa7386fb8c3862aecf51ef Author: Jin Ma Date: Thu Aug 8 07:49:51 2024 -0600 RISC-V: Delete duplicate '#define RISCV_DWARF_VLENB' gcc/ChangeLog: * config/riscv/riscv.h

[gcc r14-11567] RISC-V: Fix factor in dwarf_poly_indeterminate_value [PR116305]

https://gcc.gnu.org/g:327c7c38123eec6264324acd98b4386363d05cb4 commit r14-11567-g327c7c38123eec6264324acd98b4386363d05cb4 Author: 曾治金 Date: Wed Aug 14 14:06:23 2024 +0800 RISC-V: Fix factor in dwarf_poly_indeterminate_value [PR116305] This patch is to fix the bug (BugId:116305) in

[gcc r14-11562] riscv: Fix duplicate assmbler label in @tlsdesc insn

https://gcc.gnu.org/g:5615fea2fce63d49d67691f102601868147c2bbc commit r14-11562-g5615fea2fce63d49d67691f102601868147c2bbc Author: Andreas Schwab Date: Thu Sep 12 13:55:09 2024 +0200 riscv: Fix duplicate assmbler label in @tlsdesc insn Use %= instead of maintaining a sequence numbe

[gcc r14-11563] RISC-V: Fix vl_used_by_non_rvv_insn logic of vsetvl pass

https://gcc.gnu.org/g:94b774c5c1cd67608c31d593167996351e952cea commit r14-11563-g94b774c5c1cd67608c31d593167996351e952cea Author: garthlei Date: Wed Sep 11 17:09:37 2024 +0800 RISC-V: Fix vl_used_by_non_rvv_insn logic of vsetvl pass This patch fixes a bug in the current vsetvl pas

[gcc r14-11571] RISC-V: Reject 'd' extension with ILP32E ABI

https://gcc.gnu.org/g:eaf423763c780795ea7ae914d390ac07e149871e commit r14-11571-geaf423763c780795ea7ae914d390ac07e149871e Author: Patrick O'Neill Date: Tue Jul 30 14:28:23 2024 -0700 RISC-V: Reject 'd' extension with ILP32E ABI Also add a testcase for -mabi=lp64d where 'd' is requ

[gcc r14-11570] RISC-V: Correct mode_idx attribute for viwalu wx variants [PR116149].

https://gcc.gnu.org/g:95ac2d8afb386ccd7277f4906e0aca88d53c835a commit r14-11570-g95ac2d8afb386ccd7277f4906e0aca88d53c835a Author: Robin Dapp Date: Wed Jul 31 16:54:03 2024 +0200 RISC-V: Correct mode_idx attribute for viwalu wx variants [PR116149]. In PR116149 we choose a wrong vec

[gcc r14-11572] RISC-V: Error early with V and no M extension.

https://gcc.gnu.org/g:b7d975945025d1e4e9237c90b46bf4f660289d22 commit r14-11572-gb7d975945025d1e4e9237c90b46bf4f660289d22 Author: Robin Dapp Date: Wed Jul 24 09:08:00 2024 +0200 RISC-V: Error early with V and no M extension. For calculating the value of a poly_int at runtime we us

[gcc r14-11555] RISC-V: Fix compress shuffle pattern [PR117383].

https://gcc.gnu.org/g:ca6adeda373fc97ff57a79bc1a078f90776330cd commit r14-11555-gca6adeda373fc97ff57a79bc1a078f90776330cd Author: Robin Dapp Date: Wed Dec 11 20:48:30 2024 +0100 RISC-V: Fix compress shuffle pattern [PR117383]. This patch makes vcompress use the tail-undisturbed po

[gcc r14-11566] RISC-V: Add missing mode_idx for vrol and vror

https://gcc.gnu.org/g:d2f5d28415fe28881b4b8cadf6df85cf94ded233 commit r14-11566-gd2f5d28415fe28881b4b8cadf6df85cf94ded233 Author: Kito Cheng Date: Tue Aug 27 21:27:02 2024 +0800 RISC-V: Add missing mode_idx for vrol and vror We add pattern for vector rotate, but seems like we forg

[gcc r14-11557] RISC-V: Ensure vtype for full-register moves [PR117544].

https://gcc.gnu.org/g:164aededa828c5db6195a10f9d0f6a500f2cbef9 commit r14-11557-g164aededa828c5db6195a10f9d0f6a500f2cbef9 Author: Robin Dapp Date: Thu Nov 21 14:49:53 2024 +0100 RISC-V: Ensure vtype for full-register moves [PR117544]. As discussed in PR117544 the VTYPE register is

[gcc r14-11560] [PATCH] RISC-V: Fix th.extu operands exceeding range on rv32.

https://gcc.gnu.org/g:5b3558944a7a03071744585ee8c55f30d51b5653 commit r14-11560-g5b3558944a7a03071744585ee8c55f30d51b5653 Author: Xianmiao Qu Date: Wed Sep 18 07:28:44 2024 -0600 [PATCH] RISC-V: Fix th.extu operands exceeding range on rv32. The Combine Pass may generate zero_extra

[gcc r14-11558] [PATCH v3] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on

https://gcc.gnu.org/g:37d13153635b78013a8d27d2be9da99d0f2a88a7 commit r14-11558-g37d13153635b78013a8d27d2be9da99d0f2a88a7 Author: Jin Ma Date: Wed Sep 18 08:56:23 2024 -0600 [PATCH v3] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on rv32.

[gcc r14-11559] [PATCH 1/2] RISC-V: Fix the outer_code when calculating the cost of SET expression.

https://gcc.gnu.org/g:80ab25142565e83477af7c3e57f0a4dcf51b9659 commit r14-11559-g80ab25142565e83477af7c3e57f0a4dcf51b9659 Author: Xianmiao Qu Date: Wed Sep 18 07:35:12 2024 -0600 [PATCH 1/2] RISC-V: Fix the outer_code when calculating the cost of SET expression. I think it is a t

[gcc r14-11554] [RISC-V][PR target/106544] Avoid ICEs due to bogus asms

https://gcc.gnu.org/g:6547906bdbdb3feb0d3bd96e09ceffcbc489349f commit r14-11554-g6547906bdbdb3feb0d3bd96e09ceffcbc489349f Author: Jeff Law Date: Mon Dec 30 13:51:55 2024 -0700 [RISC-V][PR target/106544] Avoid ICEs due to bogus asms This is a fix for a bug Andrew P filed a while ba

[gcc r14-11552] RISC-V: Disallow negative step for interleaving [PR117682]

https://gcc.gnu.org/g:08e381e8af3ec9beaa887824c41d4551b54e5063 commit r14-11552-g08e381e8af3ec9beaa887824c41d4551b54e5063 Author: Robin Dapp Date: Mon Jan 13 17:09:35 2025 -0700 RISC-V: Disallow negative step for interleaving [PR117682] Hi, in PR117682 we build an interle

[gcc r14-11576] RISC-V: Fix vid const vector expander for non-npatterns size steps

https://gcc.gnu.org/g:6a66212916e70a9f27adf458b79c309c926dcf42 commit r14-11576-g6a66212916e70a9f27adf458b79c309c926dcf42 Author: Patrick O'Neill Date: Wed Aug 21 23:48:24 2024 -0700 RISC-V: Fix vid const vector expander for non-npatterns size steps Prior to this patch the expande

[gcc r14-11573] [committed] [RISC-V] Fix false-positive uninitialized variable

https://gcc.gnu.org/g:cdb987e977e03ba78a8a0e094967a5121e01f2ce commit r14-11573-gcdb987e977e03ba78a8a0e094967a5121e01f2ce Author: Jeff Law Date: Sun Jun 9 09:17:55 2024 -0600 [committed] [RISC-V] Fix false-positive uninitialized variable Andreas noted we were getting an uninit war

[gcc r14-11549] RISC-V: Move fortran testcase to gfortran.target

https://gcc.gnu.org/g:af3ebb414e2b88973d570e8878bc6262c0a1b3a9 commit r14-11549-gaf3ebb414e2b88973d570e8878bc6262c0a1b3a9 Author: Kito Cheng Date: Mon Dec 23 21:27:46 2024 +0800 RISC-V: Move fortran testcase to gfortran.target gcc/testsuite/ChangeLog: * gcc.target

[gcc r14-11569] [RISC-V][PR target/116240] Ensure object is a comparison before extracting arguments

https://gcc.gnu.org/g:86b0f63adb0815b40705051484dcb7ac640d commit r14-11569-g86b0f63adb0815b40705051484dcb7ac640d Author: Jeff Law Date: Thu Aug 8 07:42:26 2024 -0600 [RISC-V][PR target/116240] Ensure object is a comparison before extracting arguments This was supposed to

[gcc r14-11553] [PATCH] riscv: add mising masking in lrsc expander (PR118137)

https://gcc.gnu.org/g:46732eb89db2f5124f9433ef9460ff301ab7d737 commit r14-11553-g46732eb89db2f5124f9433ef9460ff301ab7d737 Author: Andreas Schwab Date: Tue Jan 7 12:23:37 2025 -0700 [PATCH] riscv: add mising masking in lrsc expander (PR118137) gcc: PR target/118137

[gcc r14-11574] RISC-V: Bugfix for max_sew_overlap_and_next_ratio_valid_for_prev_sew_p[pr117483]

https://gcc.gnu.org/g:6cd78e383a98553482811f10318ff3da9a101d38 commit r14-11574-g6cd78e383a98553482811f10318ff3da9a101d38 Author: xuli Date: Tue Nov 12 02:31:28 2024 + RISC-V: Bugfix for max_sew_overlap_and_next_ratio_valid_for_prev_sew_p[pr117483] This patch fixs https://gcc

[gcc r14-11565] RISC-V: Fix subreg of VLS modes larger than a vector [PR116086].

https://gcc.gnu.org/g:e19a21f8edda3de1e460094e54239928bd289a31 commit r14-11565-ge19a21f8edda3de1e460094e54239928bd289a31 Author: Robin Dapp Date: Tue Aug 27 10:25:34 2024 +0200 RISC-V: Fix subreg of VLS modes larger than a vector [PR116086]. When the source mode is potentially la

[gcc r14-11550] RISC-V: Fix code gen for reduction with length 0 [PR118182]

https://gcc.gnu.org/g:1eb6bf312839d0ff6f0f1a246f9b0b715d1c4b7a commit r14-11550-g1eb6bf312839d0ff6f0f1a246f9b0b715d1c4b7a Author: Kito Cheng Date: Mon Dec 23 23:23:44 2024 +0800 RISC-V: Fix code gen for reduction with length 0 [PR118182] `.MASK_LEN_FOLD_LEFT_PLUS`(or `mask_len_fol

[gcc r14-11556] RISC-V: Add assert for insn operand out of range access [PR117878][NFC]

https://gcc.gnu.org/g:acb636a9c3ac18e7234e37c99bd6e9200b80b9bd commit r14-11556-gacb636a9c3ac18e7234e37c99bd6e9200b80b9bd Author: Pan Li Date: Wed Dec 4 13:53:52 2024 +0800 RISC-V: Add assert for insn operand out of range access [PR117878][NFC] According to the the initial analysi

[gcc r14-11548] [PR target/118357] RISC-V: Disable fusing vsetvl instructions by VSETVL_VTYPE_CHANGE_ONLY for XThead

https://gcc.gnu.org/g:e4586ae318436d63aa91c2d417f068987c77e442 commit r14-11548-ge4586ae318436d63aa91c2d417f068987c77e442 Author: Jin Ma Date: Sat Jan 18 07:43:17 2025 -0700 [PR target/118357] RISC-V: Disable fusing vsetvl instructions by VSETVL_VTYPE_CHANGE_ONLY for XTheadVector.

[gcc r14-11551] RISC-V: Fix vsetvl compatibility predicate [PR118154].

https://gcc.gnu.org/g:6f549f865d02f897f682dddf56f392a22c01df6c commit r14-11551-g6f549f865d02f897f682dddf56f392a22c01df6c Author: Robin Dapp Date: Thu Jan 9 20:45:10 2025 +0100 RISC-V: Fix vsetvl compatibility predicate [PR118154]. In PR118154 we emit strided stores but the first

[gcc r15-9130] RISC-V: Tweak testcase for PIE

https://gcc.gnu.org/g:fe1e8966cb5483c4e77d7d7bbea7acb0c191cff0 commit r15-9130-gfe1e8966cb5483c4e77d7d7bbea7acb0c191cff0 Author: Kito Cheng Date: Tue Apr 1 09:14:51 2025 +0800 RISC-V: Tweak testcase for PIE Linux toolchain may configured with --enable-default-pie, and that will

[gcc r15-9118] RISC-V: testsuite: Fix broken testsuite error of zicbop

https://gcc.gnu.org/g:954708cf02adc01d3af9d7d4a860377e985cc9af commit r15-9118-g954708cf02adc01d3af9d7d4a860377e985cc9af Author: Liao Shihua Date: Mon Mar 31 16:53:27 2025 +0800 RISC-V: testsuite: Fix broken testsuite error of zicbop Fix broken testsuite like "ERROR: gcc.targe

[gcc r15-9116] RISC-V: Fix wrong LMUL when only implict zve32f.

https://gcc.gnu.org/g:28751389a68e131e21fcaf8e3f661d76a2b4d0cc commit r15-9116-g28751389a68e131e21fcaf8e3f661d76a2b4d0cc Author: Monk Chiang Date: Tue Feb 4 15:29:17 2025 +0800 RISC-V: Fix wrong LMUL when only implict zve32f. According to Section 3.4.2, Vector Register Grouping, i

[gcc r15-7681] RISC-V: Fix .cfi_offset directive when push/pop in zcmp

https://gcc.gnu.org/g:4dcd3c7749734133f7f59509b1a118f3a13de4ee commit r15-7681-g4dcd3c7749734133f7f59509b1a118f3a13de4ee Author: Lino Hsing-Yu Peng Date: Thu Feb 20 17:09:22 2025 +0800 RISC-V: Fix .cfi_offset directive when push/pop in zcmp The incorrect cfi directive info breaks

[gcc r15-7037] RISC-V: Add sifive_vector.h

https://gcc.gnu.org/g:43a6001ff58d1e0da791b5f7f4c51aa2ed1e4493 commit r15-7037-g43a6001ff58d1e0da791b5f7f4c51aa2ed1e4493 Author: Kito Cheng Date: Wed Jan 15 16:13:05 2025 +0800 RISC-V: Add sifive_vector.h sifive_vector.h is a vendor specfic header, it should include before usi

[gcc r15-6948] RISC-V: Update Xsfvfnrclip implementation.

https://gcc.gnu.org/g:030aaea78c130a31d36d1dd56b0e8b90d973b522 commit r15-6948-g030aaea78c130a31d36d1dd56b0e8b90d973b522 Author: Jiawei Date: Fri Dec 13 20:38:28 2024 +0800 RISC-V: Update Xsfvfnrclip implementation. Update implementation of Xsfvfnrclip, using return type as iterat

[gcc r15-6949] RISC-V: Update Xsfvqmacc and Xsfvfnrclip's testcases

https://gcc.gnu.org/g:8682fcbf3ced5a415d3ff9a27d6c1fa0392bb187 commit r15-6949-g8682fcbf3ced5a415d3ff9a27d6c1fa0392bb187 Author: Liao Shihua Date: Fri Dec 13 20:38:29 2024 +0800 RISC-V: Update Xsfvqmacc and Xsfvfnrclip's testcases Update Sifive Xsfvqmacc and Xsfvfnrclip extension'

[gcc r15-6906] RISC-V: Fix code gen for reduction with length 0 [PR118182]

https://gcc.gnu.org/g:40ad10f708b19d3e88948ac820fbfb9f3c3689ae commit r15-6906-g40ad10f708b19d3e88948ac820fbfb9f3c3689ae Author: Kito Cheng Date: Mon Dec 23 23:23:44 2024 +0800 RISC-V: Fix code gen for reduction with length 0 [PR118182] `.MASK_LEN_FOLD_LEFT_PLUS`(or `mask_len_fold

[gcc r15-6564] RISC-V: Move fortran testcase to gfortran.target

https://gcc.gnu.org/g:a35b89a20ed6ef697867e9149474bcdc584cd969 commit r15-6564-ga35b89a20ed6ef697867e9149474bcdc584cd969 Author: Kito Cheng Date: Mon Dec 23 21:27:46 2024 +0800 RISC-V: Move fortran testcase to gfortran.target gcc/testsuite/ChangeLog: * gcc.target/

[gcc r15-6301] RISC-V: Add new constraint R for register even-odd pairs

https://gcc.gnu.org/g:fcbb8456a58ba073d4d5b10fcb9057b6e9a100db commit r15-6301-gfcbb8456a58ba073d4d5b10fcb9057b6e9a100db Author: Kito Cheng Date: Mon Dec 9 14:55:20 2024 +0800 RISC-V: Add new constraint R for register even-odd pairs Although this constraint is not currently used f

[gcc r15-6300] RISC-V: Implment N modifier for printing the register number rather than the register name

https://gcc.gnu.org/g:2a22db391d1819f6068aa43e63632b350a0b4bec commit r15-6300-g2a22db391d1819f6068aa43e63632b350a0b4bec Author: Kito Cheng Date: Thu Nov 14 17:24:45 2024 +0800 RISC-V: Implment N modifier for printing the register number rather than the register name The modifier

[gcc r15-6299] RISC-V: Rename internal operand modifier N to n

https://gcc.gnu.org/g:192790e994c9e15949e694e0a52010001b291611 commit r15-6299-g192790e994c9e15949e694e0a52010001b291611 Author: Kito Cheng Date: Thu Nov 14 16:41:52 2024 +0800 RISC-V: Rename internal operand modifier N to n Here is a purposal that using N for printing register en

[gcc r15-6298] RISC-V: Add cr and cf constraint

https://gcc.gnu.org/g:46888571d242cf5623b7b0b74bb4490572f81cc9 commit r15-6298-g46888571d242cf5623b7b0b74bb4490572f81cc9 Author: Kito Cheng Date: Wed Nov 13 17:54:16 2024 +0800 RISC-V: Add cr and cf constraint gcc/ChangeLog: * config/riscv/constraints.md (cr): New

[gcc r15-6297] RISC-V: Rename constraint c0* to k0*

https://gcc.gnu.org/g:1a2e0fcb857d82a7cb8909cf27a5dc833fecfa9a commit r15-6297-g1a2e0fcb857d82a7cb8909cf27a5dc833fecfa9a Author: Kito Cheng Date: Mon Dec 9 15:05:37 2024 +0800 RISC-V: Rename constraint c0* to k0* Rename those constraint since we want define other constraint start

[gcc r15-6006] Revert "RISC-V: Add const to function_shape::get_name [NFC]"

https://gcc.gnu.org/g:567b0405e38b0336a4416628424c97c67d0e92b3 commit r15-6006-g567b0405e38b0336a4416628424c97c67d0e92b3 Author: Kito Cheng Date: Sat Dec 7 08:23:58 2024 +0800 Revert "RISC-V: Add const to function_shape::get_name [NFC]" This reverts commit 9bf4cad4e4e1ec92c320a619

[gcc r15-5967] RISC-V: Add --with-cmodel configure option

https://gcc.gnu.org/g:feea589d78fd5ebe1c02cf937e184d2c66cd99ed commit r15-5967-gfeea589d78fd5ebe1c02cf937e184d2c66cd99ed Author: Hau Hsu Date: Fri Aug 2 13:11:51 2024 +0800 RISC-V: Add --with-cmodel configure option Sometimes we want to use default cmodel other than medlow. Add a

[gcc r15-5931] RISC-V: Add const to function_shape::get_name [NFC]

https://gcc.gnu.org/g:9bf4cad4e4e1ec92c320a619c9bad35535596ced commit r15-5931-g9bf4cad4e4e1ec92c320a619c9bad35535596ced Author: Kito Cheng Date: Tue Dec 3 00:44:09 2024 -0800 RISC-V: Add const to function_shape::get_name [NFC] function_shape::get_name is the funciton for building

[gcc r15-5861] RISC-V: Add intrinsics testcases for SiFive Xsfvfnrclipxfqf extensions.

https://gcc.gnu.org/g:275197057677406d575bfdbffa259ba7225e671f commit r15-5861-g275197057677406d575bfdbffa259ba7225e671f Author: yulong Date: Mon Dec 2 09:31:54 2024 +0800 RISC-V: Add intrinsics testcases for SiFive Xsfvfnrclipxfqf extensions. This commit adds testcases for Xsfvfn

[gcc r15-5860] RISC-V: Add intrinsics support for SiFive Xsfvfnrclipxfqf extensions.

https://gcc.gnu.org/g:1352d4dd09293faf170072269fcef3aa6694d6ae commit r15-5860-g1352d4dd09293faf170072269fcef3aa6694d6ae Author: yulong Date: Mon Dec 2 09:31:53 2024 +0800 RISC-V: Add intrinsics support for SiFive Xsfvfnrclipxfqf extensions. This commit adds intrinsics support for

[gcc r15-5794] RISC-V: Add intrinsics testcases for SiFive Xsfvqmaccqoq/dod extensions.

https://gcc.gnu.org/g:fe29b03825c9971ef1726bf9c7288de3389511b3 commit r15-5794-gfe29b03825c9971ef1726bf9c7288de3389511b3 Author: yulong Date: Thu Nov 28 10:36:05 2024 +0800 RISC-V: Add intrinsics testcases for SiFive Xsfvqmaccqoq/dod extensions. This commit adds testcases for Xsfv

[gcc r15-5793] RISC-V: Add intrinsics support for SiFive Xsfvqmaccqoq/dod extensions.

https://gcc.gnu.org/g:356bfe8ca123954e524a9d09dd8bba5ae8474a2d commit r15-5793-g356bfe8ca123954e524a9d09dd8bba5ae8474a2d Author: yulong Date: Thu Nov 28 10:36:04 2024 +0800 RISC-V: Add intrinsics support for SiFive Xsfvqmaccqoq/dod extensions. This commit adds intrinsics support f

[gcc r15-5645] RISC-V: Use dynamic shadow offset

https://gcc.gnu.org/g:c84a8a274af3163a4042bcfd77dd1988bd1eb0ce commit r15-5645-gc84a8a274af3163a4042bcfd77dd1988bd1eb0ce Author: Kito Cheng Date: Fri Nov 15 12:14:55 2024 +0800 RISC-V: Use dynamic shadow offset Switch to dynamic offset so that we can support Sv39, Sv48, and Sv57 a

[gcc r15-5644] asan: Support dynamic shadow offset

https://gcc.gnu.org/g:63c68752768fd6d67c695e09c85e0e1ca59cd6d4 commit r15-5644-g63c68752768fd6d67c695e09c85e0e1ca59cd6d4 Author: Kito Cheng Date: Fri Nov 15 12:14:54 2024 +0800 asan: Support dynamic shadow offset AddressSanitizer has supported dynamic shadow offsets since 2016[1],

[gcc r15-5643] RISC-V: Minimal support for svvptc extension.

https://gcc.gnu.org/g:e4f4b2dc08b6720acab563db48fd4b0427d2b0c6 commit r15-5643-ge4f4b2dc08b6720acab563db48fd4b0427d2b0c6 Author: Dongyan Chen Date: Fri Nov 22 13:13:46 2024 +0800 RISC-V: Minimal support for svvptc extension. This patch support svvptc extension[1]. To enable GC

[gcc r15-5483] RISC-V: Add the mini support for SiFive extensions.

https://gcc.gnu.org/g:139bd3198a738a1d49cd27f37bab16c1916f3164 commit r15-5483-g139bd3198a738a1d49cd27f37bab16c1916f3164 Author: yulong Date: Sun Nov 17 17:55:30 2024 +0800 RISC-V: Add the mini support for SiFive extensions. This patch add the mini support for xsfvqmaccqoq, xsfvqm

[gcc r15-5199] RISC-V: Implement TARGET_GENERATE_VERSION_DISPATCHER_BODY and TARGET_GET_FUNCTION_VERSIONS_DISPATCHE

https://gcc.gnu.org/g:917d03e4f366f7738684bed2eae02482b535b7fc commit r15-5199-g917d03e4f366f7738684bed2eae02482b535b7fc Author: Yangyu Chen Date: Tue Nov 5 11:23:07 2024 +0800 RISC-V: Implement TARGET_GENERATE_VERSION_DISPATCHER_BODY and TARGET_GET_FUNCTION_VERSIONS_DISPATCHER T

[gcc r15-5193] Introduce TARGET_CLONES_ATTR_SEPARATOR for RISC-V

https://gcc.gnu.org/g:9bf0dbe67244fffc5cb939e51ead2876557c8c37 commit r15-5193-g9bf0dbe67244fffc5cb939e51ead2876557c8c37 Author: Yangyu Chen Date: Tue Nov 5 11:21:22 2024 +0800 Introduce TARGET_CLONES_ATTR_SEPARATOR for RISC-V Some architectures may use ',' in the attribute string

[gcc r15-5200] RISC-V: Add Multi-Versioning Test Cases

https://gcc.gnu.org/g:f42f8dcf495e0a17df95a71c6a91093532cb9f3b commit r15-5200-gf42f8dcf495e0a17df95a71c6a91093532cb9f3b Author: Yangyu Chen Date: Tue Nov 5 11:23:16 2024 +0800 RISC-V: Add Multi-Versioning Test Cases This patch adds test cases for the Function Multi-Versioning (FM

[gcc r15-5197] RISC-V: Implement TARGET_COMPARE_VERSION_PRIORITY and TARGET_OPTION_FUNCTION_VERSIONS

https://gcc.gnu.org/g:78753c75cf154e7432624e24c68aae3b81ed49f0 commit r15-5197-g78753c75cf154e7432624e24c68aae3b81ed49f0 Author: Yangyu Chen Date: Tue Nov 5 11:22:45 2024 +0800 RISC-V: Implement TARGET_COMPARE_VERSION_PRIORITY and TARGET_OPTION_FUNCTION_VERSIONS This patch implem

[gcc r15-5198] RISC-V: Implement TARGET_MANGLE_DECL_ASSEMBLER_NAME

https://gcc.gnu.org/g:0c77c4b082bf110fd2fc9c800268ac58fa579d06 commit r15-5198-g0c77c4b082bf110fd2fc9c800268ac58fa579d06 Author: Yangyu Chen Date: Tue Nov 5 11:22:56 2024 +0800 RISC-V: Implement TARGET_MANGLE_DECL_ASSEMBLER_NAME This patch implements the TARGET_MANGLE_DECL_ASSEMBL

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