https://gcc.gnu.org/g:5b3558944a7a03071744585ee8c55f30d51b5653
commit r14-11560-g5b3558944a7a03071744585ee8c55f30d51b5653
Author: Xianmiao Qu <cooper...@linux.alibaba.com>
Date: Wed Sep 18 07:28:44 2024 -0600
[PATCH] RISC-V: Fix th.extu operands exceeding range on rv32.
The Combine Pass may generate zero_extract instructions that are out of
range.
Drawing from other architectures like AArch64, we should impose restrictions
on the "*th_extu<mode>4" pattern.
gcc/
* config/riscv/thead.md (*th_extu<mode>4): Fix th.extu
operands exceeding range on rv32.
gcc/testsuite/
* gcc.target/riscv/xtheadbb-extu-4.c: New.
Diff:
---
gcc/config/riscv/thead.md | 4 +++-
gcc/testsuite/gcc.target/riscv/xtheadbb-extu-4.c | 17 +++++++++++++++++
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
index 5c7d4beb1b66..2bbbb45386a1 100644
--- a/gcc/config/riscv/thead.md
+++ b/gcc/config/riscv/thead.md
@@ -85,7 +85,9 @@
(zero_extract:GPR (match_operand:GPR 1 "register_operand" "r")
(match_operand 2 "const_int_operand")
(match_operand 3 "const_int_operand")))]
- "TARGET_XTHEADBB"
+ "TARGET_XTHEADBB
+ && (UINTVAL (operands[2]) + UINTVAL (operands[3])
+ <= GET_MODE_BITSIZE (<MODE>mode))"
{
operands[2] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3]) - 1);
return "th.extu\t%0,%1,%2,%3";
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-extu-4.c
b/gcc/testsuite/gcc.target/riscv/xtheadbb-extu-4.c
new file mode 100644
index 000000000000..41d3fc1f5b40
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-extu-4.c
@@ -0,0 +1,17 @@
+/* { dg-do compile { target { rv32 } } } */
+/* { dg-options "-march=rv32gc_xtheadbb" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Os" "-Og" "-Oz" } } */
+
+struct c {
+ int f : 25;
+} d;
+
+int b;
+extern unsigned int e[];
+
+void g()
+{
+ d.f = e[2] >> (b << ~4194303 + 4194332) - 58096371;
+}
+
+/* { dg-final { scan-assembler-not {th.extu\t[ax][0-9]+,[ax][0-9]+,37,13} } }
*/
\ No newline at end of file
