[gcc r15-6299] RISC-V: Rename internal operand modifier N to n

[Kito Cheng via Gcc-cvs]

https://gcc.gnu.org/g:192790e994c9e15949e694e0a52010001b291611

commit r15-6299-g192790e994c9e15949e694e0a52010001b291611
Author: Kito Cheng <kito.ch...@sifive.com>
Date:   Thu Nov 14 16:41:52 2024 +0800

    RISC-V: Rename internal operand modifier N to n
    
    Here is a purposal that using N for printing register encoding number,
    so let rename the existing internal operand modifier `N` to `n`.
    
    gcc/ChangeLog:
    
            * config/riscv/corev.md (*cv_branch<mode>): Update modifier.
            (*branch<mode>): Ditto.
            * config/riscv/riscv.cc (riscv_print_operand): Update modifier.
            * config/riscv/riscv.md (*branch<mode>): Update modifier.

Diff:
---
 gcc/config/riscv/corev.md | 4 ++--
 gcc/config/riscv/riscv.cc | 4 ++--
 gcc/config/riscv/riscv.md | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index 02c270433017..3c0e9cecdfba 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -2627,7 +2627,7 @@
   "TARGET_XCVBI"
 {
   if (get_attr_length (insn) == 12)
-    return "cv.b%N1\t%2,%z3,1f; jump\t%l0,ra; 1:";
+    return "cv.b%n1\t%2,%z3,1f; jump\t%l0,ra; 1:";
 
   return "cv.b%C1imm\t%2,%3,%0";
 }
@@ -2645,7 +2645,7 @@
   "TARGET_XCVBI"
 {
   if (get_attr_length (insn) == 12)
-    return "b%N1\t%2,%z3,1f; jump\t%l0,ra; 1:";
+    return "b%n1\t%2,%z3,1f; jump\t%l0,ra; 1:";
 
   return "b%C1\t%2,%z3,%l0";
 }
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 6492913d8f80..db2329c03193 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -6823,7 +6823,7 @@ riscv_asm_output_opcode (FILE *asm_out_file, const char 
*p)
          any outermost HIGH.
    'R' Print the low-part relocation associated with OP.
    'C' Print the integer branch condition for comparison OP.
-   'N' Print the inverse of the integer branch condition for comparison OP.
+   'n' Print the inverse of the integer branch condition for comparison OP.
    'A' Print the atomic operation suffix for memory model OP.
    'I' Print the LR suffix for memory model OP.
    'J' Print the SC suffix for memory model OP.
@@ -6981,7 +6981,7 @@ riscv_print_operand (FILE *file, rtx op, int letter)
       fputs (GET_RTX_NAME (code), file);
       break;
 
-    case 'N':
+    case 'n':
       /* The RTL names match the instruction names. */
       fputs (GET_RTX_NAME (reverse_condition (code)), file);
       break;
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 3a4cd1d93a0f..1eec51c117a7 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3215,7 +3215,7 @@
   "!TARGET_XCVBI"
 {
   if (get_attr_length (insn) == 12)
-    return "b%N1\t%2,%z3,1f; jump\t%l0,ra; 1:";
+    return "b%n1\t%2,%z3,1f; jump\t%l0,ra; 1:";
 
   return "b%C1\t%2,%z3,%l0";
 }