https://gcc.gnu.org/g:077cdc9dc0ff7f5c9d12829bfed220d1e63b1525
commit r16-949-g077cdc9dc0ff7f5c9d12829bfed220d1e63b1525
Author: Jerry Zhang Jian <jerry.zhangj...@sifive.com>
Date: Wed May 28 10:17:36 2025 +0800
RISC-V: Add minimal support of double trap extension 1.0
Add support of double trap extension [1], enabling GCC
to recognize the following extensions at compile time.
New extensions:
- ssdbltrp
- smdbltrp
[1]
https://github.com/riscv/riscv-double-trap/releases/download/v1.0/riscv-double-trap.pdf
gcc/ChangeLog:
* config/riscv/riscv-ext.def: New extensions
* config/riscv/riscv-ext.opt: Auto re-generated
* doc/riscv-ext.texi: Auto re-generated
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-57.c: New test
* gcc.target/riscv/arch-58.c: New test
Signed-off-by: Jerry Zhang Jian <jerry.zhangj...@sifive.com>
Diff:
---
gcc/config/riscv/riscv-ext.def | 26 ++++++++++++++++++++++++++
gcc/config/riscv/riscv-ext.opt | 4 ++++
gcc/doc/riscv-ext.texi | 8 ++++++++
gcc/testsuite/gcc.target/riscv/arch-57.c | 6 ++++++
gcc/testsuite/gcc.target/riscv/arch-58.c | 6 ++++++
5 files changed, 50 insertions(+)
diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index 97b576617add..dbda8ded3974 100644
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -1727,6 +1727,19 @@ DEFINE_RISCV_EXT(
/* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
/* EXTRA_EXTENSION_FLAGS */ 0)
+DEFINE_RISCV_EXT(
+ /* NAME */ smdbltrp,
+ /* UPPERCAE_NAME */ SMDBLTRP,
+ /* FULL_NAME */ "Double Trap Extensions",
+ /* DESC */ "",
+ /* URL */ ,
+ /* DEP_EXTS */ ({"zicsr"}),
+ /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+ /* FLAG_GROUP */ sm,
+ /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+ /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+ /* EXTRA_EXTENSION_FLAGS */ 0)
+
DEFINE_RISCV_EXT(
/* NAME */ ssaia,
/* UPPERCAE_NAME */ SSAIA,
@@ -1818,6 +1831,19 @@ DEFINE_RISCV_EXT(
/* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
/* EXTRA_EXTENSION_FLAGS */ 0)
+DEFINE_RISCV_EXT(
+ /* NAME */ ssdbltrp,
+ /* UPPERCAE_NAME */ SSDBLTRP,
+ /* FULL_NAME */ "Double Trap Extensions",
+ /* DESC */ "",
+ /* URL */ ,
+ /* DEP_EXTS */ ({"zicsr"}),
+ /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+ /* FLAG_GROUP */ ss,
+ /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+ /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+ /* EXTRA_EXTENSION_FLAGS */ 0)
+
DEFINE_RISCV_EXT(
/* NAME */ supm,
/* UPPERCAE_NAME */ SUPM,
diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index 9199aa31b420..5e9c5f56ad67 100644
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -343,6 +343,8 @@ Mask(SMNPM) Var(riscv_sm_subext)
Mask(SMSTATEEN) Var(riscv_sm_subext)
+Mask(SMDBLTRP) Var(riscv_sm_subext)
+
Mask(SSAIA) Var(riscv_ss_subext)
Mask(SSCOFPMF) Var(riscv_ss_subext)
@@ -357,6 +359,8 @@ Mask(SSTC) Var(riscv_ss_subext)
Mask(SSSTRICT) Var(riscv_ss_subext)
+Mask(SSDBLTRP) Var(riscv_ss_subext)
+
Mask(SUPM) Var(riscv_su_subext)
Mask(SVINVAL) Var(riscv_sv_subext)
diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index bd3d29c75ab5..7a22d841d1b6 100644
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -510,6 +510,10 @@
@tab 1.0
@tab State enable extension
+@item smdbltrp
+@tab 1.0
+@tab Double Trap Extensions
+
@item ssaia
@tab 1.0
@tab Advanced interrupt architecture extension for supervisor-mode
@@ -538,6 +542,10 @@
@tab 1.0
@tab ssstrict extension
+@item ssdbltrp
+@tab 1.0
+@tab Double Trap Extensions
+
@item supm
@tab 1.0
@tab supm extension
diff --git a/gcc/testsuite/gcc.target/riscv/arch-57.c
b/gcc/testsuite/gcc.target/riscv/arch-57.c
new file mode 100644
index 000000000000..08d3761a4700
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-57.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_smdbltrp -mabi=lp64" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch,
\"rv64i2p1_zicsr2p0_smdbltrp1p0\"" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/arch-58.c
b/gcc/testsuite/gcc.target/riscv/arch-58.c
new file mode 100644
index 000000000000..1481da5ecdbe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-58.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_ssdbltrp -mabi=lp64" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch,
\"rv64i2p1_zicsr2p0_ssdbltrp1p0\"" } } */
