[PATCH] D50043: [RISCV] RISC-V using -fuse-init-array by default

kito-cheng updated this revision to Diff 161990. kito-cheng added a comment. Herald added subscribers: jocewei, the_o, brucehoult, MartinMosbeck, mgrang, edward-jones, zzheng, niosHD, sabuasal, simoncook, johnrusso, rbar. Changes: - Add test. https://reviews.llvm.org/D50043 Files: lib/Drive

[PATCH] D44888: [RISCV] Default enable linker relaxation and add -mrelax, -mno-relax flags

kito-cheng added inline comments. Comment at: lib/Driver/ToolChains/Arch/RISCV.cpp:130 + // which may override the defaults. + handleTargetFeaturesGroup(Args, Features, options::OPT_m_riscv_Features_Group); } This part should move to the begin of the functio

[PATCH] D46822: [RISCV] Add driver for riscv32-unknown-elf baremetal target

kito-cheng added a comment. Herald added subscribers: rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, jrtc27. ping, Alex, could you commit that? Repository: rC Clang https://reviews.llvm.org/D46822 ___ cfe-commits mailing list cfe-commits@l

[PATCH] D50043: [RISCV] RISC-V using -fuse-init-array by default

kito-cheng created this revision. kito-cheng added reviewers: asb, apazos. Herald added subscribers: cfe-commits, rkruppe, rogfer01, shiva0217, fedor.sergeev. RISC-V target using -fuse-init-array even for bare-mental target. Repository: rC Clang https://reviews.llvm.org/D50043 Files: lib/

[PATCH] D43105: [RISCV] Enable __int128_t and uint128_t through clang flag

kito-cheng added a comment. Hi Eli: We need that because compiler-rt implement 128 bits soft floating point with int128_t, and RISC-V need that but RV32 doesn't support int128_t, we know it's can be just return true to support that. but we don't want to bring any ABI contemptible issue between

[PATCH] D43105: [RISCV] Enable __int128_t and uint128_t through clang flag

kito-cheng added a comment. Hi Eli: > but you want to make int128_t opt-in to avoid the possibility of someone > getting a link error trying to link code built with clang against libgcc.a? Yes, that's the problem we want to avoid, and we actually get the problem if we built libc (newlib) with

[PATCH] D43105: [RISCV] Enable __int128_t and uint128_t through clang flag

kito-cheng added inline comments. Comment at: lib/Basic/Targets/RISCV.h:85 + bool hasInt128Type(const LangOptions &Opts) const override { +return Opts.UseInt128; + } efriedma wrote: > Maybe make this a cross-platform flag, rather than riscv-specific? +1, th

[PATCH] D44189: [RISCV] Verify the input value of -march=

kito-cheng created this revision. kito-cheng added reviewers: asb, apazos. Herald added subscribers: cfe-commits, shiva0217, niosHD, sabuasal, jordy.potman.lists, simoncook, johnrusso, rbar. This patch doing more check and verify the -march= string and will issue and error if it's a invalid comb

[PATCH] D44189: [RISCV] Verify the input value of -march=

kito-cheng updated this revision to Diff 137547. Repository: rC Clang https://reviews.llvm.org/D44189 Files: lib/Driver/ToolChains/Arch/RISCV.cpp test/Driver/riscv-arch.c Index: test/Driver/riscv-arch.c === --- /dev/null +++

[PATCH] D44189: [RISCV] Verify the input value of -march=

kito-cheng marked 2 inline comments as done. kito-cheng added inline comments. Comment at: lib/Driver/ToolChains/Arch/RISCV.cpp:48 + break; +default: + // First letter should be 'i' or 'g'. apazos wrote: > In the switch cases move default to first p

[PATCH] D44189: [RISCV] Verify the input value of -march=

kito-cheng updated this revision to Diff 137687. kito-cheng added a comment. This version only update variable name which changed in last version by accident. https://reviews.llvm.org/D44189 Files: lib/Driver/ToolChains/Arch/RISCV.cpp test/Driver/riscv-arch.c Index: test/Driver/riscv-arch

[PATCH] D44189: [RISCV] Verify the input value of -march=

kito-cheng updated this revision to Diff 137970. kito-cheng added a comment. Add test cases for the correct inputs. https://reviews.llvm.org/D44189 Files: lib/Driver/ToolChains/Arch/RISCV.cpp test/Driver/riscv-arch.c Index: test/Driver/riscv-arch.c =

[PATCH] D67409: [RISCV] enable LTO support, pass some options to linker.

kito-cheng added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:387 + +void riscv::addGoldOptions(const ToolChain &ToolChain, + const llvm::opt::ArgList &Args, MaskRay wrote: > gold doesn't support RISC-V, does i

[PATCH] D67508: [RISCV] support mutilib in baremetal environment

kito-cheng added inline comments. Comment at: clang/lib/Driver/ToolChains/Gnu.cpp:1548 +{M.gccSuffix(), + "/../../../../riscv64-unknown-elf/lib" + M.gccSuffix()}); + }); It could be "riscv32-unknown-elf" other than "riscv6

[PATCH] D71124: [RISCV] support clang driver to select cpu

kito-cheng added a comment. Another proposal for -mcpu and -mtune: Decoupling the -mcpu and -mtune option, -mcpu only accept concrete CPU, and -mtune for micro-arch/pipeline model, they accept different option set. e.g. -mcpu=sifive-e24 # Imply -march=rv32imafc -mtune=sifive-2-series -mtune=sif

[PATCH] D71124: [RISCV] support clang driver to select cpu

kito-cheng added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:478 // 1. Explicit choices using `--with-abi=` - // 2. A default based on `--with-arch=`, if provided - // 3. A default based on the target triple's arch + // 2. A default based on arch

[PATCH] D132843: [RISCV] Ensure target features get passed to the LTO linker for RISC-V

kito-cheng added a subscriber: khchen. kito-cheng added a comment. This is dump from my mailbox, few month ago I written a offlist mail to describe about RISC-V LTO status: --- LTO for RISC-V is really kind of a long long story. @khchen has been fighting for that for a long time, but he is no

[PATCH] D132843: [RISCV] Ensure target features get passed to the LTO linker for RISC-V

kito-cheng added a comment. > I'm not sure how the issues with datalayout in particular end up being an > issue in practice. > > clang shouldn't be writing out object files without a datalayout. > The code to infer alignment on load/store/etc. only exists for compatibility > with old bitcode/IR;

[PATCH] D132192: [RISCV] Add '32bit' feature to rv32 only builtins.

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, and +1 for the error message improvement, but could be separated patch. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D132192/new/

[PATCH] D128726: [RISCV][NFC] Move static global variables into static variable in function.

kito-cheng created this revision. Herald added subscribers: sunshaoce, VincentWu, luke957, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, niosHD, s

[PATCH] D128726: [RISCV][NFC] Move static global variables into static variable in function.

kito-cheng added a comment. My understanding is the reason why no global variable is because 1. the initialization order and 2. might increase the launch time of programs, moving that into function scope could resolve both issue: 1. initialized in deterministic order[1], 2. Initialized that whe

[PATCH] D128625: [RISCV][Driver] Fix baremetal `GCCInstallation` paths

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, `riscv*-unknown-unknown` match `riscv*-unknown-elf` sound make more sense than `riscv*-unknown-linux-gnu` :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION h

[PATCH] D128726: [RISCV][NFC] Move static global variables into static variable in function.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG1b8cde9b6338: [RISCV][NFC] Move static global variables into static variable in function. (authored by kito-cheng). Repository: rG LLVM Github Mon

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

kito-cheng updated this revision to Diff 441320. kito-cheng added a comment. Changes: - Rebase - Address @khchen's comment Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111617/new/ https://reviews.llvm.org/D111617 Files: clang/include/clang/Bas

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

kito-cheng updated this revision to Diff 441610. kito-cheng marked 24 inline comments as done. kito-cheng added a comment. Changes: - Address @craig.topper's comment - Address @khchen's comment Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111617/n

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

kito-cheng added inline comments. Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:114 bool operator>(const PrototypeDescriptor &PD) const { -return !(PD.PT <= PT && PD.VTM <= VTM && PD.TM <= TM); +if (PD.PT != PT) + return PD.PT > PT; --

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

kito-cheng marked an inline comment as done. kito-cheng added a comment. Oh, have one comment not address yet Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111617/new/ https://reviews.llvm.org/D111617 __

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

kito-cheng updated this revision to Diff 441684. kito-cheng added a comment. Changes: - Address @craig.topper's comment - Introduce RISCVIntrinsicManager.h and let it become member of Sema, that make sure the it won't outlive than Sema. Repository: rG LLVM Github Monorepo CHANGES SINCE LA

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

kito-cheng updated this revision to Diff 441692. kito-cheng marked 18 inline comments as done. kito-cheng added a comment. Changes: - Address @aaron.ballman’s comment - Add 2 new testcase: - riscv-bad-intrnisic-pragma.c - riscv-intrnisic-pragma.c Repository: rG LLVM Github Monorepo

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

kito-cheng added inline comments. Comment at: clang/lib/Parse/ParsePragma.cpp:3963 +<< PP.getSpelling(Tok) << "riscv" << /*Expected=*/true << "'intrinsic'"; +return; + } aaron.ballman wrote: > It's fine to warn on this, but then you need to eat toke

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

kito-cheng updated this revision to Diff 442025. kito-cheng marked 9 inline comments as done. kito-cheng added a comment. Changes: - Address @frasercrmck's comment Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111617/new/ https://reviews.llvm.org/

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

kito-cheng added inline comments. Comment at: clang/lib/Sema/SemaRISCVVectorLookup.cpp:100 +switch (Type->getElementBitwidth()) { +case 64: + QT = Context.DoubleTy; aaron.ballman wrote: > kito-cheng wrote: > > aaron.ballman wrote: > > > I almost hate

[PATCH] D129043: [RISCV][Clang] Teach RISCVEmitter to generate BitCast for pointer operands.

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, thanks for clean this up :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D129043/new/ https://reviews.llvm.org/D129043 __

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

kito-cheng updated this revision to Diff 442429. kito-cheng added a comment. Changes: - Less invasive way to fix this issue. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111617/new/ https://reviews.llvm.org/D111617 Files: llvm/lib/Target/RISCV

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

kito-cheng updated this revision to Diff 442431. kito-cheng added a comment. Changes: Restore the patch, I just accidentally updated wrong revision here... Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111617/new/ https://reviews.llvm.org/D111617

[PATCH] D121984: [RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGad57e10dbca2: [RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support (authored by kito-cheng). Changed prior to commit: https://revie

[PATCH] D121984: [RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support

kito-cheng added a subscriber: akuegel. kito-cheng added a comment. Hi @MaskRay, @akuegel has removed the `llvm/TableGen/*`, so I guess the issue you mentioned in https://github.com/llvm/llvm-project/commit/c0eb9b4cdef6049ebabb4018d3c9dcb0dc699868 is resolved by https://github.com/llvm/llvm-pr

[PATCH] D122629: [RISCV] Add index check for vset/vget

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, thanks :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D122629/new/ https://reviews.llvm.org/D122629

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

kito-cheng marked 9 inline comments as done. kito-cheng added a comment. @aaron.ballman thanks for your review! Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:400 + // Number of fields, greater than 1 if it's segment load/store. + uint8_t NF; +}; -

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

This revision was not accepted when it landed; it landed in state "Needs Review". This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. kito-cheng marked an inline comment as done. Closed by commit rG7a5cb15ea6fa: [RISCV]

[PATCH] D126744: [RISCV][Clang] Support policy functions for vneg, vnot, vncvt, vwcvt, vwcvtu, vfabs and vfneg.

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, and verified with internal testsuite :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D126744/new/ https://reviews.llvm.org/D126744

[PATCH] D126745: [RISCV][Clang] Support policy functions for vmerge, vfmerge and vcompress.

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. Herald added a subscriber: nlopes. LGTM, and verified with internal testsuite :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D126745/new

[PATCH] D126748: [RISCV][Clang] Support policy functions for Vector Reduction Instructions.

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. Herald added a subscriber: nlopes. LGTM, and verified with internal testsuite :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D126748/new

[PATCH] D126750: [RISCV][Clang] Support policy function for all vector segment load.

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. Herald added a subscriber: nlopes. LGTM, and verified with internal testsuite :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D126750/new

[PATCH] D126742: [RISCV][Clang] Support RVV policy functions.

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, and verified with internal testsuite :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D126742/new/ https://reviews.llvm.org/D126742

[PATCH] D130311: [RISCV] Enable strict FP in clang as long as Zve* or V are not enabled.

kito-cheng added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:286 + // StrictFP support for vectors is incomplete. + if (ISAInfo->hasExtension("zve32x")) +HasStrictFP = false; craig.topper wrote: > reames wrote: > > craig.topper wrote: > >

[PATCH] D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way

kito-cheng added a comment. Just realized the problem is trying to fixed the default value of `-mabi=`, currently `clang -target riscv32-elf -march=rv64gc -mabi=lp64d`/`riscv32-elf-clang -march=rv64gc -mabi=lp64d` is work, and match the behavior of GCC did, `riscv32-elf-gcc -march=rv64gc -mabi=

[PATCH] D131345: [RISC-V][HWASAN] Enable HWASAN for RISC-V architecture

kito-cheng added a comment. I guess we should checking `J` extension is enabled somewhere when user trying to enable HWASAN? or checking that at HWASAN library at run-time? otherwise my understanding is user will get crash when enabling HWASAN if linux and/or HW don't support that? Repository

[PATCH] D105690: [RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change

kito-cheng added inline comments. Comment at: llvm/test/MC/RISCV/rvv/aliases.s:86 +# NO-ALIAS: vfwredusum.vs v8, v4, v20, v0.t # encoding: [0x57,0x14,0x4a,0xc4] +vfwredusum.vs v8, v4, v20, v0.t I guess you want to verify `vfredsum.vs` and `vfwredsum.vs` here?

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng marked 2 inline comments as done. kito-cheng added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:460 + +addExtension("e"); + } khchen wrote: > nit: add `break;` to avoid the implicit-fallthrough warning. Oh, thanks, it seems like

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng updated this revision to Diff 360842. kito-cheng marked an inline comment as done. kito-cheng added a comment. Changes: - Address @khchen's comment. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105168/new/ https://reviews.llvm.org/D105

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng updated this revision to Diff 361137. kito-cheng added a comment. Changes: - New function RISCVISAInfo::isSupportedExtensionFeature - Remove parameter CheckExperimental from RISCVISAInfo::isSupportedExtension - Clean up obvious comments - Address @jrtc27's and @craig.topper's comments

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng marked 8 inline comments as done. kito-cheng added inline comments. Comment at: clang/test/Driver/riscv-arch.c:198-201 -// RUN: %clang -target riscv32-unknown-elf -march=rv32e -### %s \ -// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32E %s -// RV32E: error: in

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng updated this revision to Diff 361141. kito-cheng marked an inline comment as done. kito-cheng added a comment. Changes: - Rename RISCVISAInfo::parse to RISCVISAInfo::parseFeatures/RISCVISAInfo::parseArchString Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https:

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng marked an inline comment as done. kito-cheng added inline comments. Comment at: llvm/include/llvm/Support/RISCVISAInfo.h:45 + + // Parse RISCV ISA info from arch string. + Error parse(StringRef Arch, bool EnableExperimentalExtension, jrtc27 wrote: >

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng updated this revision to Diff 361915. kito-cheng marked an inline comment as done. kito-cheng added a comment. Changes: - Address @frasercrmck's comment Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105168/new/ https://reviews.llvm.org/

[PATCH] D121431: Split up large test files(over 10k lines) under clang/test/CodeGen/RISCV including:

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D121431/new/ https://reviews.llvm.org/D121431 __

[PATCH] D121345: [RISCV] Add +experimental-zvfh extension to cover half types in vectors.

kito-cheng added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:727 + if (Exts.count("zvfh") && !Exts.count("zfh") && !Exts.count("zhinx")) +return createStringError( Zvfh require `Zfhmin` rather than `Zfh` Spec: `The Zvfh extension additi

[PATCH] D121345: [RISCV] Add +experimental-zvfh extension to cover half types in vectors.

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. Herald added subscribers: s, arichardson. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D121345/new/ https://reviews.llvm.org/D12134

[PATCH] D121984: [RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support

kito-cheng created this revision. Herald added subscribers: s, VincentWu, luke957, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook,

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

kito-cheng added a comment. > If I understand correctly, E can't be combined with D in current > specification since E must use ILP32E calling convention. Calling convention and extensions are separated, calling convention are specify the how argument passing and the register convention, so ILP

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

kito-cheng added a comment. Last LLVM sync-up call @asb has raise the discussion about the ILP32E issue, so here is note from my site: RISC-V psABI doc still say "we don't guarantee the stability of `ILP32E`", the reason is RV32E still not a ratified extension, but as psABI chair, what I can

[PATCH] D121984: [RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support

kito-cheng added a comment. Oh, apology, I guess I just miss the discussion, let me revert that again. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D121984/new/ https://reviews.llvm.org/D121984 ___ cfe-c

[PATCH] D121984: [RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support

kito-cheng updated this revision to Diff 421477. kito-cheng added a comment. Changes: - Move those stuffs into clang/Support instead of llvm/Support - Keep table gen staffs in clang/utils/TableGen/RISCVVEmitter.cpp Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://revie

[PATCH] D121984: [RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support

kito-cheng added a comment. @MaskRay I've move those stuffs into clang/Support which is introduce by this patch, and also keep those table gen stuffs in clang-tblgen, did you mind take a look? Thanks :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.or

[PATCH] D121984: [RISCV] Moving RVV intrinsic type related util to clang/Support

kito-cheng added a comment. Hi @aaron.ballman: > Why shouldn't this live in clang/utils/TableGen along with the others? We plan to use those stuffs on clang side in https://reviews.llvm.org/D111617, my original change was put those stuffs on `llvm/Support`, but actually those stuffs are only u

[PATCH] D121984: [RISCV] Moving RVV intrinsic type related util to clang/Support

kito-cheng updated this revision to Diff 422783. kito-cheng added a comment. Fix comment in RISCVVIntrinsicUtils.h Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D121984/new/ https://reviews.llvm.org/D121984 Files: clang/include/clang/Support/RISC

[PATCH] D121984: [RISCV] Moving RVV intrinsic type related util to clang/Support

kito-cheng updated this revision to Diff 422786. kito-cheng marked an inline comment as done. kito-cheng added a comment. Fix comment in RISCVVIntrinsicUtils.h...again :P Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D121984/new/ https://reviews.llv

[PATCH] D121984: [RISCV] Moving RVV intrinsic type related util to clang/Support

kito-cheng added a comment. > Thank you for the explanation. I still don't think this is really "Support" > material, but I'm also struggling to think of a better place to put it in an > existing directory in Clang aside from Basic, but that would still be a bit > of a layering violation it fee

[PATCH] D121984: [RISCV] Moving RVV intrinsic type related util to clang/Support

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGf26c41e8dd28: [RISCV] Moving RVV intrinsic type related util to clang/Support (authored by kito-cheng). Changed prior to commit: https://reviews.l

[PATCH] D118225: [RISCV] Decouple Zve* extensions.

kito-cheng added a comment. Discussion on riscv-v-spec : https://github.com/riscv/riscv-v-spec/issues/723#issuecomment-922153867, although v-spec and isa-spec still not clearly describe that, but seems ISA folks prefer having those implication relationship between those zve* and v extensions.

[PATCH] D119250: [RISCV][NFC] Refactor RISCVISAInfo.

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D119250/new/ https://reviews.llvm.org/D119250 ___

[PATCH] D119837: [RISCV] Fix the include search path order between sysroot and resource folder

kito-cheng created this revision. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, abidh, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, j

[PATCH] D124348: [1/2][RISCV]Add Intrinsics for B extension in Clang

kito-cheng added a comment. > And I want to know that do you have any documents about intrinsic of bitmanip > extension, like RISC-V Vector Extension Intrinsic Document. No, we didn't a formal document for that, I expect we will have one once this finalized https://github.com/riscv-non-isa/risc

[PATCH] D124509: [RISCV] Fix int16 -> __fp16 conversion code gen

kito-cheng created this revision. Herald added subscribers: sunshaoce, VincentWu, luke957, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal, si

[PATCH] D124510: [RISCV] Precommit test for D124509

kito-cheng created this revision. Herald added subscribers: sunshaoce, VincentWu, luke957, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal, si

[PATCH] D124510: [RISCV] Precommit test for D124509

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG02c7de3a4c32: [RISCV] Precommit test for D124509 (authored by kito-cheng). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https:

[PATCH] D124509: [RISCV] Fix int16 -> __fp16 conversion code gen

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG41b951c92931: [RISCV] Fix int16 -> __fp16 conversion code gen (authored by kito-cheng). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST AC

[PATCH] D124730: [RISCV][NFC] Refactor RISC-V vector intrinsic utils.

kito-cheng created this revision. Herald added subscribers: sunshaoce, VincentWu, luke957, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal, si

[PATCH] D124730: [RISCV][NFC] Refactor RISC-V vector intrinsic utils.

kito-cheng updated this revision to Diff 426276. kito-cheng added a comment. Changes: - Extract more utils functions to RISCVVIntrinsicUtils Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D124730/new/ https://reviews.llvm.org/D124730 Files: clang

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

kito-cheng updated this revision to Diff 426281. kito-cheng marked 2 inline comments as done. kito-cheng added a comment. Changes: - Split out refactor part to D124730 . - Add more comment. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION http

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

kito-cheng updated this revision to Diff 426284. kito-cheng marked 4 inline comments as done. kito-cheng added a comment. Changes: - Add more comments. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111617/new/ https://reviews.llvm.org/D111617 Fil

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

kito-cheng added inline comments. Comment at: clang/lib/Sema/SemaRVVLookup.cpp:91 +struct RVVIntrinsicDef { + std::string Name; + std::string GenericName; khchen wrote: > why do we need to declare Name as std::string here but RVVIntrinsicRecord use > `const ch

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

kito-cheng updated this revision to Diff 426285. kito-cheng marked 2 inline comments as done. kito-cheng added a comment. Changes: - Minor tweak. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111617/new/ https://reviews.llvm.org/D111617 Files:

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

kito-cheng updated this revision to Diff 444188. kito-cheng added a comment. Changes: - Correct filename for testcases. - Use forward declaration for llvm::raw_ostream Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111617/new/ https://reviews.llvm.

[PATCH] D130190: [Driver] Error for -gsplit-dwarf with RISC-V linker relaxation

kito-cheng accepted this revision. kito-cheng added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D130190/new/ https://reviews.llvm.org/D130190 ___ cfe-commits mailing list cfe-commits@lis

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

kito-cheng added a comment. ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111617/new/ https://reviews.llvm.org/D111617 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

kito-cheng added a comment. @aaron.ballman do you mind give few more look on this patch, we would like gather LGTM from both RISC-V folks and clang folks, thanks :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111617/new/ https://reviews.llvm.org

[PATCH] D124730: [RISCV][NFC] Refactor RISC-V vector intrinsic utils.

kito-cheng updated this revision to Diff 429184. kito-cheng marked 3 inline comments as done. kito-cheng added a comment. Changes: - Address @khchen's comment. - Use new hash scheme for cache the result of computeType. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://r

[PATCH] D124730: [RISCV][NFC] Refactor RISC-V vector intrinsic utils.

kito-cheng added inline comments. Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:55 +// basic vector type, used to compute type info of arguments. +enum class PrimitiveType : uint8_t { + Invalid, khchen wrote: > I think vector is not a primitive

[PATCH] D124730: [RISCV][NFC] Refactor RISC-V vector intrinsic utils.

This revision was automatically updated to reflect the committed changes. Closed by commit rG7ff0bf576b84: [RISCV][NFC] Refactor RISC-V vector intrinsic utils. (authored by kito-cheng). Changed prior to commit: https://reviews.llvm.org/D124730?vs=429184&id=429620#toc Repository: rG LLVM Gith

[PATCH] D125886: [RISCV][NFC] Rename variable in RISCVVEmitter.cpp

kito-cheng created this revision. Herald added subscribers: sunshaoce, VincentWu, luke957, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, niosHD, s

[PATCH] D125886: [RISCV][NFC] Rename variable in RISCVVEmitter.cpp

This revision was automatically updated to reflect the committed changes. Closed by commit rG1467e01f8f69: [RISCV][NFC] Rename variable in RISCVVEmitter.cpp (authored by kito-cheng). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125886/new/ https://

[PATCH] D125893: [RISCV][NFC] Change interface of RVVIntrinsic::getSuffixStr

kito-cheng created this revision. kito-cheng added a reviewer: khchen. Herald added subscribers: sunshaoce, VincentWu, luke957, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones,

[PATCH] D125893: [RISCV][NFC] Change interface of RVVIntrinsic::getSuffixStr

kito-cheng updated this revision to Diff 430390. kito-cheng added a comment. Changes: - Fix dumb typo... Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125893/new/ https://reviews.llvm.org/D125893 Files: clang/include/clang/Support/RISCVVIntrins

[PATCH] D125893: [RISCV][NFC] Change interface of RVVIntrinsic::getSuffixStr

kito-cheng updated this revision to Diff 430391. kito-cheng added a comment. Changes: - clang-format has applied on unexpected part, remove that. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125893/new/ https://reviews.llvm.org/D125893 Files:

[PATCH] D125893: [RISCV][NFC] Change interface of RVVIntrinsic::getSuffixStr

kito-cheng updated this revision to Diff 430911. kito-cheng added a comment. Changes: - Apply @craig.topper's suggestion. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125893/new/ https://reviews.llvm.org/D125893 Files: clang/include/clang/Supp

[PATCH] D125893: [RISCV][NFC] Change interface of RVVIntrinsic::getSuffixStr

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGb166aa833e44: [RISCV][NFC] Change interface of RVVIntrinsic::getSuffixStr (authored by kito-cheng). Repository: rG LLVM Github Monorepo CHANGES S

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

kito-cheng updated this revision to Diff 431646. kito-cheng marked 5 inline comments as done. kito-cheng added a comment. Changes: - Split out several NFC changes to individual NFC patchs. - Moving most code emission logic into RISCVVIntrinsicUtils to prevent require sync manually. - PCH support

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

kito-cheng added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:480 +// They are handled by riscv_vector.h +if (Name == "vsetvli" || Name == "vsetvlimax") + continue; khchen wrote: > I feel little tricky to checking the name here

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