[PATCH] D124509: [RISCV] Fix int16 -> __fp16 conversion code gen

[Kito Cheng via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG41b951c92931: [RISCV] Fix int16 -> __fp16 conversion code 
gen (authored by kito-cheng).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124509/new/

https://reviews.llvm.org/D124509

Files:
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/__fp16-convert.c


Index: clang/test/CodeGen/RISCV/__fp16-convert.c
===================================================================
--- clang/test/CodeGen/RISCV/__fp16-convert.c
+++ clang/test/CodeGen/RISCV/__fp16-convert.c
@@ -6,10 +6,10 @@
 short z;
 // CHECK-LABEL: @bar1(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[TMP0:%.*]] = load i16, ptr @y, align 2
-// CHECK-NEXT:    [[TMP1:%.*]] = call float @llvm.convert.from.fp16.f32(i16 
[[TMP0]])
-// CHECK-NEXT:    [[CONV:%.*]] = fptosi float [[TMP1]] to i16
-// CHECK-NEXT:    store i16 [[CONV]], ptr @z, align 2
+// CHECK-NEXT:    [[TMP0:%.*]] = load half, ptr @y, align 2
+// CHECK-NEXT:    [[CONV:%.*]] = fpext half [[TMP0]] to float
+// CHECK-NEXT:    [[CONV1:%.*]] = fptosi float [[CONV]] to i16
+// CHECK-NEXT:    store i16 [[CONV1]], ptr @z, align 2
 // CHECK-NEXT:    ret void
 //
 void bar1(){
@@ -18,7 +18,9 @@
 // CHECK-LABEL: @bar2(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[TMP0:%.*]] = load i16, ptr @z, align 2
-// CHECK-NEXT:    store i16 [[TMP0]], ptr @y, align 2
+// CHECK-NEXT:    [[CONV:%.*]] = sitofp i16 [[TMP0]] to float
+// CHECK-NEXT:    [[CONV1:%.*]] = fptrunc float [[CONV]] to half
+// CHECK-NEXT:    store half [[CONV1]], ptr @y, align 2
 // CHECK-NEXT:    ret void
 //
 void bar2(){
Index: clang/lib/Basic/Targets/RISCV.h
===================================================================
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -96,6 +96,10 @@
                             DiagnosticsEngine &Diags) override;
 
   bool hasBitIntType() const override { return true; }
+
+  bool useFP16ConversionIntrinsics() const override {
+    return false;
+  }
 };
 class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
 public:



Index: clang/test/CodeGen/RISCV/__fp16-convert.c
===================================================================
--- clang/test/CodeGen/RISCV/__fp16-convert.c
+++ clang/test/CodeGen/RISCV/__fp16-convert.c
@@ -6,10 +6,10 @@
 short z;
 // CHECK-LABEL: @bar1(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[TMP0:%.*]] = load i16, ptr @y, align 2
-// CHECK-NEXT:    [[TMP1:%.*]] = call float @llvm.convert.from.fp16.f32(i16 [[TMP0]])
-// CHECK-NEXT:    [[CONV:%.*]] = fptosi float [[TMP1]] to i16
-// CHECK-NEXT:    store i16 [[CONV]], ptr @z, align 2
+// CHECK-NEXT:    [[TMP0:%.*]] = load half, ptr @y, align 2
+// CHECK-NEXT:    [[CONV:%.*]] = fpext half [[TMP0]] to float
+// CHECK-NEXT:    [[CONV1:%.*]] = fptosi float [[CONV]] to i16
+// CHECK-NEXT:    store i16 [[CONV1]], ptr @z, align 2
 // CHECK-NEXT:    ret void
 //
 void bar1(){
@@ -18,7 +18,9 @@
 // CHECK-LABEL: @bar2(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[TMP0:%.*]] = load i16, ptr @z, align 2
-// CHECK-NEXT:    store i16 [[TMP0]], ptr @y, align 2
+// CHECK-NEXT:    [[CONV:%.*]] = sitofp i16 [[TMP0]] to float
+// CHECK-NEXT:    [[CONV1:%.*]] = fptrunc float [[CONV]] to half
+// CHECK-NEXT:    store half [[CONV1]], ptr @y, align 2
 // CHECK-NEXT:    ret void
 //
 void bar2(){
Index: clang/lib/Basic/Targets/RISCV.h
===================================================================
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -96,6 +96,10 @@
                             DiagnosticsEngine &Diags) override;
 
   bool hasBitIntType() const override { return true; }
+
+  bool useFP16ConversionIntrinsics() const override {
+    return false;
+  }
 };
 class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
 public:

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