[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86Subtarget.h:748 bool hasVLX() const { return HasVLX; } + bool hasFP16() const { return HasFP16; } bool hasPKU() const { return HasPKU; } pengfei wrote: > RKSimon wrote: > > I'm a little

[PATCH] D88398: [X86] Support Intel Key Locker

craig.topper added a comment. In D88398#2857370 , @xiangzhangllvm wrote: > Refine Clang format Did you mean to upload to this old review? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D88398/new/ https://reviews.llvm.org/D88398 ___

[PATCH] D105462: [X86] Add CRC32 feature.

craig.topper added inline comments. Comment at: llvm/lib/Support/X86TargetParser.cpp:531 constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3; -constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1; +constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1 |

[PATCH] D105462: [X86] Add CRC32 feature.

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86.td:84 "Enable SSE 4.2 instructions", - [FeatureSSE41]>; + [FeatureSSE41, FeatureCRC32]>; // Th

[PATCH] D105462: [X86] Add CRC32 feature.

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86.td:84 "Enable SSE 4.2 instructions", - [FeatureSSE41]>; + [FeatureSSE41, FeatureCRC32]>; // Th

[PATCH] D105263: [X86] AVX512FP16 instructions enabling 1/6

craig.topper added inline comments. Comment at: clang/lib/Headers/avx512fp16intrin.h:254 +/// Constructs a 512-bit floating-point vector of [32 x half] from a +///128-bit floating-point vector of [16 x half]. The lower 256 bits +///contain the value of the source vector.

[PATCH] D103527: [Clang][RISCV] Implement vlseg and vlsegff.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D103527/new/ https://reviews.llvm.org/D103527 ___

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoP.td:599 + Sched<[]>; +def SMBB32 : RVPBinary<0b100, 0b010, "smbb32">, + Sched<[]>; It looks like the 0.9.3 spec lists this as an alias of MULSR6

[PATCH] D103465: [OpaquePtr] Track pointee types in Clang

craig.topper added inline comments. Comment at: clang/lib/CodeGen/Address.h:31 + : Address(pointer, nullptr, alignment) {} + Address(llvm::Value *pointer, llvm::Type *PointeeType, CharUnits alignment) + : Pointer(pointer), PointeeType(PointeeType), Alignment(alignment)

[PATCH] D105611: [RISCV] Support overloading for RVV miscellaneous functions.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105611/new/ https://reviews.llvm.org/D105611 ___

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

craig.topper added inline comments. Comment at: llvm/include/llvm/Support/RISCVISAInfo.h:42 + // keep entries in canonical order of extension. + typedef std::map + OrderedExtensionMap; Could this be a sorted vector? Would require a good spot to sort it aft

[PATCH] D103527: [Clang][RISCV] Implement vlseg and vlsegff.

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:836 + clang::CharUnits Align = + CGM.getNaturalTypeAlignment(getContext().getSizeType()); + llvm::Value *V; I don't think this alignment is correct. A vin

[PATCH] D112408: [WIP][RISCV] Add the zve extension according to the v1.0-rc2 spec

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:184 Builder.defineMacro("__riscv_v_min_vlen", Twine(MinVLen)); +Builder.defineMacro("__riscv_v_max_eew", Twine(MaxEew)); +Builder.defineMacro("__riscv_v_max_eew_fp", Twine(MaxEewFp)); -

[PATCH] D112398: [RISCV] Add ABI testing for Float16.

craig.topper added a comment. In D112398#3087183 , @frasercrmck wrote: > It looks as though all checks are checking the same thing? Presumably this is > expected? I wonder if allowing an extra combined check > (`--check-prefixes=CHECK,CHECK-ZFH-ILP32F`

[PATCH] D112534: [PoC][RISCV] Use an attribute to declare C intrinsics with different policy.

craig.topper added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:18614 + auto *PolicyAttr = E->getCalleeDecl()->getAttr(); + size_t PolicyValue; Why size_t? This would be the size_t of the host machine that's building/running the compiler and

[PATCH] D112408: [WIP][RISCV] Add the zve extension according to the v1.0-rc2 spec

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.h:141 + // either v or zve* suppaort v instructions + bool hasStdExtV() const { return HasStdExtV || HasStdExtZve32x; } + bool hasStdExtZve32x() const { return HasStdExtZve32x; } -

[PATCH] D112534: [PoC][RISCV] Use an attribute to declare C intrinsics with different policy.

craig.topper added a comment. I think the concept seems good to me. I'd like @aaron.ballman to review the attribute code. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:18610 unsigned NF = 1; constexpr unsigned TAIL_UNDISTURBED = 0; + constexpr unsigned TAIL_AGNOSTIC = 0b0

[PATCH] D105690: [RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change

craig.topper added a comment. Herald added subscribers: VincentWu, luke957. This patch as committed, deleted 5 test files instead of renaming them. I'm working on restoring them. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105690/new/ https://re

[PATCH] D105690: [RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change

craig.topper added a comment. In D105690#3101129 , @craig.topper wrote: > This patch as committed, deleted 5 test files instead of renaming them. I'm > working on restoring them. Deleted tests have been restored by 670c72f6f70434500d1475e1524a7088814fb

[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.h:170 // D and Zfh imply F. bool hasVInstructionsAnyF() const { return HasStdExtV && hasStdExtF(); } unsigned getMaxInterleaveFactor() const { This needs to be the same

[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:225 +def HasStdExtVIntegerEEW32 +: Predicate<"Subtarget->hasStdExtV() || SubTarget->hasStdExtZve32x()">, + AssemblerPredicate< StdExtV depends on Zve64d which depends on Featu

[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:224 + +def HasStdExtVIntegerEEW32 +: Predicate<"Subtarget->hasStdExtV() || SubTarget->hasStdExtZve32x()">, Can we add the AssemblerPredicate to HasVInstructions and use that? Or we

[PATCH] D112613: [RISCV] Change TARGET_BUILTIN require to zve32x for vector instruction

craig.topper added a comment. The title of this patch isn't descriptive of the changes in this patch. Based on the title I would only expect changes to RISCVEmitter.cpp. Can you clarify the title? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D1126

[PATCH] D112613: [RISCV] Change TARGET_BUILTIN require to zve32x for vector instruction

craig.topper added inline comments. Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c:3 // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileC

[PATCH] D112777: [X86][FP16] add alias for *_fmul_pch intrinsics

craig.topper added a comment. Not directly related to this patch, but why is the suffix _pch and _sch when the instruction names end in CPH and CSH? Why does the name here need to be aligned with mul_ps/pd? This a "complex" multiply which is a different operation. Is gcc also going to add alias

[PATCH] D112777: [X86][FP16] add alias for *_fmul_pch intrinsics

craig.topper added a comment. In D112777#3114560 , @FreddyYe wrote: > In D112777#3114502 , @craig.topper > wrote: > >> Not directly related to this patch, but why is the suffix _pch and _sch when >> the instruct

[PATCH] D112890: headers: optionalise some generated resource headers

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112890/new/ https://reviews.llvm.org/D112890 ___

[PATCH] D113647: [X86] Honor command line features along with cpu_specific attribute

craig.topper created this revision. craig.topper added reviewers: andrew.w.kaylor, erichkeane, pengfei. craig.topper requested review of this revision. Herald added a project: clang. If the feature is on the command line we should honor it for all functions. I don't think we could reliably target

[PATCH] D113647: [X86] Honor command line features along with cpu_specific attribute

craig.topper added a comment. In D113647#3124363 , @erichkeane wrote: > Is there a lit-test that could be added to make sure this happens? We put > this in an llvm-attribute, so it should be checkable. Forgot to git add the file I wrote. Repository:

[PATCH] D113647: [X86] Honor command line features along with cpu_specific attribute

craig.topper updated this revision to Diff 386524. craig.topper added a comment. Add test file Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D113647/new/ https://reviews.llvm.org/D113647 Files: clang/lib/AST/ASTContext.cpp clang/test/CodeGen/at

[PATCH] D113647: [X86] Honor command line features along with cpu_specific attribute

This revision was automatically updated to reflect the committed changes. Closed by commit rG893efd0d665b: [X86] Honor command line features along with cpu_specific attribute (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D1

[PATCH] D96843: [Clang][RISCV] Add vsetvl and vsetvlmax.

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:165 + // and it will have to be provided manually. See IntrinsicTypes below. + bit HasManualCodegen = true; + Why do we need a flag? Can we just make ManualCodegen and Man

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:908 + +// Compute Buitlin types +SmallVector ProtoMaskSeq = ProtoSeq; Buitlin->Bu

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:66 +// element type which is bool +// 0: void type, ignores "t" +// z: size_t, ignores "t" jrtc27 wrote: > khchen wrote: > > jrtc27 wrote: > > > Then why aren't the

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

craig.topper requested changes to this revision. craig.topper added a comment. This revision now requires changes to proceed. Dropping my approval pending @jrtc27 comments. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95016/new/ https://reviews.ll

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

craig.topper added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:567 + // Compute type transformers + for (char I : Transformer.take_front(Transformer.size() - 1)) { +switch (I) { jrtc27 wrote: > craig.topper wrote: > > Can we do Trans

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

craig.topper added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:259-260 + +LMULType &LMULType::operator*=(unsigned RHS) { + this->Log2LMUL = this->Log2LMUL + RHS; + return *this; jrtc27 wrote: > That's not how multiplication works. This i

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:66 +// element type which is bool +// 0: void type, ignores "t" +// z: size_t, ignores "t" jrtc27 wrote: > craig.topper wrote: > > jrtc27 wrote: > > > khchen wrote:

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

craig.topper added a comment. t Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:58-62 + bool IsPointer = false; + // IsConstant indices are "int", but have the constant expression. + bool IsImmediate = false; + // const qualifier. + bool IsConstant = false;

[PATCH] D97825: [RISCV] Use RISCVV_BUILTIN for vector intrinsic checking.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D97825/new/ https://reviews.llvm.org/D97825 _

[PATCH] D97826: [RISCV] Make use of the required features in BuiltinInfo to store that V extension builtins require 'experimental-v'.

craig.topper created this revision. craig.topper added reviewers: evandro, HsiangKai, rogfer01, khchen, arcbbb. Herald added subscribers: StephenFan, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jone

[PATCH] D97826: [RISCV] Make use of the required features in BuiltinInfo to store that V extension builtins require 'experimental-v'.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG201ebf211f97: [RISCV] Make use of the required features in BuiltinInfo to store that V… (authored by craig.topper). Changed prior to commit: https

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

craig.topper added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:58-62 + bool IsPointer = false; + // IsConstant indices are "int", but have the constant expression. + bool IsImmediate = false; + // const qualifier. + bool IsConstant = false; --

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

craig.topper added a comment. LGTM. @jrtc27 are you ok with this? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95016/new/ https://reviews.llvm.org/D95016 ___ cfe-commits mailing list cfe-commits@lists.l

[PATCH] D98265: [NFC] Use llvm::SmallVector to workaround XL compiler problem on AIX

craig.topper added a comment. Maybe this needs to be addressed in the forward declaration in clang/include/clang/Basic/LLVM.h ? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D98265/new/ https://reviews.llvm.org/D98265 _

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM. I think we can address any remaining issues post-commit. I'd like to see us start adding the intrinsics that use this. Repository: rG LLVM Github Monorepo CHANGES SINCE L

[PATCH] D98379: [RISCV] Add additional checking to tablgen RISCVVEmitter requested in D95016.

craig.topper created this revision. craig.topper added reviewers: jrtc27, khchen. Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217,

[PATCH] D98379: [RISCV] Add additional checking to tablgen RISCVVEmitter requested in D95016.

craig.topper updated this revision to Diff 329807. craig.topper added a comment. Turn some llvm_unreachables into fatal errors Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D98379/new/ https://reviews.llvm.org/D98379 Files: clang/utils/TableGen/R

[PATCH] D98379: [RISCV] Add additional checking to tablgen RISCVVEmitter requested in D95016.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG9773cad51939: [RISCV] Add additional checking to tablgen RISCVVEmitter requested in D95016. (authored by craig.topper). Changed prior to commit: h

[PATCH] D98388: [RISCV][Clang] Add RVV vle/vse intrinsic functions.

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:225 +Ops[0] = Builder.CreateBitCast(Ops[0], +llvm::PointerType::getUnqual(ResultType)); }], + ManualCodegenMask= [{ I think you can use ResultType->getP

[PATCH] D96843: [Clang][RISCV] Add vsetvl and vsetvlmax.

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:164 + +// SEW +Builder.defineMacro("__rvv_e8", "0"); I'm not sure if it makes sense to expose these from the compiler. Should we define them in the header instead? They don

[PATCH] D98388: [RISCV][Clang] Add RVV vle/vse intrinsic functions.

craig.topper added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:687 + +unsigned Skew = 0; +if (HasMaskedOffOperand) ``` unsigned Skew = HasMaskedOffOperand ? 1 : 0; ``` unless this needs to get more complicated in a future patch?

[PATCH] D114059: [X86] add 3 missing intrinsics: _mm_(mask/maskz)_cvtpbh_ps

craig.topper added inline comments. Comment at: clang/lib/Headers/avx512vlbf16intrin.h:429 +///A 128-bit vector of [4 x bfloat]. +/// \returns A 128-bit vector of [4 x float] come from convertion of __A +static __inline__ __m128 __DEFAULT_FN_ATTRS128 _mm_cvtpbh_ps(__m128bh __

[PATCH] D114059: [X86] add 3 missing intrinsics: _mm_(mask/maskz)_cvtpbh_ps

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D114059/new/ https://reviews.llvm.org/D114059 ___

[PATCH] D114318: [clang] Add missing CPUID feature bit masks

craig.topper added inline comments. Comment at: clang/lib/Headers/cpuid.h:76 /* Features in %ecx for leaf 1 */ -#define bit_SSE30x0001 -#define bit_PCLMULQDQ 0x0002 -#define bit_PCLMUL bit_PCLMULQDQ /* for gcc compat */ -#define bit_DTES64 0x000

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

craig.topper added inline comments. Comment at: clang/lib/Parse/ParsePragma.cpp:511 +RISCVPragmaHandler = std::make_unique(Actions); +PP.AddPragmaHandler(RISCVPragmaHandler.get()); + } Since this is a clang specific pragma should it be `#pragma clang ris

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

craig.topper added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:69 {"zfh", RISCVExtensionVersion{0, 1}}, +{"zfinx", RISCVExtensionVersion{1, 0}}, +{"zdinx", RISCVExtensionVersion{1, 0}}, Do we need to enforce that these can't be mix

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoD.td:489 +let Predicates = [HasStdExtZdinx] in { +def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D_INX GPRF64Op:$rd, GPRF64Op:$rs, GPRF64Op:$rs)>; Aren't these aliases only valid f

[PATCH] D135938: [X86] Add AVX-VNNI-INT8 instructions.

craig.topper added inline comments. Comment at: llvm/test/CodeGen/X86/avxvnniint8-intrinsics.ll:6 + +declare <4 x i32> @llvm.x86.avx2.vpdpbssd.128(<4 x i32>, <4 x i32>, <4 x i32>) + FreddyYe wrote: > craig.topper wrote: > > Are there tests for commuting? > Hi Cra

[PATCH] D136040: [X86][1/2] Support PREFETCHI instructions

craig.topper added a comment. Can the intrinsics changes be split from this patch so they don't depend on D136145 . There's no reason to block assembler/disassembler support for that. Comment at: clang/lib/Headers/prfchiintrin.h:16 +/// Loads

[PATCH] D136145: [IR][RFC] Restrict read only when cache type of llvm.prefetch is instruction

craig.topper added inline comments. Comment at: clang/lib/Sema/SemaChecking.cpp:7574 - if (NumArgs > 3) + if (NumArgs > 4) return Diag(TheCall->getEndLoc(), Not clear to me that we should be changing the definition of `__builtin_prefetch`. It wouldn't

[PATCH] D136145: [IR][RFC] Restrict read only when cache type of llvm.prefetch is instruction

craig.topper added inline comments. Comment at: clang/lib/Sema/SemaChecking.cpp:7574 - if (NumArgs > 3) + if (NumArgs > 4) return Diag(TheCall->getEndLoc(), craig.topper wrote: > Not clear to me that we should be changing the definition of > `__builtin_

[PATCH] D136040: [X86][1/2] Support PREFETCHI instructions

craig.topper added inline comments. Comment at: clang/lib/Headers/prfchiintrin.h:16 +/// Loads an instruction sequence containing the specified memory address into +///all level cache. +/// craig.topper wrote: > It looks old that this indented differently tha

[PATCH] D136040: [X86][1/2] Support PREFETCHI instructions

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. Herald added a subscriber: StephenFan. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136040/new/ https://reviews.llvm.org/D1360

[PATCH] D135933: [X86] Add CMPCCXADD instructions.

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/X86.cpp:970 .Case("xsaveopt", true) + .Case("cmpccxadd", true) .Default(false); This list is alphabetized or was supposed to be Comment at: clang/lib/Bas

[PATCH] D135933: [X86] Add CMPCCXADD instructions.

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h:1071 return 1; // Check for AVX-512 scatter which has a TIED_TO in the second to last // operand. craig.topper wrote: > This comment is out of da

[PATCH] D136511: [RISCV][clang] Suppor RISC-V vectors in UninitializedValues.

craig.topper created this revision. craig.topper added reviewers: erichkeane, aaron.ballman, kito-cheng, eopXD, rogfer01. Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the

[PATCH] D135933: [X86] Add CMPCCXADD instructions.

craig.topper added inline comments. Comment at: clang/lib/Headers/cmpccxaddintrin.h:19-34 + _CMPCCX_O, /* Overflow. */ + _CMPCCX_NO, /* No overflow. */ + _CMPCCX_B, /* Below. */ + _CMPCCX_NB, /* Not below. */ + _CMPCCX_Z, /* Zero. */ + _CMPCCX_NZ, /* Not zero.

[PATCH] D136570: [RISCV] Add Svnapot extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:394 + "'Svnapot' (NAPOT Translation Contiguity)">; +def HasStdExtSvnapot : Predicate<"Subtarget->hasStdExtSvnapot()">, + AssemblerPredicate<(all_of Fea

[PATCH] D136571: [RISCV] add svinval extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:814 def SFENCE_VMA : Priv_rr<"sfence.vma", 0b0001001>, Sched<[]>; +let Predicates = [HasStdExtSvinval] in { def SINVAL_VMA : Priv_rr<"sinval.vma", 0b0001011>, Sched<[]>; C

[PATCH] D136511: [RISCV][clang] Support RISC-V vectors in UninitializedValues.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGc3ead85e2f1c: [RISCV][clang] Support RISC-V vectors in UninitializedValues. (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANG

[PATCH] D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string

craig.topper updated this revision to Diff 471209. craig.topper added a comment. Add to release notes Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D116735/new/ https://reviews.llvm.org/D116735 Files: clang/lib/Basic/Targets/RISCV.h llvm/docs/R

[PATCH] D116735: [RISCV] Adjust RV64I data layout by using n32:64 in layout string

craig.topper updated this revision to Diff 471385. craig.topper added a comment. Refine ReleaseNotes Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D116735/new/ https://reviews.llvm.org/D116735 Files: clang/lib/Basic/Targets/RISCV.h llvm/docs/Re

[PATCH] D116735: [RISCV] Adjust RV64I data layout by using n32:64 in layout string

This revision was automatically updated to reflect the committed changes. Closed by commit rG974e2e690b40: [RISCV] Adjust RV64I data layout by using n32:64 in layout string (authored by craig.topper). Changed prior to commit: https://reviews.llvm.org/D116735?vs=471385&id=471564#toc Repository:

[PATCH] D137036: [X86] Enable EVEX GFNI instructions without avx512bw.

craig.topper created this revision. craig.topper added reviewers: RKSimon, pengfei. Herald added subscribers: StephenFan, hiraditya. Herald added a project: All. craig.topper requested review of this revision. Herald added projects: clang, LLVM. We only really need avx512bw for masking 256 or 512

[PATCH] D137054: [X86][Driver] Remove stale FIXME. NFC

craig.topper created this revision. craig.topper added reviewers: pengfei, RKSimon. Herald added a subscriber: StephenFan. Herald added a project: All. craig.topper requested review of this revision. Herald added subscribers: cfe-commits, MaskRay. Herald added a project: clang. We use getHostCPUFe

[PATCH] D136930: [RISCV] Support -mcpu/mtune=native

craig.topper added inline comments. Comment at: clang/lib/Driver/ToolChains/Clang.cpp:2190 CmdArgs.push_back("-tune-cpu"); -CmdArgs.push_back(A->getValue()); +if (strcmp(A->getValue(), "native") == 0) + CmdArgs.push_back(Args.MakeArgString(llvm::sys::getHostCPUN

[PATCH] D137036: [X86] Enable EVEX GFNI instructions without avx512bw.

craig.topper added inline comments. Comment at: llvm/test/CodeGen/X86/avx512-gfni-intrinsics.ll:29 +; +; X86NOBW-LABEL: test_vgf2p8affineinvqb_128: +; X86NOBW: # %bb.0: pengfei wrote: > Since we are able to lower the mask version intrinsics, we have 3 choic

[PATCH] D136930: [RISCV] Support -mcpu/mtune=native

craig.topper added inline comments. Comment at: clang/lib/Driver/ToolChains/Clang.cpp:2190 CmdArgs.push_back("-tune-cpu"); -CmdArgs.push_back(A->getValue()); +if (strcmp(A->getValue(), "native") == 0) + CmdArgs.push_back(Args.MakeArgString(llvm::sys::getHostCPUN

[PATCH] D137036: [X86] Enable EVEX GFNI instructions without avx512bw.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG06f640d3fb06: [X86] Enable EVEX GFNI instructions without avx512bw. (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE

[PATCH] D137054: [X86][Driver] Remove stale FIXME. NFC

This revision was automatically updated to reflect the committed changes. Closed by commit rG6fa0e3df97ac: [X86][Driver] Remove stale FIXME. NFC (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137054/new/ https://reviews.ll

[PATCH] D134089: [clang] Mention vector in the description for -mno-implict-float.

craig.topper added a comment. Ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D134089/new/ https://reviews.llvm.org/D134089 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.or

[PATCH] D131134: [X86] Report error if the amx enabled on the non-64-bits target

craig.topper added a comment. In D131134#3715062 , @pengfei wrote: > In D131134#3715024 , @pengfei wrote: > >> In D131134#3714860 , @craig.topper >> wrote: >> >>> Yes AMX

[PATCH] D131677: [clang][RISCV] Fix incorrect ABI lowering for inherited structs under hard-float ABIs

craig.topper added a comment. Remove the WIP note from the end of the description? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D131677/new/ https://reviews.llvm.org/D131677 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://list

[PATCH] D131677: [clang][RISCV] Fix incorrect ABI lowering for inherited structs under hard-float ABIs

craig.topper added inline comments. Comment at: clang/lib/CodeGen/TargetInfo.cpp:10986 +bool Ret = detectFPCCEligibleStructHelper( +B.getType(), CurOff, Field1Ty, Field1Off, Field2Ty, Field2Off); +if (!Ret) jrtc27 wrote: > jrtc27 wrote

[PATCH] D131708: [RISCV] Change how mtune aliases are implemented.

craig.topper created this revision. craig.topper added reviewers: jrtc27, asb, luismarques, kito-cheng. Herald added subscribers: sunshaoce, VincentWu, luke957, jeroen.dobbelaere, StephenFan, vkmr, frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o,

[PATCH] D131448: Introduce iterator sentinel to make graph traversal implementation more efficient and cleaner

craig.topper added inline comments. Comment at: llvm/include/llvm/ADT/iterator_range.h:50 +/// As of C++17, the types of the begin-expr and the end-expr do not have to be +/// the same in 'based-range for loop'. This class represents a tag that should +/// be returned from the 'e

[PATCH] D131708: [RISCV] Change how mtune aliases are implemented.

craig.topper planned changes to this revision. craig.topper added inline comments. Comment at: clang/test/Driver/riscv-cpus.c:27 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=rocket | FileCheck -check-prefix=MTUNE-ROCKET-64 %s -// MTUNE-ROCKET-64: "-tune-cpu" "rocket-r

[PATCH] D131708: [RISCV] Change how mtune aliases are implemented.

craig.topper updated this revision to Diff 452889. craig.topper added a comment. Handle TUNE_PROC in checkTuneCPUKind Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D131708/new/ https://reviews.llvm.org/D131708 Files: clang/lib/Driver/ToolChains/C

[PATCH] D132141: [X86] Emulate _rdrand64_step with two rdrand32 if it is 32bit

craig.topper added inline comments. Comment at: clang/lib/Headers/immintrin.h:301 + unsigned long long tmp; + if (__builtin_ia32_rdrand32_step((unsigned int *)&tmp) & + __builtin_ia32_rdrand32_step(((unsigned int *)&tmp) + 1)) { Should `&` be `&&`? =

[PATCH] D131677: [clang][RISCV] Fix incorrect ABI lowering for inherited structs under hard-float ABIs

craig.topper added inline comments. Comment at: clang/test/CodeGen/RISCV/riscv-abi.cpp:98 + +// Check for correct lowering in the presence of diamoned inheritance. + diamoned -> diamond CHANGES SINCE LAST ACTION https://reviews.llvm.org/D131677/new/ https://

[PATCH] D131708: [RISCV] Change how mtune aliases are implemented.

craig.topper updated this revision to Diff 453746. craig.topper added a comment. Add release note about sifive-7-rv32/64 being removed Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D131708/new/ https://reviews.llvm.org/D131708 Files: clang/docs/R

[PATCH] D130586: [cmake] Use `CMAKE_INSTALL_LIBDIR` too

craig.topper added a comment. I seem to be unable to pass `check-clang` after this. A lot of tests fail because they can't find headers they need. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D130586/new/ https://reviews.llvm.org/D130586

[PATCH] D131708: [RISCV] Change how mtune aliases are implemented.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG37c47b2cacae: [RISCV] Change how mtune aliases are implemented. (authored by craig.topper). Changed prior to commit: https://reviews.llvm.org/D131

[PATCH] D132192: [RISCV] Add '32bit' feature to rv32 only builtins.

craig.topper created this revision. craig.topper added reviewers: asb, luismarques, reames, kito-cheng. Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinM

[PATCH] D132197: [RISCV] Use Triple::isRISCV/isRISCV32/isRISCV64 helps in some places. NFC

craig.topper created this revision. craig.topper added reviewers: kito-cheng, asb, luismarques, reames, gbenyei. Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult

[PATCH] D132197: [RISCV] Use Triple::isRISCV/isRISCV32/isRISCV64 helps in some places. NFC

craig.topper added inline comments. Comment at: clang/lib/Driver/ToolChains/Linux.cpp:741 getTriple().getArch() == llvm::Triple::thumbeb; - const bool IsRISCV64 = getTriple().getArch() == llvm::Triple::riscv64; + const bool IsRISCV64 = getTriple().isRI

[PATCH] D132197: [RISCV] Use Triple::isRISCV/isRISCV32/isRISCV64 helps in some places. NFC

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG1a60e003df8a: [RISCV] Use Triple::isRISCV/isRISCV32/isRISCV64 helps in some places. NFC (authored by craig.topper). Changed prior to commit: http

[PATCH] D132141: [X86] Emulate _rdrand64_step with two rdrand32 if it is 32bit

craig.topper added inline comments. Comment at: clang/lib/Headers/immintrin.h:300 +{ + unsigned int lo, hi; + if (__builtin_ia32_rdrand32_step(&lo) && __builtin_ia32_rdrand32_step(&hi)) { variable names in intrinsic headers must start with 2 underscores. Repo

[PATCH] D132141: [X86] Emulate _rdrand64_step with two rdrand32 if it is 32bit

craig.topper added inline comments. Comment at: clang/lib/Headers/immintrin.h:300 +{ + unsigned int lo, hi; + if (__builtin_ia32_rdrand32_step(&lo) && __builtin_ia32_rdrand32_step(&hi)) { craig.topper wrote: > variable names in intrinsic headers must start with

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