[clang] [llvm] [RISCV] Implement Clang Builtins for XAndesPerf Extension (PR #147018)

wangpc-pp wrote: Should we document this in https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc? https://github.com/llvm/llvm-project/pull/147018 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-

[clang] [llvm] [RISCV] Implement Clang Builtins for XAndesPerf Extension (PR #147018)

@@ -0,0 +1,159 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple riscv32 -target-feature +xandesperf -emit-llvm %s -o - \ wangpc-pp wrote: Run mem2ssa? https://github.com/llvm/llvm-project/pull/147018

[clang] [llvm] [RISCV] Implement Clang Builtins for XAndesPerf Extension (PR #147018)

@@ -0,0 +1,29 @@ +//==- BuiltinsRISCVXAndes.td - RISC-V Andes Builtin database -*- C++ -*-==// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apa

[clang] [llvm] [RISCV] Add Andes XAndesVSIntLoad (Andes Vector INT4 Load) extension (PR #147005)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/147005 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][MC] Add MC support of Zibi experimental extension (PR #127463)

@@ -0,0 +1,44 @@ +//===-- RISCVInstrInfoZibi.td - 'Zibi' instructions *- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apa

[clang] [llvm] [RISCV][MC] Add MC support of Zibi experimental extension (PR #127463)

wangpc-pp wrote: > > > > This adds the support of Zibi v0.1 experimental extension. > > > > References: > > > > > > > > * > > > > https://lf-riscv.atlassian.net/wiki/spaces/USXX/pages/599261201/Branch+with+Immediate+Zibi+Ratification+Plan > > > > > > > > > I cannot for the life of me find an

[clang] [llvm] [RISCV] Add big-endian support to RISC-V backend (PR #146534)

https://github.com/wangpc-pp commented: How are we going to verify the correctness? Does qemu support big-endian riscv64? https://github.com/llvm/llvm-project/pull/146534 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/c

[clang] [RISCV] Decrease the capacity of SmallVector to 6. NFC. (PR #145650)

https://github.com/wangpc-pp approved this pull request. https://github.com/llvm/llvm-project/pull/145650 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Fix crash on VLS calling convention (PR #145489)

@@ -143,52 +143,82 @@ void __attribute__((riscv_vls_cc)) test_too_large(int32x64_t arg) {} // CHECK-LLVM: define dso_local riscv_vls_cc(256) void @test_too_large_256( noundef %arg.coerce) void __attribute__((riscv_vls_cc(256))) test_too_large_256(int32x64_t arg) {} -// CHECK

[clang] [llvm] [RISCV] Add Andes AX45MPV processor definition (PR #145267)

@@ -0,0 +1,33 @@ +// RUN: %clang --target=riscv64 -mcpu=andes-ax45mpv --print-enabled-extensions | FileCheck %s wangpc-pp wrote: Is that necessary to add a new file for each CPU? https://github.com/llvm/llvm-project/pull/145267 _

[clang] [llvm] [RISCV] Add Andes AX45MPV processor definition (PR #145267)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/145267 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Andes AX45MPV processor definition (PR #145267)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/145267 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [AArch64] Add option -msve-streaming-vector-bits= . (PR #144611)

@@ -1034,9 +1034,16 @@ class TargetInfo : public TransferrableTargetInfo, /// set of primary and secondary targets. virtual llvm::SmallVector getTargetBuiltins() const = 0; + enum class ArmStreamingKind { +NotStreaming, +StreamingCompatible, +Streaming, + };

[clang] [AArch64] Add option -msve-streaming-vector-bits= . (PR #144611)

@@ -1034,9 +1034,16 @@ class TargetInfo : public TransferrableTargetInfo, /// set of primary and secondary targets. virtual llvm::SmallVector getTargetBuiltins() const = 0; + enum class ArmStreamingKind { +NotStreaming, +StreamingCompatible, +Streaming, + };

[clang] [llvm] [RISCV] Fix incorrect predicates for fp16 permutation intrinsics (PR #144063)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/144063 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Remove B and Zbc extension from Andes series cpus. (PR #144022)

wangpc-pp wrote: Not related to this PR, but I'd like to raise the question here: For configurable cores, what is the best way to specify the features? `-mcpu` is meant to support the base configuration, but how can we specify the additional optional extensions? Apparently, failing back to `-m

[clang] [RISCV] Use StringRef for RequiredExtensions in RVVIntrinsicDef (PR #143503)

https://github.com/wangpc-pp approved this pull request. https://github.com/llvm/llvm-project/pull/143503 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm][RISCV] Handle required features of intrinsic correctly (PR #143062)

https://github.com/wangpc-pp approved this pull request. https://github.com/llvm/llvm-project/pull/143062 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add SiFive X390 processor definition (PR #142517)

https://github.com/wangpc-pp approved this pull request. https://github.com/llvm/llvm-project/pull/142517 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add shlcofideleg extension (PR #141572)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/141572 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Handle target features correctly in CheckBuiltinFunctionCall (PR #141548)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/141548 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Handle target features correctly in CheckBuiltinFunctionCall (PR #141548)

@@ -0,0 +1,11 @@ +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +zvknha %s -fsyntax-only -verify + +#include + +// expected-no-diagnostics + +__attribute__((target("arch=+zvl128b"))) +void test_zvk_features(vuint32m1_t vd, vuint32m1_t v

[clang] [llvm] [RISCV] Add MC layer support for XSfmm*. (PR #133031)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/133031 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISC-V] Allow intrinsics to be used with any pointer type. (PR #139634)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/139634 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

@@ -0,0 +1,153 @@ +//===-- RISCVInstrInfoQ.td - RISC-V 'Q' instructions ---*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

@@ -291,6 +291,13 @@ def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">, AssemblerPredicate<(all_of FeatureStdExtD), "'D' (Double-Precision Floating-Point)">; +def FeatureStdExtQ +: RISCVExtension<2, 2, "Quad-Precisio

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/139519 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

@@ -75,7 +75,7 @@ def ZhinxminZdinxExt: ExtInfo<"_INX", "Zfinx", ?, ?, FPR32INX, FPR64INX, FPR16INX>; def ZhinxZdinx32Ext : ExtInfo<"_IN32X", "ZdinxGPRPairRV32", [HasStdExtZhinx, HasStdExtZdinx, IsRV32]

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

@@ -147,6 +147,13 @@ def ntl_load : RISCVBuiltin<"void(...)">; def ntl_store : RISCVBuiltin<"void(...)">; } // Features = "zihintntl", Attributes = [CustomTypeChecking] +//===--===// +// Zihintpause extension.

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

@@ -1886,6 +1886,12 @@ let TargetPrefix = "riscv" in { def int_riscv_vsm3me : RISCVBinaryAAXUnMasked; } // TargetPrefix = "riscv" +// Zihintpause extensions +//===--===// +let TargetPrefix = "riscv" in { -

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

https://github.com/wangpc-pp approved this pull request. LGTM with nits. https://github.com/llvm/llvm-project/pull/139519 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

@@ -2198,6 +2198,15 @@ def : Pat<(binop_allwusers GPR:$rs1, immop_oneuse:$rs2), def : Pat<(i64 (add GPR:$rs1, negImm:$rs2)), (SUB GPR:$rs1, negImm:$rs2)>; } +//===--===// +// Zihintpause +//===---

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

@@ -0,0 +1,14 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple riscv32 -target-feature +zihintpause -emit-llvm %s -o - \ +// RUN: | FileCheck %s + +#include wangpc-pp wrote: Remove this include.

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

@@ -0,0 +1,14 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple riscv32 -target-feature +zihintpause -emit-llvm %s -o - \ wangpc-pp wrote: riscv64 RUN as well. https://github.com/llvm/llvm-project/pull

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

https://github.com/wangpc-pp commented: Do we need a header for it (just like others in https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc#intrinsic-functions)? https://github.com/llvm/llvm-project/pull/139519 ___ cfe-commits ma

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/139519 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

@@ -0,0 +1,17 @@ +//===-- RISCVInstrInfoZihintpause.td ---*- tablegen -*-===// wangpc-pp wrote: This file is too small, we may not need a standalone file for `Zihintpause`. You can put this pattern to llvm/lib/Target/RISCV/RISCVInstrInfo.td

[clang] [llvm] [RISCV] Add `zihintpause` LLVM/Clang intrinsic (PR #139519)

@@ -147,6 +147,13 @@ def ntl_load : RISCVBuiltin<"void(...)">; def ntl_store : RISCVBuiltin<"void(...)">; } // Features = "zihintntl", Attributes = [CustomTypeChecking] +//===--===// +// Zihintpause extension.

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

https://github.com/wangpc-pp commented: Thanks! The PR is neater now! Please add a ReleaseNote as well. https://github.com/llvm/llvm-project/pull/139369 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/list

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/139369 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

@@ -131,20 +131,22 @@ def FPR32INX : RegisterOperand { // The DAGOperand can be unset if the predicates are not enough to define it. class ExtInfo predicates, ValueType primaryvt, DAGOperand primaryty, DAGOperand f32ty, - DAGOperand f64ty, DAGOperand

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

@@ -0,0 +1,153 @@ +//===-- RISCVInstrInfoQ.td - RISC-V 'Q' instructions ---*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/139369 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

@@ -43,34 +43,43 @@ def WriteAtomicSTD : SchedWrite;// Atomic store double word def WriteFAdd16 : SchedWrite;// 16-bit floating point addition/subtraction def WriteFAdd32 : SchedWrite;// 32-bit floating point addition/subtraction def WriteFAdd64 : Sc

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

@@ -131,20 +131,22 @@ def FPR32INX : RegisterOperand { // The DAGOperand can be unset if the predicates are not enough to define it. class ExtInfo predicates, ValueType primaryvt, DAGOperand primaryty, DAGOperand f32ty, - DAGOperand f64ty, DAGOperand

[clang] [llvm] [RISCV][MC] Add support for Q extension (PR #139369)

https://github.com/wangpc-pp commented: We should support `Zfa+Q` as well (this can be a follow-up). https://github.com/llvm/llvm-project/pull/139369 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinf

[clang] [llvm] [RISCV] Add Andes XAndesVPackFPH (Andes Vector Packed FP16) extension. (PR #138827)

https://github.com/wangpc-pp approved this pull request. https://github.com/llvm/llvm-project/pull/138827 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Fix generation of DWARF info for vector segmented types (PR #137941)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/137941 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add processor definition for SiFive P870 (PR #137725)

@@ -365,6 +365,32 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model, TuneVXRMPipelineFlush, TunePostRAScheduler]>; +def SIFIVE_P870 : RISCVProcessorModel<"sifive-p870", NoSched

[clang] [llvm] [RISCV] Allow `Zicsr`/`Zifencei` to duplicate with `g` (PR #136842)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/136842 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Allow `Zicsr`/`Zifencei` to duplicate with `g` (PR #136842)

wangpc-pp wrote: /cherry-pick 6c3373534305a2ce23dd939344dd0a387a09fe88 https://github.com/llvm/llvm-project/pull/136842 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Allow `Zicsr`/`Zifencei` to duplicate with `g` (PR #136842)

wangpc-pp wrote: According to the sync-up meeting, we can proceed this patch as-is. I will merge this in a few days. I added back the release note. @asb https://github.com/llvm/llvm-project/pull/136842 ___ cfe-commits mailing list cfe-commits@lists.l

[clang] [llvm] [RISCV] Allow `Zicsr`/`Zifencei` to duplicate with `g` (PR #136842)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/136842 >From 723976e74398e12252a599e3aabb05ec8f2515ab Mon Sep 17 00:00:00 2001 From: Pengcheng Wang Date: Wed, 23 Apr 2025 18:19:41 +0800 Subject: [PATCH 1/5] [RISCV] Allow `Zicsr`/`Zifencei` to duplicate with `g` T

[clang] [llvm] [RISCV] Allow `Zicsr`/`Zifencei` to duplicate with `g` (PR #136842)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/136842 >From 723976e74398e12252a599e3aabb05ec8f2515ab Mon Sep 17 00:00:00 2001 From: Pengcheng Wang Date: Wed, 23 Apr 2025 18:19:41 +0800 Subject: [PATCH 1/4] [RISCV] Allow `Zicsr`/`Zifencei` to duplicate with `g` T

[clang] [llvm] [RISCV] Add support for Ziccamoc (PR #136694)

@@ -167,6 +167,7 @@ Changes to the RISC-V Backend * Adds assembler support for ``.option exact``, which disables automatic compression, and branch and linker relaxation. This can be disabled with ``.option noexact``, which is also the default. +* Support was added for the

[clang] [llvm] [RISCV] Allow `Zicsr`/`Zifencei` to duplicate with `g` (PR #136842)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/136842 >From 723976e74398e12252a599e3aabb05ec8f2515ab Mon Sep 17 00:00:00 2001 From: Pengcheng Wang Date: Wed, 23 Apr 2025 18:19:41 +0800 Subject: [PATCH] [RISCV] Allow `Zicsr`/`Zifencei` to duplicate with `g` This

[clang] [llvm] [RISCV] Allow `Zicsr`/`Zifencei` to duplicate with `g` (PR #136842)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/136842 This matches GCC and we supported it in LLVM 17/18. Fixes #136803 >From e133a5fc0091ec045a0ea0114d553c72e8f33e51 Mon Sep 17 00:00:00 2001 From: Pengcheng Wang Date: Wed, 23 Apr 2025 18:19:41 +0800 Subject:

[clang] [llvm] [RISCV] Add Andes A45/AX45 processor definition (PR #136832)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/136832 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Andes N45/NX45 processor definition (PR #136670)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/136670 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add support for Ziccamoc (PR #136694)

https://github.com/wangpc-pp commented: Release notes? https://github.com/llvm/llvm-project/pull/136694 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add support for Ziccamoc (PR #136694)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/136694 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Add Support for Ziccamoc (PR #136694)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/136694 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu-V2R2 (PR #123193)

https://github.com/wangpc-pp approved this pull request. LGTM! Thanks for the insistence! https://github.com/llvm/llvm-project/pull/123193 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commi

[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu-V2R2 (PR #123193)

wangpc-pp wrote: LGTM in general, but I have a question here: can you clarify the naming strategy? The name used in `-mcpu` is `xiangshan-kunminghu`, which corresponds to the `V2R2` version now apparently. Then, will there be `V2R3`/`V3R2`/...? If so, what should we use in `-mcpu`? https://gi

[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu-V2R2 (PR #123193)

@@ -558,6 +558,34 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", TuneZExtWFusion, TuneShiftedZExtWFusion]>; +def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunmi

[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu-V2R2 (PR #123193)

@@ -558,6 +558,34 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", TuneZExtWFusion, TuneShiftedZExtWFusion]>; +def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunmi

[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu-V2R2 (PR #123193)

@@ -558,6 +558,34 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", TuneZExtWFusion, TuneShiftedZExtWFusion]>; +def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunmi

[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu-V2R2 (PR #123193)

@@ -126,6 +126,7 @@ Changes to the PowerPC Backend Changes to the RISC-V Backend - + wangpc-pp wrote: Remove this extra blank line. https://github.com/llvm/llvm-project/pull/123193 ___ c

[clang] [llvm] [RISCV] Fix xmipscmov extension name (PR #135647)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/135647 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][NFC] Make generated intrinsic records more human-readable (PR #133710)

wangpc-pp wrote: > @wangpc-pp you might want to revert this or fix it soon. Reverted. Thanks! https://github.com/llvm/llvm-project/pull/133710 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-

[clang] [RISCV][NFC] Make generated intrinsic records more human-readable (PR #133710)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/133710 >From 031ef3fa34f0448dc9743135802e7c6be2025442 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Mon, 31 Mar 2025 20:12:40 +0800 Subject: [PATCH 1/3] [RISCV][NFC] Make generated intrinsic records more human

[clang] [RISCV][NFC] Make generated intrinsic records more human-readable (PR #133710)

https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/133710 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][NFC] Make generated intrinsic records more human-readable (PR #133710)

wangpc-pp wrote: > Does this have any effect on the build time of the compiler? This file is > already large and I assume this significantly increases the size. Yes, the .inc size is 6 times larger. I don't know how to assess the impact, theoretically the time to read file and tokenize will in

[clang] [RISCV][NFC] Make generated intrinsic records more human-readable (PR #133710)

wangpc-pp wrote: ping. https://github.com/llvm/llvm-project/pull/133710 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Remove experimental from Sdext and Sdtrig which are ratified. (PR #132529)

https://github.com/wangpc-pp approved this pull request. https://github.com/llvm/llvm-project/pull/132529 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

@@ -176,6 +176,13 @@ def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">, "'Zicfiss' (Shadow stack)">; def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">; +def FeatureStdExtZilsd +: RISCVExtension<1

[clang] [llvm] Vectorize: Support fminimumnum and fmaximumnum (PR #131781)

@@ -0,0 +1,1059 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 wangpc-pp wrote: Precommit this test. https://github.com/llvm/llvm-project/pull/131781 ___ cfe-commit

[clang] [RISCV][NFC] Make generated intrinsic records more human-readable (PR #133710)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/133710 >From 81c45d6226d217197ae7b6c35e9ace22027cb7a5 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Mon, 31 Mar 2025 20:12:40 +0800 Subject: [PATCH 1/2] [RISCV][NFC] Make generated intrinsic records more human

[clang] [RISCV][NFC] Make generated intrinsic records more human-readable (PR #133710)

wangpc-pp wrote: Examples: ```cpp {/*Name=*/"vbrev_v", /*OverloadedName=*/"vbrev", /*RequiredExtensions=*/{RVV_REQ_Zvbb}, /*PrototypeIndex=*/417, /*SuffixIndex=*/47, /*OverloadedSuffixIndex=*/0, /*PrototypeLength=*/2, /*SuffixLength=*/1, /*OverloadedSuffixSize=*/0, /*TypeRangeMask=*/15, /*Log

[clang] [RISCV][NFC] Make generated intrinsic records more human-readable (PR #133710)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/133710 We add comment markers and print enum names instead of numbers. For required extensions, we print the feature list instead of raw bits. >From 81c45d6226d217197ae7b6c35e9ace22027cb7a5 Mon Sep 17 00:00:00 2001

[clang] [llvm] Vectorize: Support fminimumnum and fmaximumnum (PR #131781)

@@ -0,0 +1,1059 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 +; RUN: opt --passes=loop-vectorize --mtriple=riscv64 -mattr="+zvfh,+v" -S < %s | FileCheck %s --check-prefix=RV64 +; RUN: opt --passes=loop-vectorize --mtriple=aa

[clang] [llvm] Vectorize: Support fminimumnum and fmaximumnum (PR #131781)

@@ -962,6 +962,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, static const unsigned ZvfhminZvfbfminPromoteOps[] = { ISD::FMINNUM, ISD::FMAXNUM, +ISD::FMINIMUMNUM, wangpc-pp wrote: RISCV changes should be in

[clang] [llvm] Vectorize: Support fminimumnum and fmaximumnum (PR #131781)

https://github.com/wangpc-pp commented: I think you should provide LLVM IR tests in `llvm/test/Transforms/LoopVectorize/**` instead of Clang tests. https://github.com/llvm/llvm-project/pull/131781 ___ cfe-commits mailing list cfe-commits@lists.llvm.or

[clang] [llvm] [RISCV] Add MC layer support for XSfmm*. (PR #133031)

wangpc-pp wrote: > > but won't merge them until they are ratified just like Zvzip/Zvabd/Zibimm > > I think this patch is supported to be the vendor instruction set of `SiFive > Xsfmm* Attached Matrix Extensions` if I understand correctly of this PR. > > AME is another issue that we don’t have

[clang] [llvm] [RISCV] Add MC layer support for XSfmm*. (PR #133031)

@@ -830,3 +830,16 @@ def : RISCVRegisterClass<[XLenVT], 32, (add SF_VCIX_STATE)> { let RegInfos = XLenRI; let isAllocatable = 0; } + +//===--===// +// XSfmmbase tiles +//===

[clang] [RISCV] Make RequiredExtensions for intrinsics scalable to more than 32 extensions. NFC (PR #132895)

@@ -45,7 +45,7 @@ struct SemaRecord { unsigned Log2LMULMask; // Required extensions for this intrinsic. - uint32_t RequiredExtensions; + uint32_t RequiredExtensions[(RVV_REQ_Experimental + 31) / 32]; wangpc-pp wrote: RVV_REQ_Experimental->RVV_REQ_NUM?

[clang] [RISCV] Make RequiredExtensions for intrinsics scalable to more than 32 extensions. NFC (PR #132895)

@@ -519,6 +517,9 @@ struct RVVIntrinsicRecord { // e.g. vadd const char *OverloadedName; + // Required target features for this intrinsic. + uint32_t RequiredExtensions[(RVV_REQ_NUM + 31) / 32]; wangpc-pp wrote: I wonder if we can use `FeatureBitset` he

[clang] [clang][RISCV] Fix RUN line and rename test name for pr129995 (PR #132676)

https://github.com/wangpc-pp approved this pull request. https://github.com/llvm/llvm-project/pull/132676 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Implement the implications of C extension (PR #132259)

https://github.com/wangpc-pp approved this pull request. I'd like to give it a LGTM. :-) https://github.com/llvm/llvm-project/pull/132259 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commit

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

@@ -176,6 +176,13 @@ def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">, "'Zicfiss' (Shadow stack)">; def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">; +def FeatureStdExtZilsd +: RISCVExtension<1

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

https://github.com/wangpc-pp commented: Please add a ReleaseNote. https://github.com/llvm/llvm-project/pull/131094 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

@@ -19,31 +19,29 @@ # TODO: more exhaustive testing of immediate encoding. -# CHECK-ASM-AND-OBJ: c.ldsp ra, 0(sp) -# CHECK-ASM: encoding: [0x82,0x60] +# CHECK-ASM-AND-OBJ: c.ldsp s0, 0(sp) +# CHECK-ASM: encoding: [0x02,0x64] # CHECK-NO-EXT: error: instruction requires the f

[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/131094 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Rename variable name in SemaRISCV. NFC (PR #131261)

https://github.com/wangpc-pp approved this pull request. https://github.com/llvm/llvm-project/pull/131261 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][Sema] Add feature check for target attribute to VSETVL intrinsics (PR #126064)

https://github.com/wangpc-pp approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/126064 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)

wangpc-pp wrote: Agree, we should try the RISCVInsertVSETVLI approach. https://github.com/llvm/llvm-project/pull/128636 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)

wangpc-pp wrote: > > I am not familiar with the target attribute implementation, can we get the > > list of function features here and add the clobbers at: > > https://github.com/llvm/llvm-project/blob/6d93280aabc2fd132f54e5aa615d25abeadabe7b/clang/lib/CodeGen/CGStmt.cpp#L3087-L3093 > > > > cc

[clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)

wangpc-pp wrote: I am not familiar with the target attribute implementation, can we get the list of function features here and add the clobbers at: https://github.com/llvm/llvm-project/blob/6d93280aabc2fd132f54e5aa615d25abeadabe7b/clang/lib/CodeGen/CGStmt.cpp#L3087-L3093 cc @topperc @4vtomat

[clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)

wangpc-pp wrote: > I think what @wangpc-pp advocated here (please correct me if I'm wrong) was > that user should be responsible annotating these registers as clobbered so > that we have more freedom on scheduling when the inline assembly is not using > any vector instructions. While other app

[clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)

https://github.com/wangpc-pp commented: I see. But what's the difference if we add `vl/vtype` to the list of clobbered registers explicitly in C/C++ asm statements? https://github.com/llvm/llvm-project/pull/128636 ___ cfe-commits mailing list cfe-comm

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