================
@@ -131,20 +131,22 @@ def FPR32INX : RegisterOperand<GPRF32> {
// The DAGOperand can be unset if the predicates are not enough to define it.
class ExtInfo<string suffix, string space, list<Predicate> predicates,
ValueType primaryvt, DAGOperand primaryty, DAGOperand f32ty,
- DAGOperand f64ty, DAGOperand f16ty> {
+ DAGOperand f64ty, DAGOperand f16ty, DAGOperand f128ty> {
list<Predicate> Predicates = predicates;
string Suffix = suffix;
string Space = space;
DAGOperand PrimaryTy = primaryty;
DAGOperand F16Ty = f16ty;
DAGOperand F32Ty = f32ty;
DAGOperand F64Ty = f64ty;
+ DAGOperand F128Ty = f128ty;
----------------
wangpc-pp wrote:
I think we don't have `Zqinx`?
> In the future, an RV64Zqinx quad-precision extension could be defined
> analogously to RV32Zdinx. An RV32Zqinx extension could also be defined but
> would require quad-register groups.
https://github.com/llvm/llvm-project/pull/139369
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