[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu-V2R2 (PR #123193)

[Pengcheng Wang via cfe-commits]

================
@@ -558,6 +558,34 @@ def XIANGSHAN_NANHU : 
RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneZExtWFusion,
                                             TuneShiftedZExtWFusion]>;
 
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
+                                              NoSchedModel,
+                                              !listconcat(RVA23S64Features,
+                                              [FeatureStdExtZicsr,
----------------
wangpc-pp wrote:

Yes you can remove it because the F/D extensions imply `Zicsr`. I can add it 
explicitly to the RISCVProfiles.td to avoid future misleadings.

https://github.com/llvm/llvm-project/pull/123193
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