[clang] [llvm] [RISCV] Add processor definition for SiFive P870 (PR #137725)

[Pengcheng Wang via cfe-commits]

================
@@ -365,6 +365,32 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", 
SiFiveP600Model,
                                        TuneVXRMPipelineFlush,
                                        TunePostRAScheduler]>;
 
+def SIFIVE_P870 : RISCVProcessorModel<"sifive-p870", NoSchedModel,
+                                      !listconcat(RVA23U64Features,
+                                      [FeatureStdExtZama16b,
+                                       FeatureStdExtZfh,
+                                       FeatureStdExtZifencei,
+                                       FeatureStdExtZihintntl,
----------------
wangpc-pp wrote:

Aha, I always thought `Zifencei` is in userspace profile. It turns out my 
understanding is wrong.

https://github.com/llvm/llvm-project/pull/137725
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits